From 86e3b735cd803cc22c9eae15d99ce9df5956aae6 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Mon, 20 Apr 2020 15:15:05 -0400 Subject: [PATCH 001/910] [hip] Claim builtin type `__float128` supported if the host target supports it. Reviewers: tra, yaxunl Subscribers: jvesely, nhaehnle, kerbowa, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D78513 --- clang/lib/Basic/Targets/AMDGPU.cpp | 13 +++++++++++++ clang/test/SemaCUDA/amdgpu-f128.cu | 4 ++++ 2 files changed, 17 insertions(+) create mode 100644 clang/test/SemaCUDA/amdgpu-f128.cu diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index 3fd9008e4660..b9d7640a10b8 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -363,4 +363,17 @@ void AMDGPUTargetInfo::setAuxTarget(const TargetInfo *Aux) { copyAuxTarget(Aux); LongDoubleFormat = SaveLongDoubleFormat; Float128Format = SaveFloat128Format; + // For certain builtin types support on the host target, claim they are + // support to pass the compilation of the host code during the device-side + // compilation. + // FIXME: As the side effect, we also accept `__float128` uses in the device + // code. To rejct these builtin types supported in the host target but not in + // the device target, one approach would support `device_builtin` attribute + // so that we could tell the device builtin types from the host ones. The + // also solves the different representations of the same builtin type, such + // as `size_t` in the MSVC environment. + if (Aux->hasFloat128Type()) { + HasFloat128 = true; + Float128Format = DoubleFormat; + } } diff --git a/clang/test/SemaCUDA/amdgpu-f128.cu b/clang/test/SemaCUDA/amdgpu-f128.cu new file mode 100644 index 000000000000..9a0212cdb93c --- /dev/null +++ b/clang/test/SemaCUDA/amdgpu-f128.cu @@ -0,0 +1,4 @@ +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -fsyntax-only -verify %s + +// expected-no-diagnostics +typedef __float128 f128_t; -- GitLab From 163bd9d858008c6f48ec38f3ba857faf9bd6c543 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 21 Apr 2020 16:09:17 -0400 Subject: [PATCH 002/910] Fix `-Wpedantic` warnings. NFC. --- llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp index 2655ef304787..32f37c6d04cf 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp @@ -319,7 +319,7 @@ LLVM_NODISCARD Value *Negator::visit(Value *V, unsigned Depth) { } llvm_unreachable("Can't get here. We always return from switch."); -}; +} LLVM_NODISCARD Optional Negator::run(Value *Root) { Value *Negated = visit(Root, /*Depth=*/0); @@ -331,7 +331,7 @@ LLVM_NODISCARD Optional Negator::run(Value *Root) { return llvm::None; } return std::make_pair(ArrayRef(NewInstructions), Negated); -}; +} LLVM_NODISCARD Value *Negator::Negate(bool LHSIsZero, Value *Root, InstCombiner &IC) { @@ -374,4 +374,4 @@ LLVM_NODISCARD Value *Negator::Negate(bool LHSIsZero, Value *Root, // And return the new root. return Res->second; -}; +} -- GitLab From e2b53a4c05cbeeb4a2f1231ba16d3de4ce45ba62 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 17 Apr 2020 21:09:16 -0500 Subject: [PATCH 003/910] [Attributor][NFC] Remove obsolete option from tests Since D76871 it is sufficient to run `opt -atributor` or `-attributor-cgscc`. --- .../ArgumentPromotion/2008-02-01-ReturnAttrs.ll | 8 ++++---- .../ArgumentPromotion/2008-07-02-array-indexing.ll | 8 ++++---- .../ArgumentPromotion/2008-09-07-CGUpdate.ll | 8 ++++---- .../ArgumentPromotion/2008-09-08-CGUpdateSelfEdge.ll | 8 ++++---- .../Attributor/ArgumentPromotion/X86/attributes.ll | 8 ++++---- .../ArgumentPromotion/X86/min-legal-vector-width.ll | 8 ++++---- .../Attributor/ArgumentPromotion/X86/thiscall.ll | 8 ++++---- .../ArgumentPromotion/aggregate-promote.ll | 8 ++++---- .../Attributor/ArgumentPromotion/alignment.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/attrs.ll | 8 ++++---- .../Attributor/ArgumentPromotion/basictest.ll | 8 ++++---- .../Attributor/ArgumentPromotion/byval-2.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/byval.ll | 8 ++++---- .../Attributor/ArgumentPromotion/chained.ll | 8 ++++---- .../Attributor/ArgumentPromotion/control-flow.ll | 8 ++++---- .../Attributor/ArgumentPromotion/control-flow2.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/crash.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/dbg.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/fp80.ll | 8 ++++---- .../Attributor/ArgumentPromotion/inalloca.ll | 8 ++++---- .../ArgumentPromotion/live_called_from_dead.ll | 8 ++++---- .../ArgumentPromotion/live_called_from_dead_2.ll | 8 ++++---- .../Attributor/ArgumentPromotion/musttail.ll | 8 ++++---- .../Attributor/ArgumentPromotion/naked_functions.ll | 8 ++++---- .../ArgumentPromotion/nonzero-address-spaces.ll | 8 ++++---- .../Attributor/ArgumentPromotion/pr27568.ll | 8 ++++---- .../Attributor/ArgumentPromotion/pr32917.ll | 8 ++++---- .../ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll | 8 ++++---- .../Attributor/ArgumentPromotion/profile.ll | 8 ++++---- .../Attributor/ArgumentPromotion/reserve-tbaa.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/sret.ll | 8 ++++---- .../Transforms/Attributor/ArgumentPromotion/tail.ll | 8 ++++---- .../Attributor/ArgumentPromotion/variadic.ll | 8 ++++---- .../Attributor/IPConstantProp/2008-06-09-WeakProp.ll | 8 ++++---- .../IPConstantProp/2009-09-24-byval-ptr.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/PR16052.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/PR26044.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/PR43857.ll | 8 ++++---- .../Attributor/IPConstantProp/arg-count-mismatch.ll | 8 ++++---- .../Attributor/IPConstantProp/arg-type-mismatch.ll | 8 ++++---- .../Attributor/IPConstantProp/comdat-ipo.ll | 8 ++++---- .../IPConstantProp/dangling-block-address.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/deadarg.ll | 8 ++++---- .../IPConstantProp/fp-bc-icmp-const-fold.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/global.ll | 8 ++++---- .../Attributor/IPConstantProp/multiple_callbacks.ll | 8 ++++---- .../Attributor/IPConstantProp/musttail-call.ll | 8 ++++---- .../Attributor/IPConstantProp/naked-return.ll | 8 ++++---- .../Attributor/IPConstantProp/openmp_parallel_for.ll | 8 ++++---- .../Transforms/Attributor/IPConstantProp/pthreads.ll | 8 ++++---- .../Attributor/IPConstantProp/recursion.ll | 8 ++++---- .../Attributor/IPConstantProp/remove-call-inst.ll | 8 ++++---- .../Attributor/IPConstantProp/return-argument.ll | 8 ++++---- .../Attributor/IPConstantProp/return-constant.ll | 8 ++++---- .../Attributor/IPConstantProp/return-constants.ll | 8 ++++---- ...solve-after-each-resolving-undefs-for-function.ll | 8 ++++---- .../Attributor/IPConstantProp/thread_local_acs.ll | 8 ++++---- llvm/test/Transforms/Attributor/align.ll | 8 ++++---- llvm/test/Transforms/Attributor/alwaysinline.ll | 8 ++++---- llvm/test/Transforms/Attributor/callbacks.ll | 8 ++++---- llvm/test/Transforms/Attributor/dereferenceable-1.ll | 8 ++++---- llvm/test/Transforms/Attributor/dereferenceable-2.ll | 8 ++++---- llvm/test/Transforms/Attributor/heap_to_stack.ll | 8 ++++---- llvm/test/Transforms/Attributor/internal-noalias.ll | 8 ++++---- llvm/test/Transforms/Attributor/liveness.ll | 8 ++++---- llvm/test/Transforms/Attributor/liveness_chains.ll | 8 ++++---- .../Transforms/Attributor/lvi-after-jumpthreading.ll | 8 ++++---- llvm/test/Transforms/Attributor/lvi-for-ashr.ll | 8 ++++---- llvm/test/Transforms/Attributor/memory_locations.ll | 8 ++++---- llvm/test/Transforms/Attributor/misc.ll | 8 ++++---- llvm/test/Transforms/Attributor/new_attributes.ll | 12 ++++++------ llvm/test/Transforms/Attributor/noalias.ll | 8 ++++---- llvm/test/Transforms/Attributor/nocapture-1.ll | 8 ++++---- llvm/test/Transforms/Attributor/nocapture-2.ll | 8 ++++---- llvm/test/Transforms/Attributor/nofree.ll | 8 ++++---- llvm/test/Transforms/Attributor/nonnull.ll | 8 ++++---- llvm/test/Transforms/Attributor/norecurse.ll | 8 ++++---- llvm/test/Transforms/Attributor/noreturn.ll | 8 ++++---- llvm/test/Transforms/Attributor/noreturn_async.ll | 2 +- llvm/test/Transforms/Attributor/noreturn_sync.ll | 2 +- llvm/test/Transforms/Attributor/nosync.ll | 8 ++++---- llvm/test/Transforms/Attributor/nounwind.ll | 8 ++++---- llvm/test/Transforms/Attributor/range.ll | 8 ++++---- .../Attributor/read_write_returned_arguments_scc.ll | 8 ++++---- llvm/test/Transforms/Attributor/readattrs.ll | 8 ++++---- .../Attributor/reduced/register_benchmark_test.ll | 8 ++++---- llvm/test/Transforms/Attributor/returned.ll | 8 ++++---- .../test/Transforms/Attributor/undefined_behavior.ll | 8 ++++---- llvm/test/Transforms/Attributor/value-simplify.ll | 8 ++++---- llvm/test/Transforms/Attributor/willreturn.ll | 8 ++++---- llvm/test/Transforms/Attributor/wrapper.ll | 2 +- .../Transforms/IPConstantProp/multiple_callbacks.ll | 4 ++-- llvm/test/Transforms/OpenMP/parallel_deletion.ll | 4 ++-- llvm/test/Transforms/OpenMP/rtf_type_checking.ll | 2 +- 94 files changed, 362 insertions(+), 362 deletions(-) diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll index f17d077fce73..77e75084059a 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal i32 @deref(i32* %x) nounwind { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@deref diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-07-02-array-indexing.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-07-02-array-indexing.ll index 92eaeb0f3edc..5fc1b94fcd98 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-07-02-array-indexing.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-07-02-array-indexing.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR2498 ; This test tries to convince CHECK about promoting the load from %A + 2, diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-07-CGUpdate.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-07-CGUpdate.ll index 2854f7111867..fb80ad91c716 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-07-CGUpdate.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-07-CGUpdate.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal fastcc i32 @hash(i32* %ts, i32 %mod) nounwind { ; IS__CGSCC____-LABEL: define {{[^@]+}}@hash() diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-08-CGUpdateSelfEdge.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-08-CGUpdateSelfEdge.ll index c179dd52bbe5..b76c5dd67184 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-08-CGUpdateSelfEdge.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-09-08-CGUpdateSelfEdge.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal fastcc i32 @term_SharingList(i32* %Term, i32* %List) nounwind { ; IS__CGSCC____-LABEL: define {{[^@]+}}@term_SharingList() diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll index dc99e85c12fd..0a3ac67b31ff 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Test that we only promote arguments when the caller/callee have compatible ; function attrubtes. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll index ead9a0e10f71..f6c993f5ee98 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Test that we only promote arguments when the caller/callee have compatible ; function attrubtes. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll index ec32b24e1b9a..b715e428d563 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll @@ -4,10 +4,10 @@ ; we don't do that anymore. It also verifies that the combination of ; globalopt and argpromotion is able to optimize the call safely. ; -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i386-pc-windows-msvc19.11.0" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/aggregate-promote.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/aggregate-promote.ll index be64712b02bb..8196d18c0e68 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/aggregate-promote.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/aggregate-promote.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM %T = type { i32, i32, i32, i32 } @G = constant %T { i32 0, i32 0, i32 17, i32 25 } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll index 21f7ead3b0a4..cc1df4abcaa1 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define void @f() { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f() diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll index e28e4e592f12..deab6567c7f4 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM %struct.ss = type { i32, i64 } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll index 6d2131610fb1..83216f5815dc 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" define internal i32 @test(i32* %X, i32* %Y) { diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll index f867c3c36ebd..cf10658bb7ef 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM %struct.ss = type { i32, i64 } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll index c8d1afef5709..5ac448e22f70 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/chained.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/chained.ll index 5684807e4745..823edbbd7783 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/chained.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/chained.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @G1 = constant i32 0 @G2 = constant i32* @G1 diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow.ll index 142df98051eb..e8fd28fa817d 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Don't promote around control flow. define internal i32 @callee(i1 %C, i32* %P) { diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll index 773df89affb5..2e6d68463771 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll index 9d7fd443fe29..66e3ad1cc6d3 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM %S = type { %S* } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll index 8a02146d893b..a15e5a68eccd 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM declare void @sink(i32) diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll index 1323ac179519..fe558ea02e73 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; TODO: The old pass manager cgscc run is disabled as it causes a crash on windows which is under investigation: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/23151 -; opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll index fc2f6ef1724e..beefa33a436a 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll index 1f034c8404fe..e4b375d3891d 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal void @dead() { diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll index d3892d2093a0..65f199dd69fa 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal void @dead() { diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll index 0fc379c705f1..a5e0140977fe 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR36543 ; Don't promote arguments of musttail callee diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/naked_functions.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/naked_functions.ll index 92cb7efb7bd2..b952ac6dc9a2 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/naked_functions.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/naked_functions.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Don't promote paramaters of/arguments to naked functions diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/nonzero-address-spaces.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/nonzero-address-spaces.ll index 04e8bd6bdc8b..1e9e45ed37e8 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/nonzero-address-spaces.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/nonzero-address-spaces.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ArgumentPromotion should preserve the default function address space ; from the data layout. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr27568.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr27568.ll index d7aafae2d158..a60d18f5e6cb 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr27568.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr27568.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target triple = "x86_64-pc-windows-msvc" define internal void @callee(i8*) { diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr32917.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr32917.ll index 50bfcce5a3af..c03473bcf116 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr32917.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr32917.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR 32917 @b = common local_unnamed_addr global i32 0, align 4 diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll index fff94d452e00..e33891d27c31 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Fix for PR33641. ArgumentPromotion removed the argument to bar but left the call to ; dbg.value which still used the removed argument. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll index 1f50e1f9e5b1..e3842c1aa213 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" ; Checks if !prof metadata is corret in deadargelim. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/reserve-tbaa.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/reserve-tbaa.ll index dbceea83a4fe..ac61432c1843 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/reserve-tbaa.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/reserve-tbaa.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR17906 ; When we promote two arguments in a single function with different types, diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll index d1d2c556b971..1affb64add13 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll index 7502ae651c4f..c1388072f5a5 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR14710 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll index 694c2ef250ef..4cc49336fa6a 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Unused arguments from variadic functions cannot be eliminated as that changes ; their classiciation according to the SysV amd64 ABI. Clang and other frontends diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/2008-06-09-WeakProp.ll b/llvm/test/Transforms/Attributor/IPConstantProp/2008-06-09-WeakProp.ll index 8669f0794826..8ff87ae3bf33 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/2008-06-09-WeakProp.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/2008-06-09-WeakProp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Should not propagate the result of a weak function. ; PR2411 diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll index 1b7b90d4471d..869b67df3e66 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Don't constant-propagate byval pointers, since they are not pointers! ; PR5038 diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll b/llvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll index 786873f8dedf..0c1884ff0a89 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll b/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll index d4eef4c20642..dd1086210e8f 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/PR43857.ll b/llvm/test/Transforms/Attributor/IPConstantProp/PR43857.ll index bb8283125ebe..c894dc9bd767 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/PR43857.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/PR43857.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM %struct.wobble = type { i32 } %struct.zot = type { %struct.wobble, %struct.wobble, %struct.wobble } diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll b/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll index 2a6bd94e1daf..4f177224d314 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/arg-count-mismatch.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; The original C source looked like this: ; diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/arg-type-mismatch.ll b/llvm/test/Transforms/Attributor/IPConstantProp/arg-type-mismatch.ll index 576a6fb9f084..2d38afb5dfc9 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/arg-type-mismatch.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/arg-type-mismatch.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; This test is just to verify that we do not crash/assert due to mismatch in ; argument type between the caller and callee. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll b/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll index 41428b3ff5e4..9ba9f69f4e00 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; See PR26774 diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/dangling-block-address.ll b/llvm/test/Transforms/Attributor/IPConstantProp/dangling-block-address.ll index 489ddb66da71..a285ffc03f27 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/dangling-block-address.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/dangling-block-address.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR5569 ; IPSCCP should prove that the blocks are dead and delete them, and diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/deadarg.ll b/llvm/test/Transforms/Attributor/IPConstantProp/deadarg.ll index b5742a49e64d..c46e9d103d28 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/deadarg.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/deadarg.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal void @foo(i32 %X) { ; CHECK-LABEL: define {{[^@]+}}@foo ; CHECK-SAME: (i32 [[X:%.*]]) diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll b/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll index 727785260f76..4cd030b408f5 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/fp-bc-icmp-const-fold.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-bgq-linux" diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/global.ll b/llvm/test/Transforms/Attributor/IPConstantProp/global.ll index 4326239f1932..a4ba98c3cdf0 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/global.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/global.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @_ZL6test1g = internal global i32 42, align 4 diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/multiple_callbacks.ll b/llvm/test/Transforms/Attributor/IPConstantProp/multiple_callbacks.ll index bbef0302b6ce..f80e72f852c1 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/multiple_callbacks.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/multiple_callbacks.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; ; /---------------------------------------| diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/musttail-call.ll b/llvm/test/Transforms/Attributor/IPConstantProp/musttail-call.ll index fa2a136fcc73..b421498fef25 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/musttail-call.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/musttail-call.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR36485 ; musttail call result can't be replaced with a constant, unless the call can be removed diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/naked-return.ll b/llvm/test/Transforms/Attributor/IPConstantProp/naked-return.ll index badb82bd566f..9e30c16db9b5 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/naked-return.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/naked-return.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-pc-windows-msvc19.0.24215" diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll b/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll index 258bb0745b4c..778ef542fe3d 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; void bar(int, float, double); ; diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/pthreads.ll b/llvm/test/Transforms/Attributor/IPConstantProp/pthreads.ll index 4399f3a37a8b..78272c19cc99 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/pthreads.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/pthreads.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; #include ; diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/recursion.ll b/llvm/test/Transforms/Attributor/IPConstantProp/recursion.ll index 1351d3117853..717552aee1c3 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/recursion.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/recursion.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; CHECK-NOT: %X diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll b/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll index 5b11512f9b6d..a0d71566c3ba 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; PR5596 ; IPSCCP should propagate the 0 argument, eliminate the switch, and propagate diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll index 80c0ba7b5fb7..c4debc479a07 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ;; This function returns its second argument on all return statements define internal i32* @incdec(i1 %C, i32* %V) { diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll index d7c5e9278a81..c82766937471 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; FIXME: icmp folding is missing diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll index 51d94f7be855..0eff5269ea30 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constants.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ;; FIXME: support for extractvalue and insertvalue missing. diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll index 6ed063662dfa..f958e068da17 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define internal i32 @testf(i1 %c) { ; IS__CGSCC____-LABEL: define {{[^@]+}}@testf diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/thread_local_acs.ll b/llvm/test/Transforms/Attributor/IPConstantProp/thread_local_acs.ll index 10e2ac8006d5..036a2e81e2a6 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/thread_local_acs.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/thread_local_acs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; #include ; thread_local int gtl = 0; diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll index 88d070fb8768..08cd6df3cd14 100644 --- a/llvm/test/Transforms/Attributor/align.ll +++ b/llvm/test/Transforms/Attributor/align.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/alwaysinline.ll b/llvm/test/Transforms/Attributor/alwaysinline.ll index 91a7e8fd21b5..49fc2983fde6 100644 --- a/llvm/test/Transforms/Attributor/alwaysinline.ll +++ b/llvm/test/Transforms/Attributor/alwaysinline.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; When a function is marked `alwaysinline` and is able to be inlined, ; we can IPO its boundaries diff --git a/llvm/test/Transforms/Attributor/callbacks.ll b/llvm/test/Transforms/Attributor/callbacks.ll index d6efa5326c68..7d375a3ce8f8 100644 --- a/llvm/test/Transforms/Attributor/callbacks.ll +++ b/llvm/test/Transforms/Attributor/callbacks.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/dereferenceable-1.ll b/llvm/test/Transforms/Attributor/dereferenceable-1.ll index 9036667630eb..43acdaa4d793 100644 --- a/llvm/test/Transforms/Attributor/dereferenceable-1.ll +++ b/llvm/test/Transforms/Attributor/dereferenceable-1.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; FIXME: Figure out why we need 16 iterations here. declare void @deref_phi_user(i32* %a); diff --git a/llvm/test/Transforms/Attributor/dereferenceable-2.ll b/llvm/test/Transforms/Attributor/dereferenceable-2.ll index 3e94364a816b..5b3c444a5cc2 100644 --- a/llvm/test/Transforms/Attributor/dereferenceable-2.ll +++ b/llvm/test/Transforms/Attributor/dereferenceable-2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Determine dereference-ability before unused loads get deleted: ; https://bugs.llvm.org/show_bug.cgi?id=21780 diff --git a/llvm/test/Transforms/Attributor/heap_to_stack.ll b/llvm/test/Transforms/Attributor/heap_to_stack.ll index 3049d5154100..addb7de8d70a 100644 --- a/llvm/test/Transforms/Attributor/heap_to_stack.ll +++ b/llvm/test/Transforms/Attributor/heap_to_stack.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM declare noalias i8* @malloc(i64) diff --git a/llvm/test/Transforms/Attributor/internal-noalias.ll b/llvm/test/Transforms/Attributor/internal-noalias.ll index 2df1c11d9bb9..50a3de608270 100644 --- a/llvm/test/Transforms/Attributor/internal-noalias.ll +++ b/llvm/test/Transforms/Attributor/internal-noalias.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define dso_local i32 @visible(i32* noalias %A, i32* noalias %B) #0 { ; IS__TUNIT____-LABEL: define {{[^@]+}}@visible diff --git a/llvm/test/Transforms/Attributor/liveness.ll b/llvm/test/Transforms/Attributor/liveness.ll index 10c2387973c7..8295e9b4dee3 100644 --- a/llvm/test/Transforms/Attributor/liveness.ll +++ b/llvm/test/Transforms/Attributor/liveness.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; TODO: The old pass manager cgscc run is disabled as it causes a crash on windows which is under investigation: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/23151 -; opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; NOT_CGSCC_OPM: @dead_with_blockaddress_users.l = constant [2 x i8*] [i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 1 to i8*)] ; IS__CGSCC_OPM: @dead_with_blockaddress_users.l = constant [2 x i8*] [i8* blockaddress(@dead_with_blockaddress_users, %lab0), i8* blockaddress(@dead_with_blockaddress_users, %end)] diff --git a/llvm/test/Transforms/Attributor/liveness_chains.ll b/llvm/test/Transforms/Attributor/liveness_chains.ll index 3ba97f2a6c78..53c05bf2d7a7 100644 --- a/llvm/test/Transforms/Attributor/liveness_chains.ll +++ b/llvm/test/Transforms/Attributor/liveness_chains.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; Make sure we need a single iteration to determine the chains are dead/alive. diff --git a/llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll b/llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll index 1511cd3124eb..846a3615d0b4 100644 --- a/llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll +++ b/llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM define i8 @test1(i32 %a, i32 %length) { ; IS________OPM-LABEL: define {{[^@]+}}@test1 diff --git a/llvm/test/Transforms/Attributor/lvi-for-ashr.ll b/llvm/test/Transforms/Attributor/lvi-for-ashr.ll index 729ff66f0735..a9d46b97b228 100644 --- a/llvm/test/Transforms/Attributor/lvi-for-ashr.ll +++ b/llvm/test/Transforms/Attributor/lvi-for-ashr.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; FIXME: DOT should be replaced with 3 diff --git a/llvm/test/Transforms/Attributor/memory_locations.ll b/llvm/test/Transforms/Attributor/memory_locations.ll index 237617d6a9cc..2b07926d8aef 100644 --- a/llvm/test/Transforms/Attributor/memory_locations.ll +++ b/llvm/test/Transforms/Attributor/memory_locations.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" ; CHECK: Function Attrs: inaccessiblememonly diff --git a/llvm/test/Transforms/Attributor/misc.ll b/llvm/test/Transforms/Attributor/misc.ll index 07149471565b..be5cae86807f 100644 --- a/llvm/test/Transforms/Attributor/misc.ll +++ b/llvm/test/Transforms/Attributor/misc.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; Mostly check we do not crash on these uses diff --git a/llvm/test/Transforms/Attributor/new_attributes.ll b/llvm/test/Transforms/Attributor/new_attributes.ll index 6e87cffeb022..6f20a1255ab6 100644 --- a/llvm/test/Transforms/Attributor/new_attributes.ll +++ b/llvm/test/Transforms/Attributor/new_attributes.ll @@ -1,9 +1,9 @@ -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=0 -S | FileCheck %s -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=1 -S | FileCheck %s -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=2 -S | FileCheck %s -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=3 -S | FileCheck %s -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=4 -S | FileCheck %s -; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-disable=false -attributor-max-iterations=2147483647 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=0 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=1 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=2 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=3 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=4 -S | FileCheck %s +; RUN: opt < %s -attributor -attributor-annotate-decl-cs -attributor-max-iterations=2147483647 -S | FileCheck %s ; CHECK-NOT: Function ; CHECK: declare i32 @foo1() diff --git a/llvm/test/Transforms/Attributor/noalias.ll b/llvm/test/Transforms/Attributor/noalias.ll index 53031cd32d78..94bfebe1cfde 100644 --- a/llvm/test/Transforms/Attributor/noalias.ll +++ b/llvm/test/Transforms/Attributor/noalias.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; TODO: The old pass manager cgscc run is disabled as it causes a crash on windows which is under investigation: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/23151 -; opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; TEST 1 - negative. diff --git a/llvm/test/Transforms/Attributor/nocapture-1.ll b/llvm/test/Transforms/Attributor/nocapture-1.ll index 24018b289579..aa908d5ce09f 100644 --- a/llvm/test/Transforms/Attributor/nocapture-1.ll +++ b/llvm/test/Transforms/Attributor/nocapture-1.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @g = global i32* null ; [#uses=1] diff --git a/llvm/test/Transforms/Attributor/nocapture-2.ll b/llvm/test/Transforms/Attributor/nocapture-2.ll index c43df44d770f..d9ad8adf9df8 100644 --- a/llvm/test/Transforms/Attributor/nocapture-2.ll +++ b/llvm/test/Transforms/Attributor/nocapture-2.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; Test cases specifically designed for the "no-capture" argument attribute. ; We use FIXME's to indicate problems and missing attributes. diff --git a/llvm/test/Transforms/Attributor/nofree.ll b/llvm/test/Transforms/Attributor/nofree.ll index 538fee5fb875..b9a2305ab5f8 100644 --- a/llvm/test/Transforms/Attributor/nofree.ll +++ b/llvm/test/Transforms/Attributor/nofree.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/nonnull.ll b/llvm/test/Transforms/Attributor/nonnull.ll index ce8626ab5943..1da05261ac3a 100644 --- a/llvm/test/Transforms/Attributor/nonnull.ll +++ b/llvm/test/Transforms/Attributor/nonnull.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/norecurse.ll b/llvm/test/Transforms/Attributor/norecurse.ll index 3c60c08c8d8e..e94a0f723729 100644 --- a/llvm/test/Transforms/Attributor/norecurse.ll +++ b/llvm/test/Transforms/Attributor/norecurse.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSSA____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn diff --git a/llvm/test/Transforms/Attributor/noreturn.ll b/llvm/test/Transforms/Attributor/noreturn.ll index 864769dc3454..0520a52a47b9 100644 --- a/llvm/test/Transforms/Attributor/noreturn.ll +++ b/llvm/test/Transforms/Attributor/noreturn.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; Test cases specifically designed for the "no-return" function attribute. ; We use FIXME's to indicate problems and missing attributes. diff --git a/llvm/test/Transforms/Attributor/noreturn_async.ll b/llvm/test/Transforms/Attributor/noreturn_async.ll index 17bf0c767f87..c632a4e6d118 100644 --- a/llvm/test/Transforms/Attributor/noreturn_async.ll +++ b/llvm/test/Transforms/Attributor/noreturn_async.ll @@ -1,4 +1,4 @@ -; RUN: opt -attributor -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s +; RUN: opt -attributor -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s ; ; This file is the same as noreturn_sync.ll but with a personality which ; indicates that the exception handler *can* catch asynchronous exceptions. As diff --git a/llvm/test/Transforms/Attributor/noreturn_sync.ll b/llvm/test/Transforms/Attributor/noreturn_sync.ll index 77754dacaba8..055a324e02ba 100644 --- a/llvm/test/Transforms/Attributor/noreturn_sync.ll +++ b/llvm/test/Transforms/Attributor/noreturn_sync.ll @@ -1,4 +1,4 @@ -; RUN: opt -attributor -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s +; RUN: opt -attributor -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s ; ; This file is the same as noreturn_async.ll but with a personality which ; indicates that the exception handler *cannot* catch asynchronous exceptions. diff --git a/llvm/test/Transforms/Attributor/nosync.ll b/llvm/test/Transforms/Attributor/nosync.ll index 7b7ba562544a..fc01770ee47e 100644 --- a/llvm/test/Transforms/Attributor/nosync.ll +++ b/llvm/test/Transforms/Attributor/nosync.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; Test cases designed for the nosync function attribute. diff --git a/llvm/test/Transforms/Attributor/nounwind.ll b/llvm/test/Transforms/Attributor/nounwind.ll index a2f86d318e6c..7f5287a74d74 100644 --- a/llvm/test/Transforms/Attributor/nounwind.ll +++ b/llvm/test/Transforms/Attributor/nounwind.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=3 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; TEST 1 ; IS__TUNIT____: Function Attrs: nofree nosync nounwind diff --git a/llvm/test/Transforms/Attributor/range.ll b/llvm/test/Transforms/Attributor/range.ll index e345b969d554..bb3706cbdf73 100644 --- a/llvm/test/Transforms/Attributor/range.ll +++ b/llvm/test/Transforms/Attributor/range.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=14 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=14 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; FIXME: CGSCC is not looking at callees and calleers even though it could be allowed. diff --git a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll index 673f17f66437..5daa45178c13 100644 --- a/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll +++ b/llvm/test/Transforms/Attributor/read_write_returned_arguments_scc.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; This is an evolved example to stress test SCC parameter attribute propagation. diff --git a/llvm/test/Transforms/Attributor/readattrs.ll b/llvm/test/Transforms/Attributor/readattrs.ll index cadb79e3bc21..fdea21da26d0 100644 --- a/llvm/test/Transforms/Attributor/readattrs.ll +++ b/llvm/test/Transforms/Attributor/readattrs.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @x = global i32 0 diff --git a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll index 4a5f1f4fb9e2..d983bc947cac 100644 --- a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll +++ b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor --attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s -; RUN: opt -attributor-cgscc --attributor-disable=false -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s -; RUN: opt -passes=attributor --attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s -; RUN: opt -passes='attributor-cgscc' --attributor-disable=false -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s +; RUN: opt -attributor -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s +; RUN: opt -attributor-cgscc -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s +; RUN: opt -passes=attributor -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s +; RUN: opt -passes='attributor-cgscc' -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s ; Somewhat reduced test case on which we crashed before. Make sure we do not. diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll index 4e4448ead796..32ab04fbf0b9 100644 --- a/llvm/test/Transforms/Attributor/returned.ll +++ b/llvm/test/Transforms/Attributor/returned.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; ; Test cases specifically designed for the "returned" argument attribute. ; We use FIXME's to indicate problems and missing attributes. diff --git a/llvm/test/Transforms/Attributor/undefined_behavior.ll b/llvm/test/Transforms/Attributor/undefined_behavior.ll index 4aa9cef4a64f..53556fb6d205 100644 --- a/llvm/test/Transforms/Attributor/undefined_behavior.ll +++ b/llvm/test/Transforms/Attributor/undefined_behavior.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=2 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll index 931212f53967..11ddf9d2352b 100644 --- a/llvm/test/Transforms/Attributor/value-simplify.ll +++ b/llvm/test/Transforms/Attributor/value-simplify.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=4 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" declare void @f(i32) diff --git a/llvm/test/Transforms/Attributor/willreturn.ll b/llvm/test/Transforms/Attributor/willreturn.ll index f168aa7864df..0e439c984db7 100644 --- a/llvm/test/Transforms/Attributor/willreturn.ll +++ b/llvm/test/Transforms/Attributor/willreturn.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM -; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "e-m:e-i54:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Attributor/wrapper.ll b/llvm/test/Transforms/Attributor/wrapper.ll index f965dbee2c73..d48ab54aef72 100644 --- a/llvm/test/Transforms/Attributor/wrapper.ll +++ b/llvm/test/Transforms/Attributor/wrapper.ll @@ -1,4 +1,4 @@ -; RUN: opt -passes=attributor-cgscc -attributor-disable=false -attributor-annotate-decl-cs -attributor-allow-shallow-wrappers -S < %s | FileCheck %s --check-prefix=CHECK +; RUN: opt -passes=attributor-cgscc -attributor-annotate-decl-cs -attributor-allow-shallow-wrappers -S < %s | FileCheck %s --check-prefix=CHECK ; TEST 1: simple test, without argument ; A wrapper will be generated for this function, Check the wrapper first diff --git a/llvm/test/Transforms/IPConstantProp/multiple_callbacks.ll b/llvm/test/Transforms/IPConstantProp/multiple_callbacks.ll index 5d4de1155617..6bc3f4477db0 100644 --- a/llvm/test/Transforms/IPConstantProp/multiple_callbacks.ll +++ b/llvm/test/Transforms/IPConstantProp/multiple_callbacks.ll @@ -1,8 +1,8 @@ ; RUN: opt -ipconstprop -S < %s | FileCheck %s ; FIXME: There seems to be another instance of nondeterminism which causes the number of iterations to be either 1 or 3, depending on the system. ; This needs to be investigated and resolved. In the meantime we do not verify the number of iterations. -; opt -S -passes=attributor -aa-pipeline='basic-aa' -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=1 < %s | FileCheck %s -; RUN: opt -S -passes=attributor -aa-pipeline='basic-aa' -attributor-disable=false -attributor-max-iterations-verify=false -attributor-max-iterations=3 < %s | FileCheck %s +; opt -S -passes=attributor -aa-pipeline='basic-aa' -attributor-max-iterations-verify -attributor-max-iterations=1 < %s | FileCheck %s +; RUN: opt -S -passes=attributor -aa-pipeline='basic-aa' -attributor-max-iterations-verify=false -attributor-max-iterations=3 < %s | FileCheck %s ; ; ; /---------------------------------------| diff --git a/llvm/test/Transforms/OpenMP/parallel_deletion.ll b/llvm/test/Transforms/OpenMP/parallel_deletion.ll index ee316b56794a..cb14cee9a325 100644 --- a/llvm/test/Transforms/OpenMP/parallel_deletion.ll +++ b/llvm/test/Transforms/OpenMP/parallel_deletion.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature -; RUN: opt -S -attributor -openmpopt -attributor-disable=false < %s | FileCheck %s -; RUN: opt -S -passes='attributor,cgscc(openmpopt)' -attributor-disable=false < %s | FileCheck %s +; RUN: opt -S -attributor -openmpopt < %s | FileCheck %s +; RUN: opt -S -passes='attributor,cgscc(openmpopt)' < %s | FileCheck %s ; target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/OpenMP/rtf_type_checking.ll b/llvm/test/Transforms/OpenMP/rtf_type_checking.ll index 6c392e75b4c4..e355c13508ca 100644 --- a/llvm/test/Transforms/OpenMP/rtf_type_checking.ll +++ b/llvm/test/Transforms/OpenMP/rtf_type_checking.ll @@ -1,5 +1,5 @@ ; RUN: opt -S -openmpopt -stats < %s 2>&1 | FileCheck %s -; RUN: opt -S -attributor -attributor-disable=false -openmpopt -stats < %s 2>&1 | FileCheck %s +; RUN: opt -S -attributor -openmpopt -stats < %s 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -- GitLab From c5794f77eb4a863f1b540222a82e6476f8892767 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 17 Apr 2020 21:43:54 -0500 Subject: [PATCH 004/910] [Attributor][PM] Introduce `-attributor-enable={none,cgscc,module,all}` The old command line option `-attributor-disable` was too coarse grained as we want to measure the effects of the module or cgscc pass without the other as well. Since `none` is the default there is no real functional change. Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D78571 --- llvm/include/llvm/Transforms/IPO/Attributor.h | 8 +++++++ llvm/lib/Passes/PassBuilder.cpp | 6 ++--- .../lib/Transforms/IPO/PassManagerBuilder.cpp | 23 ++++++++++++------- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h index be90b8d1b7fa..d934c4473ca8 100644 --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -2862,6 +2862,14 @@ struct AAValueConstantRange : public IntegerRangeState, static const char ID; }; +/// Run options, used by the pass manager. +enum AttributorRunOption { + NONE = 0, + MODULE = 1 << 0, + CGSCC = 1 << 1, + ALL = MODULE | CGSCC +}; + } // end namespace llvm #endif // LLVM_TRANSFORMS_IPO_FUNCTIONATTRS_H diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 0620c9553836..5647d9dddca4 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -258,7 +258,7 @@ extern cl::opt EnableOrderFileInstrumentation; extern cl::opt FlattenedProfileUsed; -extern cl::opt DisableAttributor; +extern cl::opt AttributorRun; const PassBuilder::OptimizationLevel PassBuilder::OptimizationLevel::O0 = { /*SpeedLevel*/ 0, @@ -768,7 +768,7 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, true /* SamplePGO */)); } - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::MODULE) MPM.addPass(AttributorPass()); // Interprocedural constant propagation now that basic cleanup has occurred @@ -852,7 +852,7 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, IP.HotCallSiteThreshold = 0; MainCGPipeline.addPass(InlinerPass(IP)); - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::CGSCC) MainCGPipeline.addPass(AttributorCGSCCPass()); if (PTO.Coroutines) diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index b32f80ce393b..50ec49b9f4a7 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -153,10 +153,17 @@ static cl::opt EnableMatrix("enable-matrix", cl::init(false), cl::Hidden, cl::desc("Enable lowering of the matrix intrinsics")); -cl::opt DisableAttributor( - "attributor-disable", cl::Hidden, - cl::desc("Disable the attributor inter-procedural deduction pass."), - cl::init(true)); +cl::opt AttributorRun( + "attributor-enable", cl::Hidden, cl::init(AttributorRunOption::NONE), + cl::desc("Enable the attributor inter-procedural deduction pass."), + cl::values(clEnumValN(AttributorRunOption::ALL, "all", + "enable all attributor runs"), + clEnumValN(AttributorRunOption::MODULE, "module", + "enable module-wide attributor runs"), + clEnumValN(AttributorRunOption::CGSCC, "cgscc", + "enable call graph SCC attributor runs"), + clEnumValN(AttributorRunOption::NONE, "none", + "disable attributor runs"))); PassManagerBuilder::PassManagerBuilder() { OptLevel = 2; @@ -552,7 +559,7 @@ void PassManagerBuilder::populateModulePassManager( MPM.add(createInferFunctionAttrsLegacyPass()); // Infer attributes on declarations, call sites, arguments, etc. - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::MODULE) MPM.add(createAttributorLegacyPass()); addExtensionsToPM(EP_ModuleOptimizerEarly, MPM); @@ -601,7 +608,7 @@ void PassManagerBuilder::populateModulePassManager( } // Infer attributes on declarations, call sites, arguments, etc. for an SCC. - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::CGSCC) MPM.add(createAttributorCGSCCLegacyPass()); // Try to perform OpenMP specific optimizations. This is a (quick!) no-op if @@ -888,7 +895,7 @@ void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) { PM.add(createCalledValuePropagationPass()); // Infer attributes on declarations, call sites, arguments, etc. - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::MODULE) PM.add(createAttributorLegacyPass()); } @@ -943,7 +950,7 @@ void PassManagerBuilder::addLTOOptimizationPasses(legacy::PassManagerBase &PM) { addPGOInstrPasses(PM, /* IsCS */ true); // Infer attributes on declarations, call sites, arguments, etc. for an SCC. - if (!DisableAttributor) + if (AttributorRun & AttributorRunOption::CGSCC) PM.add(createAttributorCGSCCLegacyPass()); // Try to perform OpenMP specific optimizations. This is a (quick!) no-op if -- GitLab From ea439bbcbb41e81e0953b38463c95e95ea3ec4bf Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 16 Apr 2020 20:32:06 -0500 Subject: [PATCH 005/910] [Attributor][NFC] Track the number of created AAs in the statistics --- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 2d63bc830982..1052dda05f47 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -40,6 +40,8 @@ static cl::opt ManifestInternal( static cl::opt MaxHeapToStackSize("max-heap-to-stack-size", cl::init(128), cl::Hidden); +STATISTIC(NumAAs, "Number of abstract attributes created"); + // Some helper macros to deal with statistics tracking. // // Usage: @@ -6995,6 +6997,7 @@ const char AAValueConstantRange::ID = 0; #define SWITCH_PK_CREATE(CLASS, IRP, PK, SUFFIX) \ case IRPosition::PK: \ AA = new (A.Allocator) CLASS##SUFFIX(IRP, A); \ + ++NumAAs; \ break; #define CREATE_FUNCTION_ABSTRACT_ATTRIBUTE_FOR_POSITION(CLASS) \ -- GitLab From 46b7ed0e6fdf70efb70c33beb2ec6790d4c284d4 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 21 Apr 2020 13:57:19 -0500 Subject: [PATCH 006/910] [Attributor] Remove dependence edges eagerly If we have a dependence between an abstract attribute A to an abstract attribute B such hat changes in A should trigger an update of B, we do not need to keep the dependence around once the update was triggered. If the dependence is still required the update will reinsert it into the dependence map, if it is not we avoid triggering B in the future. This replaces the "recompute interval" mechanism we used before to prune stale dependences. Number of required iterations is generally down, compile time for the module pass (not really the CGSCC pass) is down quite a bit. There is one test change which looks like an artifact in the undefined behavior AA that needs to be looked at. --- llvm/include/llvm/Transforms/IPO/Attributor.h | 11 ++---- llvm/lib/Transforms/IPO/Attributor.cpp | 36 ++++--------------- .../Attributor/ArgumentPromotion/basictest.ll | 4 +-- .../live_called_from_dead_2.ll | 4 +-- .../IPConstantProp/2009-09-24-byval-ptr.ll | 4 +-- llvm/test/Transforms/Attributor/align.ll | 4 +-- .../Attributor/dereferenceable-1.ll | 4 +-- llvm/test/Transforms/Attributor/range.ll | 27 +++++++++----- llvm/test/Transforms/Attributor/returned.ll | 4 +-- llvm/test/Transforms/Attributor/willreturn.ll | 2 +- 10 files changed, 40 insertions(+), 60 deletions(-) diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h index d934c4473ca8..3002a111a716 100644 --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -729,15 +729,12 @@ struct Attributor { /// \param InfoCache Cache to hold various information accessible for /// the abstract attributes. /// \param CGUpdater Helper to update an underlying call graph. - /// \param DepRecomputeInterval Number of iterations until the dependences - /// between abstract attributes are recomputed. /// \param Whitelist If not null, a set limiting the attribute opportunities. Attributor(SetVector &Functions, InformationCache &InfoCache, - CallGraphUpdater &CGUpdater, unsigned DepRecomputeInterval, + CallGraphUpdater &CGUpdater, DenseSet *Whitelist = nullptr) : Allocator(InfoCache.Allocator), Functions(Functions), - InfoCache(InfoCache), CGUpdater(CGUpdater), - DepRecomputeInterval(DepRecomputeInterval), Whitelist(Whitelist) {} + InfoCache(InfoCache), CGUpdater(CGUpdater), Whitelist(Whitelist) {} ~Attributor(); @@ -1268,10 +1265,6 @@ private: /// Set if the attribute currently updated did query a non-fix attribute. bool QueriedNonFixAA; - /// Number of iterations until the dependences between abstract attributes are - /// recomputed. - const unsigned DepRecomputeInterval; - /// If not null, a set limiting the attribute opportunities. const DenseSet *Whitelist; diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 0cda3890804c..e715d04c0d1e 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -68,11 +68,6 @@ static cl::opt AnnotateDeclarationCallSites( "attributor-annotate-decl-cs", cl::Hidden, cl::desc("Annotate call sites of function declarations."), cl::init(false)); -static cl::opt DepRecInterval( - "attributor-dependence-recompute-interval", cl::Hidden, - cl::desc("Number of iterations until dependences are recomputed."), - cl::init(4)); - static cl::opt EnableHeapToStack("enable-heap-to-stack-conversion", cl::init(true), cl::Hidden); @@ -915,8 +910,6 @@ ChangeStatus Attributor::run() { SetVector Worklist, InvalidAAs; Worklist.insert(AllAbstractAttributes.begin(), AllAbstractAttributes.end()); - bool RecomputeDependences = false; - do { // Remember the size to determine new attributes. size_t NumAAs = AllAbstractAttributes.size(); @@ -948,24 +941,9 @@ ChangeStatus Attributor::run() { else ChangedAAs.push_back(DepOnInvalidAA); } - if (!RecomputeDependences) - Worklist.insert(QuerriedAAs->OptionalAAs.begin(), - QuerriedAAs->OptionalAAs.end()); - } - - // If dependences (=QueryMap) are recomputed we have to look at all abstract - // attributes again, regardless of what changed in the last iteration. - if (RecomputeDependences) { - LLVM_DEBUG( - dbgs() << "[Attributor] Run all AAs to recompute dependences\n"); - // The query map entries are reused (1) because it is likely a future - // iteration has similar dependences and (2) the QueryMapValueTy is - // allocated via a BumpPtrAllocator and cannot be reused otherwise. - for (auto &It : QueryMap) - It.getSecond()->clear(); - ChangedAAs.clear(); - Worklist.insert(AllAbstractAttributes.begin(), - AllAbstractAttributes.end()); + Worklist.insert(QuerriedAAs->OptionalAAs.begin(), + QuerriedAAs->OptionalAAs.end()); + QuerriedAAs->clear(); } // Add all abstract attributes that are potentially dependent on one that @@ -976,6 +954,7 @@ ChangeStatus Attributor::run() { QuerriedAAs->OptionalAAs.end()); Worklist.insert(QuerriedAAs->RequiredAAs.begin(), QuerriedAAs->RequiredAAs.end()); + QuerriedAAs->clear(); } } @@ -1004,9 +983,6 @@ ChangeStatus Attributor::run() { } } - // Check if we recompute the dependences in the next iteration. - RecomputeDependences = (DepRecomputeInterval > 0 && - IterationCounter % DepRecomputeInterval == 0); // Add attributes to the changed set if they have been created in the last // iteration. @@ -1050,6 +1026,8 @@ ChangeStatus Attributor::run() { QuerriedAAs->OptionalAAs.end()); ChangedAAs.append(QuerriedAAs->RequiredAAs.begin(), QuerriedAAs->RequiredAAs.end()); + // Release the memory early. + QuerriedAAs->clear(); } } @@ -2002,7 +1980,7 @@ static bool runAttributorOnFunctions(InformationCache &InfoCache, // Create an Attributor and initially empty information cache that is filled // while we identify default attribute opportunities. - Attributor A(Functions, InfoCache, CGUpdater, DepRecInterval); + Attributor A(Functions, InfoCache, CGUpdater); // Create shallow wrappers for all functions that are not IPO amendable if (AllowShallowWrappers) diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll index 83216f5815dc..25febca6cd29 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll index 65f199dd69fa..bb7af74ed57e 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll index 869b67df3e66..cfac2978e05c 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll index 08cd6df3cd14..e6245c6033f7 100644 --- a/llvm/test/Transforms/Attributor/align.ll +++ b/llvm/test/Transforms/Attributor/align.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM diff --git a/llvm/test/Transforms/Attributor/dereferenceable-1.ll b/llvm/test/Transforms/Attributor/dereferenceable-1.ll index 43acdaa4d793..a03f512d5360 100644 --- a/llvm/test/Transforms/Attributor/dereferenceable-1.ll +++ b/llvm/test/Transforms/Attributor/dereferenceable-1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=16 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=12 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=12 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; FIXME: Figure out why we need 16 iterations here. diff --git a/llvm/test/Transforms/Attributor/range.ll b/llvm/test/Transforms/Attributor/range.ll index bb3706cbdf73..9c6ae894766a 100644 --- a/llvm/test/Transforms/Attributor/range.ll +++ b/llvm/test/Transforms/Attributor/range.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=14 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=15 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM @@ -437,13 +437,22 @@ define void @f1(i32){ ; IS________OPM: 5: ; IS________OPM-NEXT: ret void ; -; IS________NPM-LABEL: define {{[^@]+}}@f1 -; IS________NPM-SAME: (i32 [[TMP0:%.*]]) -; IS________NPM-NEXT: br label [[TMP3:%.*]] -; IS________NPM: 2: -; IS________NPM-NEXT: unreachable -; IS________NPM: 3: -; IS________NPM-NEXT: ret void +; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@f1 +; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]]) +; IS__TUNIT_NPM-NEXT: br label [[TMP3:%.*]] +; IS__TUNIT_NPM: 2: +; IS__TUNIT_NPM-NEXT: tail call void @unkown() +; IS__TUNIT_NPM-NEXT: br label [[TMP3]] +; IS__TUNIT_NPM: 3: +; IS__TUNIT_NPM-NEXT: ret void +; +; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f1 +; IS__CGSCC_NPM-SAME: (i32 [[TMP0:%.*]]) +; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] +; IS__CGSCC_NPM: 2: +; IS__CGSCC_NPM-NEXT: unreachable +; IS__CGSCC_NPM: 3: +; IS__CGSCC_NPM-NEXT: ret void ; %2 = tail call i32 @r1(i32 %0) %3 = icmp sgt i32 %2, 15 diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll index 32ab04fbf0b9..54aa7daf1865 100644 --- a/llvm/test/Transforms/Attributor/returned.ll +++ b/llvm/test/Transforms/Attributor/returned.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM ; diff --git a/llvm/test/Transforms/Attributor/willreturn.ll b/llvm/test/Transforms/Attributor/willreturn.ll index 0e439c984db7..63767a0e7670 100644 --- a/llvm/test/Transforms/Attributor/willreturn.ll +++ b/llvm/test/Transforms/Attributor/willreturn.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes ; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=5 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM -; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=7 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM ; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM ; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM -- GitLab From 8bec33c096bd71bbace60c4371cde88fd48ae651 Mon Sep 17 00:00:00 2001 From: Christopher Tetreault Date: Tue, 21 Apr 2020 13:02:23 -0700 Subject: [PATCH 007/910] [SVE] Remove VectorType::getBitWidth() Summary: * VectorType::getBitWidth() is just an unsafe version of getPrimitiveSizeInBits() that assumes all vectors are fixed width. Reviewers: efriedma, sdesmalen, huntergr, craig.topper Reviewed By: efriedma Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77833 --- llvm/include/llvm/IR/DerivedTypes.h | 6 ---- llvm/lib/IR/Type.cpp | 33 ++++++++++++---------- llvm/unittests/AsmParser/AsmParserTest.cpp | 4 +-- 3 files changed, 20 insertions(+), 23 deletions(-) diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h index 186430754303..306d388cb8a7 100644 --- a/llvm/include/llvm/IR/DerivedTypes.h +++ b/llvm/include/llvm/IR/DerivedTypes.h @@ -519,12 +519,6 @@ public: return Scalable; } - /// Return the minimum number of bits in the Vector type. - /// Returns zero when the vector is a vector of pointers. - unsigned getBitWidth() const { - return getNumElements() * getElementType()->getPrimitiveSizeInBits(); - } - /// Methods for support type inquiry through isa, cast, and dyn_cast. static bool classof(const Type *T) { return T->getTypeID() == VectorTyID; diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp index 17ca43cbbccb..e8c693aedf64 100644 --- a/llvm/lib/IR/Type.cpp +++ b/llvm/lib/IR/Type.cpp @@ -68,20 +68,20 @@ bool Type::canLosslesslyBitCastTo(Type *Ty) const { return false; // Vector -> Vector conversions are always lossless if the two vector types - // have the same size, otherwise not. Also, 64-bit vector types can be - // converted to x86mmx. - if (auto *thisPTy = dyn_cast(this)) { - if (auto *thatPTy = dyn_cast(Ty)) - return thisPTy->getBitWidth() == thatPTy->getBitWidth(); - if (Ty->getTypeID() == Type::X86_MMXTyID && - thisPTy->getBitWidth() == 64) - return true; - } - - if (this->getTypeID() == Type::X86_MMXTyID) - if (auto *thatPTy = dyn_cast(Ty)) - if (thatPTy->getBitWidth() == 64) - return true; + // have the same size, otherwise not. + if (isa(this) && isa(Ty)) + return getPrimitiveSizeInBits() == Ty->getPrimitiveSizeInBits(); + + // 64-bit fixed width vector types can be losslessly converted to x86mmx. + if (((isa(this) && + !cast(this)->getElementCount().Scalable) && + Ty->isX86_MMXTy()) && + getPrimitiveSizeInBits().getFixedSize() == 64) + return true; + if ((isX86_MMXTy() && (isa(Ty) && + !cast(Ty)->getElementCount().Scalable)) && + Ty->getPrimitiveSizeInBits().getFixedSize() == 64) + return true; // At this point we have only various mismatches of the first class types // remaining and ptr->ptr. Just select the lossless conversions. Everything @@ -125,7 +125,10 @@ TypeSize Type::getPrimitiveSizeInBits() const { return TypeSize::Fixed(cast(this)->getBitWidth()); case Type::VectorTyID: { const VectorType *VTy = cast(this); - return TypeSize(VTy->getBitWidth(), VTy->isScalable()); + ElementCount EC = VTy->getElementCount(); + TypeSize ETS = VTy->getElementType()->getPrimitiveSizeInBits(); + assert(!ETS.isScalable() && "Vector type should have fixed-width elements"); + return {ETS.getFixedSize() * EC.Min, EC.Scalable}; } default: return TypeSize::Fixed(0); } diff --git a/llvm/unittests/AsmParser/AsmParserTest.cpp b/llvm/unittests/AsmParser/AsmParserTest.cpp index d5f734d390af..198191bf435f 100644 --- a/llvm/unittests/AsmParser/AsmParserTest.cpp +++ b/llvm/unittests/AsmParser/AsmParserTest.cpp @@ -232,7 +232,7 @@ TEST(AsmParserTest, TypeWithSlotMappingParsing) { // Check the details of the vector. VectorType *VT = cast(Ty); ASSERT_TRUE(VT->getNumElements() == 5); - ASSERT_TRUE(VT->getBitWidth() == 160); + ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedSize() == 160); Ty = VT->getElementType(); ASSERT_TRUE(Ty->isIntegerTy()); ASSERT_TRUE(Ty->getPrimitiveSizeInBits() == 32); @@ -364,7 +364,7 @@ TEST(AsmParserTest, TypeAtBeginningWithSlotMappingParsing) { // Check the details of the vector. VectorType *VT = cast(Ty); ASSERT_TRUE(VT->getNumElements() == 5); - ASSERT_TRUE(VT->getBitWidth() == 160); + ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedSize() == 160); Ty = VT->getElementType(); ASSERT_TRUE(Ty->isIntegerTy()); ASSERT_TRUE(Ty->getPrimitiveSizeInBits() == 32); -- GitLab From 060efd24c7f06a6c66afc15fc5c499eb0d591523 Mon Sep 17 00:00:00 2001 From: Jez Ng Date: Tue, 21 Apr 2020 13:37:57 -0700 Subject: [PATCH 008/910] [lld-macho] Add basic support for linking against dylibs This diff implements: * dylib loading (much of which is being restored from @pcc and @ruiu's original work) * The GOT_LOAD relocation, which allows us to load non-lazy dylib symbols * Basic bind opcode emission, which tells `dyld` how to populate the GOT Differential Revision: https://reviews.llvm.org/D76252 --- lld/MachO/Arch/X86_64.cpp | 6 +- lld/MachO/CMakeLists.txt | 1 + lld/MachO/Config.h | 4 + lld/MachO/Driver.cpp | 48 ++++++- lld/MachO/InputFiles.cpp | 45 +++++- lld/MachO/InputFiles.h | 13 +- lld/MachO/InputSection.cpp | 14 +- lld/MachO/InputSection.h | 6 +- lld/MachO/Options.td | 9 ++ lld/MachO/OutputSegment.h | 5 + lld/MachO/SymbolTable.cpp | 10 ++ lld/MachO/SymbolTable.h | 6 +- lld/MachO/Symbols.h | 24 +++- lld/MachO/SyntheticSections.cpp | 36 +++++ lld/MachO/SyntheticSections.h | 52 +++++++ lld/MachO/Target.h | 3 + lld/MachO/Writer.cpp | 103 +++++++++++-- lld/MachO/Writer.h | 2 + lld/test/MachO/Inputs/goodbye-dylib.yaml | 175 +++++++++++++++++++++++ lld/test/MachO/Inputs/hello-dylib.yaml | 169 ++++++++++++++++++++++ lld/test/MachO/Inputs/no-id-dylib.yaml | 160 +++++++++++++++++++++ lld/test/MachO/dylink.s | 35 +++++ lld/test/MachO/missing-dylib.s | 5 + lld/test/MachO/no-id-dylink.s | 13 ++ lld/test/MachO/search-paths.test | 12 ++ 25 files changed, 919 insertions(+), 37 deletions(-) create mode 100644 lld/MachO/SyntheticSections.cpp create mode 100644 lld/MachO/SyntheticSections.h create mode 100644 lld/test/MachO/Inputs/goodbye-dylib.yaml create mode 100644 lld/test/MachO/Inputs/hello-dylib.yaml create mode 100644 lld/test/MachO/Inputs/no-id-dylib.yaml create mode 100644 lld/test/MachO/dylink.s create mode 100644 lld/test/MachO/missing-dylib.s create mode 100644 lld/test/MachO/no-id-dylink.s create mode 100644 lld/test/MachO/search-paths.test diff --git a/lld/MachO/Arch/X86_64.cpp b/lld/MachO/Arch/X86_64.cpp index 6c0989edfd39..39dd644d5d1c 100644 --- a/lld/MachO/Arch/X86_64.cpp +++ b/lld/MachO/Arch/X86_64.cpp @@ -32,6 +32,7 @@ X86_64::X86_64() { uint64_t X86_64::getImplicitAddend(const uint8_t *loc, uint8_t type) const { switch (type) { case X86_64_RELOC_SIGNED: + case X86_64_RELOC_GOT_LOAD: return read32le(loc); default: error("TODO: Unhandled relocation type " + std::to_string(type)); @@ -42,8 +43,9 @@ uint64_t X86_64::getImplicitAddend(const uint8_t *loc, uint8_t type) const { void X86_64::relocateOne(uint8_t *loc, uint8_t type, uint64_t val) const { switch (type) { case X86_64_RELOC_SIGNED: - // This type is only used for pc-relative relocations, so offset by 4 since - // the RIP has advanced by 4 at this point. + case X86_64_RELOC_GOT_LOAD: + // These types are only used for pc-relative relocations, so offset by 4 + // since the RIP has advanced by 4 at this point. write32le(loc, val - 4); break; default: diff --git a/lld/MachO/CMakeLists.txt b/lld/MachO/CMakeLists.txt index 47e4207d949b..0ed841fb15e0 100644 --- a/lld/MachO/CMakeLists.txt +++ b/lld/MachO/CMakeLists.txt @@ -10,6 +10,7 @@ add_lld_library(lldMachO2 OutputSegment.cpp SymbolTable.cpp Symbols.cpp + SyntheticSections.cpp Target.cpp Writer.cpp diff --git a/lld/MachO/Config.h b/lld/MachO/Config.h index ea8df75b6803..7542de052169 100644 --- a/lld/MachO/Config.h +++ b/lld/MachO/Config.h @@ -11,6 +11,8 @@ #include "llvm/ADT/StringRef.h" +#include + namespace lld { namespace macho { @@ -19,6 +21,8 @@ class Symbol; struct Configuration { llvm::StringRef outputFile; Symbol *entry; + + std::vector searchPaths; }; extern Configuration *config; diff --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp index 475f81a6471a..2dd58dc02094 100644 --- a/lld/MachO/Driver.cpp +++ b/lld/MachO/Driver.cpp @@ -21,6 +21,7 @@ #include "lld/Common/LLVM.h" #include "lld/Common/Memory.h" #include "lld/Common/Version.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/BinaryFormat/Magic.h" @@ -68,6 +69,17 @@ opt::InputArgList MachOOptTable::parse(ArrayRef argv) { return args; } +// This is for -lfoo. We'll look for libfoo.dylib from search paths. +static Optional findDylib(StringRef name) { + for (StringRef dir : config->searchPaths) { + std::string path = (dir + "/lib" + name + ".dylib").str(); + if (fs::exists(path)) + return path; + } + error("library not found for -l" + name); + return None; +} + static TargetInfo *createTargetInfo(opt::InputArgList &args) { StringRef s = args.getLastArgValue(OPT_arch, "x86_64"); if (s != "x86_64") @@ -75,6 +87,15 @@ static TargetInfo *createTargetInfo(opt::InputArgList &args) { return createX86_64TargetInfo(); } +static std::vector getSearchPaths(opt::InputArgList &args) { + std::vector ret{args::getStrings(args, OPT_L)}; + if (!args.hasArg(OPT_Z)) { + ret.push_back("/usr/lib"); + ret.push_back("/usr/local/lib"); + } + return ret; +} + static void addFile(StringRef path) { Optional buffer = readFile(path); if (!buffer) @@ -85,6 +106,9 @@ static void addFile(StringRef path) { case file_magic::macho_object: inputFiles.push_back(make(mbref)); break; + case file_magic::macho_dynamically_linked_shared_lib: + inputFiles.push_back(make(mbref)); + break; default: error(path + ": unhandled file type"); } @@ -98,27 +122,36 @@ bool macho::link(llvm::ArrayRef argsArr, bool canExitEarly, MachOOptTable parser; opt::InputArgList args = parser.parse(argsArr.slice(1)); - if (args.hasArg(OPT_v)) { - message(getLLDVersion()); - freeArena(); - return !errorCount(); - } - config = make(); symtab = make(); target = createTargetInfo(args); config->entry = symtab->addUndefined(args.getLastArgValue(OPT_e, "_main")); config->outputFile = args.getLastArgValue(OPT_o, "a.out"); + config->searchPaths = getSearchPaths(args); + + if (args.hasArg(OPT_v)) { + message(getLLDVersion()); + std::vector &searchPaths = config->searchPaths; + message("Library search paths:\n" + + llvm::join(searchPaths.begin(), searchPaths.end(), "\n")); + freeArena(); + return !errorCount(); + } getOrCreateOutputSegment("__TEXT", VM_PROT_READ | VM_PROT_EXECUTE); getOrCreateOutputSegment("__DATA", VM_PROT_READ | VM_PROT_WRITE); + getOrCreateOutputSegment("__DATA_CONST", VM_PROT_READ | VM_PROT_WRITE); for (opt::Arg *arg : args) { switch (arg->getOption().getID()) { case OPT_INPUT: addFile(arg->getValue()); break; + case OPT_l: + if (Optional path = findDylib(arg->getValue())) + addFile(*path); + break; } } @@ -127,6 +160,8 @@ bool macho::link(llvm::ArrayRef argsArr, bool canExitEarly, return false; } + createSyntheticSections(); + // Initialize InputSections. for (InputFile *file : inputFiles) for (InputSection *sec : file->sections) @@ -136,6 +171,7 @@ bool macho::link(llvm::ArrayRef argsArr, bool canExitEarly, for (InputSection *isec : inputSections) { OutputSegment *os = getOrCreateOutputSegment(isec->segname, VM_PROT_READ | VM_PROT_WRITE); + isec->parent = os; os->sections[isec->name].push_back(isec); } diff --git a/lld/MachO/InputFiles.cpp b/lld/MachO/InputFiles.cpp index e2cfd1f0cc5d..7794f3e893fd 100644 --- a/lld/MachO/InputFiles.cpp +++ b/lld/MachO/InputFiles.cpp @@ -74,7 +74,15 @@ Optional macho::readFile(StringRef path) { std::unique_ptr &mb = *mbOrErr; MemoryBufferRef mbref = mb->getMemBufferRef(); make>(std::move(mb)); // take mb ownership - return mbref; + + // If this is a regular non-fat file, return it. + const char *buf = mbref.getBufferStart(); + auto *hdr = reinterpret_cast(buf); + if (read32be(&hdr->magic) != MachO::FAT_MAGIC) + return mbref; + + error("TODO: Add support for universal binaries"); + return None; } static const load_command *findCommand(const mach_header_64 *hdr, @@ -155,6 +163,7 @@ ObjFile::ObjFile(MemoryBufferRef mb) : InputFile(ObjKind, mb) { sections = parseSections(objSections); } + // TODO: Error on missing LC_SYMTAB? if (const load_command *cmd = findCommand(hdr, LC_SYMTAB)) { auto *c = reinterpret_cast(cmd); const char *strtab = reinterpret_cast(buf) + c->stroff; @@ -168,7 +177,7 @@ ObjFile::ObjFile(MemoryBufferRef mb) : InputFile(ObjKind, mb) { // Undefined symbol if (!sym.n_sect) { - error("TODO: Support undefined symbols"); + symbols.push_back(symtab->addUndefined(name)); continue; } @@ -198,6 +207,38 @@ ObjFile::ObjFile(MemoryBufferRef mb) : InputFile(ObjKind, mb) { } } +DylibFile::DylibFile(MemoryBufferRef mb) : InputFile(DylibKind, mb) { + auto *buf = reinterpret_cast(mb.getBufferStart()); + auto *hdr = reinterpret_cast(mb.getBufferStart()); + + // Initialize dylibName. + if (const load_command *cmd = findCommand(hdr, LC_ID_DYLIB)) { + auto *c = reinterpret_cast(cmd); + dylibName = reinterpret_cast(cmd) + read32le(&c->dylib.name); + } else { + error("dylib " + getName() + " missing LC_ID_DYLIB load command"); + return; + } + + // Initialize symbols. + if (const load_command *cmd = findCommand(hdr, LC_SYMTAB)) { + auto *c = reinterpret_cast(cmd); + const char *strtab = reinterpret_cast(buf + c->stroff); + ArrayRef nList( + reinterpret_cast(buf + c->symoff), c->nsyms); + + symbols.reserve(c->nsyms); + + for (const nlist_64 &sym : nList) { + StringRef name = strtab + sym.n_strx; + // TODO: Figure out what to do about undefined symbols: ignore or warn + // if unsatisfied? Also make sure we handle re-exported symbols + // correctly. + symbols.push_back(symtab->addDylib(name, this)); + } + } +} + // Returns "" or "baz.o". std::string lld::toString(const InputFile *file) { return file ? std::string(file->getName()) : ""; diff --git a/lld/MachO/InputFiles.h b/lld/MachO/InputFiles.h index 7b13b1f9f6bd..72a0ae4592a0 100644 --- a/lld/MachO/InputFiles.h +++ b/lld/MachO/InputFiles.h @@ -27,17 +27,16 @@ class InputFile { public: enum Kind { ObjKind, + DylibKind, }; virtual ~InputFile() = default; - Kind kind() const { return fileKind; } StringRef getName() const { return mb.getBufferIdentifier(); } MemoryBufferRef mb; std::vector symbols; std::vector sections; - StringRef dylibName; protected: InputFile(Kind kind, MemoryBufferRef mb) : mb(mb), fileKind(kind) {} @@ -58,6 +57,16 @@ public: static bool classof(const InputFile *f) { return f->kind() == ObjKind; } }; +// .dylib file +class DylibFile : public InputFile { +public: + explicit DylibFile(MemoryBufferRef mb); + static bool classof(const InputFile *f) { return f->kind() == DylibKind; } + + StringRef dylibName; + uint64_t ordinal = 0; // Ordinal numbering starts from 1, so 0 is a sentinel +}; + extern std::vector inputFiles; llvm::Optional readFile(StringRef path); diff --git a/lld/MachO/InputSection.cpp b/lld/MachO/InputSection.cpp index 49dccf641c4c..4974d81c9ac7 100644 --- a/lld/MachO/InputSection.cpp +++ b/lld/MachO/InputSection.cpp @@ -8,6 +8,7 @@ #include "InputSection.h" #include "Symbols.h" +#include "SyntheticSections.h" #include "Target.h" #include "lld/Common/Memory.h" #include "llvm/Support/Endian.h" @@ -24,12 +25,17 @@ void InputSection::writeTo(uint8_t *buf) { for (Reloc &r : relocs) { uint64_t va = 0; - if (auto *s = r.target.dyn_cast()) - va = s->getVA(); - else if (auto *isec = r.target.dyn_cast()) + if (auto *s = r.target.dyn_cast()) { + if (auto *dylibSymbol = dyn_cast(s)) { + va = in.got->addr - ImageBase + dylibSymbol->gotIndex * WordSize; + } else { + va = s->getVA(); + } + } else if (auto *isec = r.target.dyn_cast()) { va = isec->addr; - else + } else { llvm_unreachable("Unknown relocation target"); + } uint64_t val = va + r.addend; if (1) // TODO: handle non-pcrel relocations diff --git a/lld/MachO/InputSection.h b/lld/MachO/InputSection.h index 05da49726bac..fea88ea1d2be 100644 --- a/lld/MachO/InputSection.h +++ b/lld/MachO/InputSection.h @@ -19,6 +19,7 @@ namespace macho { class InputFile; class InputSection; +class OutputSegment; class Symbol; struct Reloc { @@ -30,9 +31,12 @@ struct Reloc { class InputSection { public: - void writeTo(uint8_t *buf); + virtual ~InputSection() = default; + virtual void writeTo(uint8_t *buf); + virtual size_t getSize() const { return data.size(); } InputFile *file = nullptr; + OutputSegment *parent = nullptr; StringRef name; StringRef segname; diff --git a/lld/MachO/Options.td b/lld/MachO/Options.td index 2d9713c342e6..5a291d022edc 100644 --- a/lld/MachO/Options.td +++ b/lld/MachO/Options.td @@ -1,10 +1,19 @@ include "llvm/Option/OptParser.td" +def L: JoinedOrSeparate<["-"], "L">, MetaVarName<"">, + HelpText<"Add directory to library search path">; + +def Z: Flag<["-"], "Z">, + HelpText<"Do not add standard directories to library search path">; + def arch: Separate<["-"], "arch">, MetaVarName<"">, HelpText<"Architecture to link">; def e: Separate<["-"], "e">, HelpText<"Name of entry point symbol">; +def l: Joined<["-"], "l">, MetaVarName<"">, + HelpText<"Base name of library searched for in -L directories">; + def o: Separate<["-"], "o">, MetaVarName<"">, HelpText<"Path to file to write output">; diff --git a/lld/MachO/OutputSegment.h b/lld/MachO/OutputSegment.h index 108c1804d031..211750de8761 100644 --- a/lld/MachO/OutputSegment.h +++ b/lld/MachO/OutputSegment.h @@ -19,8 +19,13 @@ class InputSection; class OutputSegment { public: + InputSection *firstSection() const { return sections.front().second.at(0); } + + InputSection *lastSection() const { return sections.back().second.back(); } + StringRef name; uint32_t perms; + uint8_t index; llvm::MapVector> sections; }; diff --git a/lld/MachO/SymbolTable.cpp b/lld/MachO/SymbolTable.cpp index ce54416a96e7..41446d6df4db 100644 --- a/lld/MachO/SymbolTable.cpp +++ b/lld/MachO/SymbolTable.cpp @@ -59,4 +59,14 @@ Symbol *SymbolTable::addUndefined(StringRef name) { return s; } +Symbol *SymbolTable::addDylib(StringRef name, DylibFile *file) { + Symbol *s; + bool wasInserted; + std::tie(s, wasInserted) = insert(name); + + if (wasInserted) + replaceSymbol(s, file, name); + return s; +} + SymbolTable *macho::symtab; diff --git a/lld/MachO/SymbolTable.h b/lld/MachO/SymbolTable.h index 2027d367ae4b..95e7a88a38da 100644 --- a/lld/MachO/SymbolTable.h +++ b/lld/MachO/SymbolTable.h @@ -16,9 +16,9 @@ namespace lld { namespace macho { -class InputFile; -class InputSection; class ArchiveFile; +class DylibFile; +class InputSection; class Symbol; class SymbolTable { @@ -27,6 +27,8 @@ public: Symbol *addUndefined(StringRef name); + Symbol *addDylib(StringRef name, DylibFile *file); + ArrayRef getSymbols() const { return symVector; } Symbol *find(StringRef name); diff --git a/lld/MachO/Symbols.h b/lld/MachO/Symbols.h index f754ec847507..65c54feb5372 100644 --- a/lld/MachO/Symbols.h +++ b/lld/MachO/Symbols.h @@ -18,7 +18,7 @@ namespace lld { namespace macho { class InputSection; -class InputFile; +class DylibFile; class ArchiveFile; struct StringRefZ { @@ -34,6 +34,7 @@ public: enum Kind { DefinedKind, UndefinedKind, + DylibKind, }; Kind kind() const { return static_cast(symbolKind); } @@ -42,11 +43,8 @@ public: uint64_t getVA() const; - InputFile *file; - protected: - Symbol(Kind k, InputFile *file, StringRefZ name) - : file(file), symbolKind(k), name(name) {} + Symbol(Kind k, StringRefZ name) : symbolKind(k), name(name) {} Kind symbolKind; StringRefZ name; @@ -55,7 +53,7 @@ protected: class Defined : public Symbol { public: Defined(StringRefZ name, InputSection *isec, uint32_t value) - : Symbol(DefinedKind, nullptr, name), isec(isec), value(value) {} + : Symbol(DefinedKind, name), isec(isec), value(value) {} InputSection *isec; uint32_t value; @@ -65,11 +63,22 @@ public: class Undefined : public Symbol { public: - Undefined(StringRefZ name) : Symbol(UndefinedKind, nullptr, name) {} + Undefined(StringRefZ name) : Symbol(UndefinedKind, name) {} static bool classof(const Symbol *s) { return s->kind() == UndefinedKind; } }; +class DylibSymbol : public Symbol { +public: + DylibSymbol(DylibFile *file, StringRefZ name) + : Symbol(DylibKind, name), file(file) {} + + static bool classof(const Symbol *s) { return s->kind() == DylibKind; } + + DylibFile *file; + uint32_t gotIndex = UINT32_MAX; +}; + inline uint64_t Symbol::getVA() const { if (auto *d = dyn_cast(this)) return d->isec->addr + d->value - ImageBase; @@ -79,6 +88,7 @@ inline uint64_t Symbol::getVA() const { union SymbolUnion { alignas(Defined) char a[sizeof(Defined)]; alignas(Undefined) char b[sizeof(Undefined)]; + alignas(DylibSymbol) char c[sizeof(DylibSymbol)]; }; template diff --git a/lld/MachO/SyntheticSections.cpp b/lld/MachO/SyntheticSections.cpp new file mode 100644 index 000000000000..3212aea4cfc4 --- /dev/null +++ b/lld/MachO/SyntheticSections.cpp @@ -0,0 +1,36 @@ +//===- SyntheticSections.cpp ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "SyntheticSections.h" +#include "Symbols.h" + +using namespace llvm::MachO; + +namespace lld { +namespace macho { + +GotSection::GotSection() { + segname = "__DATA_CONST"; + name = "__got"; + align = 8; + flags = S_NON_LAZY_SYMBOL_POINTERS; + + // TODO: section_64::reserved1 should be an index into the indirect symbol + // table, which we do not currently emit +} + +void GotSection::addEntry(DylibSymbol &sym) { + if (entries.insert(&sym)) { + sym.gotIndex = entries.size() - 1; + } +} + +InStruct in; + +} // namespace macho +} // namespace lld diff --git a/lld/MachO/SyntheticSections.h b/lld/MachO/SyntheticSections.h new file mode 100644 index 000000000000..ba5a8f35b28b --- /dev/null +++ b/lld/MachO/SyntheticSections.h @@ -0,0 +1,52 @@ +//===- SyntheticSections.h -------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLD_MACHO_SYNTHETIC_SECTIONS_H +#define LLD_MACHO_SYNTHETIC_SECTIONS_H + +#include "InputSection.h" +#include "Target.h" +#include "llvm/ADT/SetVector.h" + +namespace lld { +namespace macho { + +class DylibSymbol; + +// This section will be populated by dyld with addresses to non-lazily-loaded +// dylib symbols. +class GotSection : public InputSection { +public: + GotSection(); + + void addEntry(DylibSymbol &sym); + const llvm::SetVector &getEntries() const { + return entries; + } + + size_t getSize() const override { return entries.size() * WordSize; } + + void writeTo(uint8_t *buf) override { + // Nothing to write, GOT contains all zeros at link time; it's populated at + // runtime by dyld. + } + +private: + llvm::SetVector entries; +}; + +struct InStruct { + GotSection *got; +}; + +extern InStruct in; + +} // namespace macho +} // namespace lld + +#endif diff --git a/lld/MachO/Target.h b/lld/MachO/Target.h index 9ebc56c9ffbd..342a204b7b10 100644 --- a/lld/MachO/Target.h +++ b/lld/MachO/Target.h @@ -15,6 +15,9 @@ namespace lld { namespace macho { enum { + // We are currently only supporting 64-bit targets since macOS and iOS are + // deprecating 32-bit apps. + WordSize = 8, PageSize = 4096, ImageBase = 4096, MaxAlignmentPowerOf2 = 32, diff --git a/lld/MachO/Writer.cpp b/lld/MachO/Writer.cpp index ce0c30d5300b..7c38487c063c 100644 --- a/lld/MachO/Writer.cpp +++ b/lld/MachO/Writer.cpp @@ -13,11 +13,13 @@ #include "OutputSegment.h" #include "SymbolTable.h" #include "Symbols.h" +#include "SyntheticSections.h" #include "Target.h" #include "lld/Common/ErrorHandler.h" #include "lld/Common/Memory.h" #include "llvm/BinaryFormat/MachO.h" +#include "llvm/Support/EndianStream.h" #include "llvm/Support/LEB128.h" #include "llvm/Support/MathExtras.h" @@ -44,8 +46,11 @@ public: Writer() : buffer(errorHandler().outputBuffer) {} void createLoadCommands(); + void scanRelocations(); void assignAddresses(); + void createDyldInfoContents(); + void openFile(); void writeHeader(); void writeSections(); @@ -83,8 +88,9 @@ public: c->cmd = LC_SEGMENT_64; c->cmdsize = getSize(); strcpy(c->segname, "__LINKEDIT"); + c->vmaddr = addr; c->fileoff = fileOff; - c->filesize = contents.size(); + c->filesize = c->vmsize = contents.size(); c->maxprot = VM_PROT_READ | VM_PROT_WRITE; c->initprot = VM_PROT_READ; } @@ -92,6 +98,7 @@ public: uint64_t getOffset() const { return fileOff + contents.size(); } uint64_t fileOff = 0; + uint64_t addr = 0; SmallVector contents; }; @@ -103,10 +110,14 @@ public: auto *c = reinterpret_cast(buf); c->cmd = LC_DYLD_INFO_ONLY; c->cmdsize = getSize(); + c->bind_off = bindOff; + c->bind_size = bindSize; c->export_off = exportOff; c->export_size = exportSize; } + uint64_t bindOff = 0; + uint64_t bindSize = 0; uint64_t exportOff = 0; uint64_t exportSize = 0; }; @@ -139,16 +150,14 @@ public: c->cmdsize = getSize(); memcpy(c->segname, name.data(), name.size()); - InputSection *firstSec = seg->sections.front().second[0]; - InputSection *lastSec = seg->sections.back().second.back(); - // dyld3's MachOLoaded::getSlide() assumes that the __TEXT segment starts // from the beginning of the file (i.e. the header). // TODO: replace this logic by creating a synthetic __TEXT,__mach_header // section instead. - c->fileoff = name == "__TEXT" ? 0 : firstSec->addr - ImageBase; + c->fileoff = name == "__TEXT" ? 0 : seg->firstSection()->addr - ImageBase; c->vmaddr = c->fileoff + ImageBase; - c->vmsize = c->filesize = lastSec->addr + lastSec->data.size() - c->vmaddr; + c->vmsize = c->filesize = + seg->lastSection()->addr + seg->lastSection()->getSize() - c->vmaddr; c->maxprot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; c->initprot = seg->perms; c->nsects = seg->sections.size(); @@ -171,7 +180,7 @@ public: maxAlign = std::max(maxAlign, section->align); sectHdr->align = Log2_32(maxAlign); sectHdr->flags = sections[0]->flags; - sectHdr->size = sections.back()->addr + sections.back()->data.size() - + sectHdr->size = sections.back()->addr + sections.back()->getSize() - sections[0]->addr; } } @@ -265,13 +274,34 @@ void Writer::createLoadCommands() { loadCommands.push_back(make()); loadCommands.push_back(make()); loadCommands.push_back(make()); + + uint8_t segIndex = 1; // LCPagezero is a segment load command + for (OutputSegment *seg : outputSegments) { + if (!seg->sections.empty()) { + loadCommands.push_back(make(seg->name, seg)); + seg->index = segIndex++; + } + } + + uint64_t dylibOrdinal = 1; + for (InputFile *file : inputFiles) { + if (auto *dylibFile = dyn_cast(file)) { + loadCommands.push_back(make(dylibFile->dylibName)); + dylibFile->ordinal = dylibOrdinal++; + } + } + // TODO: dyld requires libSystem to be loaded. libSystem is a universal // binary and we don't have support for that yet, so mock it out here. loadCommands.push_back(make("/usr/lib/libSystem.B.dylib")); +} - for (OutputSegment *seg : outputSegments) - if (!seg->sections.empty()) - loadCommands.push_back(make(seg->name, seg)); +void Writer::scanRelocations() { + for (InputSection *sect : inputSections) + for (Reloc &r : sect->relocs) + if (auto *s = r.target.dyn_cast()) + if (auto *dylibSymbol = dyn_cast(s)) + in.got->addEntry(*dylibSymbol); } void Writer::assignAddresses() { @@ -291,14 +321,56 @@ void Writer::assignAddresses() { for (InputSection *isec : sections) { addr = alignTo(addr, isec->align); isec->addr = addr; - addr += isec->data.size(); + addr += isec->getSize(); } } } + addr = alignTo(addr, PageSize); + linkEditSeg->addr = addr; linkEditSeg->fileOff = addr - ImageBase; } +// LC_DYLD_INFO_ONLY contains symbol import/export information. Imported +// symbols are described by a sequence of bind opcodes, which allow for a +// compact encoding. Exported symbols are described using a trie. +void Writer::createDyldInfoContents() { + uint64_t sectionStart = linkEditSeg->getOffset(); + raw_svector_ostream os{linkEditSeg->contents}; + + if (in.got->getSize() != 0) { + // Emit bind opcodes, which tell dyld which dylib symbols to load. + + // Tell dyld to write to the section containing the GOT. + os << static_cast(BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB | + in.got->parent->index); + encodeULEB128(in.got->addr - in.got->parent->firstSection()->addr, os); + for (const DylibSymbol *sym : in.got->getEntries()) { + // TODO: Implement compact encoding -- we only need to encode the + // differences between consecutive symbol entries. + if (sym->file->ordinal <= BIND_IMMEDIATE_MASK) { + os << static_cast(BIND_OPCODE_SET_DYLIB_ORDINAL_IMM | + sym->file->ordinal); + } else { + error("TODO: Support larger dylib symbol ordinals"); + continue; + } + os << static_cast(BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM) + << sym->getName() << '\0' + << static_cast(BIND_OPCODE_SET_TYPE_IMM | BIND_TYPE_POINTER) + << static_cast(BIND_OPCODE_DO_BIND); + } + + os << static_cast(BIND_OPCODE_DONE); + + dyldInfoSeg->bindOff = sectionStart; + dyldInfoSeg->bindSize = linkEditSeg->getOffset() - sectionStart; + } + + // TODO: emit bind opcodes for lazy symbols. + // TODO: Implement symbol export trie. +} + void Writer::openFile() { Expected> bufferOrErr = FileOutputBuffer::create(config->outputFile, fileSize, @@ -342,7 +414,11 @@ void Writer::writeSections() { void Writer::run() { createLoadCommands(); + scanRelocations(); assignAddresses(); + + // Fill __LINKEDIT contents + createDyldInfoContents(); fileSize = linkEditSeg->fileOff + linkEditSeg->contents.size(); openFile(); @@ -357,3 +433,8 @@ void Writer::run() { } void macho::writeResult() { Writer().run(); } + +void macho::createSyntheticSections() { + in.got = make(); + inputSections.push_back(in.got); +} diff --git a/lld/MachO/Writer.h b/lld/MachO/Writer.h index a0b90631f9ef..accdedca142b 100644 --- a/lld/MachO/Writer.h +++ b/lld/MachO/Writer.h @@ -14,6 +14,8 @@ namespace macho { void writeResult(); +void createSyntheticSections(); + } // namespace macho } // namespace lld diff --git a/lld/test/MachO/Inputs/goodbye-dylib.yaml b/lld/test/MachO/Inputs/goodbye-dylib.yaml new file mode 100644 index 000000000000..55797f7cc22a --- /dev/null +++ b/lld/test/MachO/Inputs/goodbye-dylib.yaml @@ -0,0 +1,175 @@ +## This yaml file was originally generated from linking the following source +## input with ld64: +## +## .section __TEXT,__cstring +## .globl _goodbye_world +## +## _goodbye_world: +## .asciz "Goodbye world!\n" +## +## When lld can produce dylibs, we will use that instead for our test setup. + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x01000007 + cpusubtype: 0x00000003 + filetype: 0x00000006 + ncmds: 11 + sizeofcmds: 624 + flags: 0x00100085 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 232 + segname: __TEXT + vmaddr: 0 + vmsize: 4096 + fileoff: 0 + filesize: 4096 + maxprot: 5 + initprot: 5 + nsects: 2 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000FF0 + size: 0 + offset: 0x00000FF0 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '' + - sectname: __cstring + segname: __TEXT + addr: 0x0000000000000FF0 + size: 16 + offset: 0x00000FF0 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000002 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 476F6F6462796520776F726C64210A00 + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 4096 + vmsize: 4096 + fileoff: 4096 + filesize: 72 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_ID_DYLIB + cmdsize: 64 + dylib: + name: 24 + timestamp: 1 + current_version: 0 + compatibility_version: 0 + PayloadString: '@executable_path/libgoodbye.dylib' + ZeroPadBytes: 7 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 4096 + export_size: 24 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 4128 + nsyms: 1 + stroff: 4144 + strsize: 24 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_UUID + cmdsize: 24 + uuid: EA09CDDC-A3EA-3EB9-8C4F-334077FE6E5A + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 659200 + sdk: 659200 + ntools: 1 + Tools: + - tool: 3 + version: 34734080 + - cmd: LC_SOURCE_VERSION + cmdsize: 16 + version: 0 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 4120 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 4128 + datasize: 0 +LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0000000000000000 + Address: 0x0000000000000000 + Other: 0x0000000000000000 + ImportName: '' + Children: + - TerminalSize: 3 + NodeOffset: 18 + Name: _goodbye_world + Flags: 0x0000000000000000 + Address: 0x0000000000000FF0 + Other: 0x0000000000000000 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0x0F + n_sect: 2 + n_desc: 0 + n_value: 4080 + StringTable: + - ' ' + - _goodbye_world + - '' + - '' + - '' + - '' + - '' + - '' + - '' +... diff --git a/lld/test/MachO/Inputs/hello-dylib.yaml b/lld/test/MachO/Inputs/hello-dylib.yaml new file mode 100644 index 000000000000..fde922856efa --- /dev/null +++ b/lld/test/MachO/Inputs/hello-dylib.yaml @@ -0,0 +1,169 @@ +## This yaml file was originally generated from linking the following source +## input with ld64: +## +## .section __TEXT,__cstring +## .globl _hello_world +## +## _hello_world: +## .asciz "Hello world!\n" +## +## When lld can produce dylibs, we will use that instead for our test setup. + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x01000007 + cpusubtype: 0x00000003 + filetype: 0x00000006 + ncmds: 11 + sizeofcmds: 616 + flags: 0x00100085 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 232 + segname: __TEXT + vmaddr: 0 + vmsize: 4096 + fileoff: 0 + filesize: 4096 + maxprot: 5 + initprot: 5 + nsects: 2 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000FF2 + size: 0 + offset: 0x00000FF2 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '' + - sectname: __cstring + segname: __TEXT + addr: 0x0000000000000FF2 + size: 14 + offset: 0x00000FF2 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000002 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 48656C6C6F20776F726C64210A00 + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 4096 + vmsize: 4096 + fileoff: 4096 + filesize: 64 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_ID_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 1 + current_version: 0 + compatibility_version: 0 + PayloadString: '@executable_path/libhello.dylib' + ZeroPadBytes: 1 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 4096 + export_size: 24 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 4128 + nsyms: 1 + stroff: 4144 + strsize: 16 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4826226E-9210-3984-A388-D5BD6D6DB368 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 659200 + sdk: 659200 + ntools: 1 + Tools: + - tool: 3 + version: 34734080 + - cmd: LC_SOURCE_VERSION + cmdsize: 16 + version: 0 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 4120 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 4128 + datasize: 0 +LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0000000000000000 + Address: 0x0000000000000000 + Other: 0x0000000000000000 + ImportName: '' + Children: + - TerminalSize: 3 + NodeOffset: 16 + Name: _hello_world + Flags: 0x0000000000000000 + Address: 0x0000000000000FF2 + Other: 0x0000000000000000 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0x0F + n_sect: 2 + n_desc: 0 + n_value: 4082 + StringTable: + - ' ' + - _hello_world + - '' +... diff --git a/lld/test/MachO/Inputs/no-id-dylib.yaml b/lld/test/MachO/Inputs/no-id-dylib.yaml new file mode 100644 index 000000000000..86657daf7f21 --- /dev/null +++ b/lld/test/MachO/Inputs/no-id-dylib.yaml @@ -0,0 +1,160 @@ +## This yaml file was originally generated from linking the following source +## input with ld64: +## +## .section __TEXT,__cstring +## .globl _hello_world +## +## _hello_world: +## .asciz "Hello world!\n" +## +## Then we deleted the LC_ID_DYLIB command from the YAML file. + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x01000007 + cpusubtype: 0x00000003 + filetype: 0x00000006 + ncmds: 10 + sizeofcmds: 616 + flags: 0x00100085 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 232 + segname: __TEXT + vmaddr: 0 + vmsize: 4096 + fileoff: 0 + filesize: 4096 + maxprot: 5 + initprot: 5 + nsects: 2 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000FF2 + size: 0 + offset: 0x00000FF2 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '' + - sectname: __cstring + segname: __TEXT + addr: 0x0000000000000FF2 + size: 14 + offset: 0x00000FF2 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000002 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 48656C6C6F20776F726C64210A00 + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 4096 + vmsize: 4096 + fileoff: 4096 + filesize: 64 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 4096 + export_size: 24 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 4128 + nsyms: 1 + stroff: 4144 + strsize: 16 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4826226E-9210-3984-A388-D5BD6D6DB368 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 659200 + sdk: 659200 + ntools: 1 + Tools: + - tool: 3 + version: 34734080 + - cmd: LC_SOURCE_VERSION + cmdsize: 16 + version: 0 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 4120 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 4128 + datasize: 0 +LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0000000000000000 + Address: 0x0000000000000000 + Other: 0x0000000000000000 + ImportName: '' + Children: + - TerminalSize: 3 + NodeOffset: 16 + Name: _hello_world + Flags: 0x0000000000000000 + Address: 0x0000000000000FF2 + Other: 0x0000000000000000 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0x0F + n_sect: 2 + n_desc: 0 + n_value: 4082 + StringTable: + - ' ' + - _hello_world + - '' +... diff --git a/lld/test/MachO/dylink.s b/lld/test/MachO/dylink.s new file mode 100644 index 000000000000..6ec7ed05a40f --- /dev/null +++ b/lld/test/MachO/dylink.s @@ -0,0 +1,35 @@ +# REQUIRES: x86 +# RUN: mkdir -p %t +# RUN: yaml2obj %p/Inputs/hello-dylib.yaml -o %t/libhello.dylib +# RUN: yaml2obj %p/Inputs/goodbye-dylib.yaml -o %t/libgoodbye.dylib +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/dylink.o +# RUN: lld -flavor darwinnew -o %t/dylink -Z -L%t -lhello -lgoodbye %t/dylink.o +# RUN: llvm-objdump --bind -d %t/dylink | FileCheck %s + +# CHECK: movq [[#%u, HELLO_OFF:]](%rip), %rsi +# CHECK-NEXT: [[#%x, HELLO_RIP:]]: + +# CHECK: movq [[#%u, GOODBYE_OFF:]](%rip), %rsi +# CHECK-NEXT: [[#%x, GOODBYE_RIP:]]: + +# CHECK-LABEL: Bind table: +# CHECK-DAG: __DATA_CONST __got 0x{{0*}}[[#%x, HELLO_RIP + HELLO_OFF]] pointer 0 libhello _hello_world +# CHECK-DAG: __DATA_CONST __got 0x{{0*}}[[#%x, GOODBYE_RIP + GOODBYE_OFF]] pointer 0 libgoodbye _goodbye_world + +.section __TEXT,__text +.globl _main + +_main: + movl $0x2000004, %eax # write() syscall + mov $1, %rdi # stdout + movq _hello_world@GOTPCREL(%rip), %rsi + mov $13, %rdx # length of str + syscall + + movl $0x2000004, %eax # write() syscall + mov $1, %rdi # stdout + movq _goodbye_world@GOTPCREL(%rip), %rsi + mov $15, %rdx # length of str + syscall + mov $0, %rax + ret diff --git a/lld/test/MachO/missing-dylib.s b/lld/test/MachO/missing-dylib.s new file mode 100644 index 000000000000..d66ff5256401 --- /dev/null +++ b/lld/test/MachO/missing-dylib.s @@ -0,0 +1,5 @@ +# REQUIRES: x86 +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t.o +# RUN: not lld -flavor darwinnew -Z -o %t -lmissing %t.o 2>&1 | FileCheck %s + +# CHECK: library not found for -lmissing diff --git a/lld/test/MachO/no-id-dylink.s b/lld/test/MachO/no-id-dylink.s new file mode 100644 index 000000000000..2fcd10da384c --- /dev/null +++ b/lld/test/MachO/no-id-dylink.s @@ -0,0 +1,13 @@ +# REQUIRES: x86 +# RUN: mkdir -p %t +# RUN: yaml2obj %p/Inputs/no-id-dylib.yaml -o %t/libnoid.dylib +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/no-id-dylink.o +# RUN: not lld -flavor darwinnew -o %t/no-id-dylink -Z -L%t -lnoid %t/no-id-dylink.o 2>&1 | FileCheck %s +# CHECK: dylib {{.*}}libnoid.dylib missing LC_ID_DYLIB load command + +.text +.globl _main + +_main: + mov $0, %rax + ret diff --git a/lld/test/MachO/search-paths.test b/lld/test/MachO/search-paths.test new file mode 100644 index 000000000000..84e8ba93c616 --- /dev/null +++ b/lld/test/MachO/search-paths.test @@ -0,0 +1,12 @@ +RUN: mkdir -p %t + +RUN: lld -flavor darwinnew -v -L%t 2>&1 | FileCheck -DDIR=%t %s +CHECK: Library search paths: +CHECK-NEXT: [[DIR]] +CHECK-NEXT: /usr/lib +CHECK-NEXT: /usr/local/lib + +RUN: lld -flavor darwinnew -v -L%t -Z 2>&1 | FileCheck -DDIR=%t --check-prefix=CHECK_Z %s +CHECK_Z: Library search paths: +CHECK_Z-NEXT: [[DIR]] +CHECK_Z-NOT: /usr/ -- GitLab From ba942610f6be63fe11b61e637ca5db2c4ef9ba8a Mon Sep 17 00:00:00 2001 From: "Joel E. Denny" Date: Tue, 21 Apr 2020 16:27:32 -0400 Subject: [PATCH 009/910] [OpenMP] Add scaffolding for negative runtime tests Without this patch, the openmp project's test suites do not appear to have support for negative tests. However, D78170 needs to add a test that an expected runtime failure occurs. This patch makes `not` visible in all of the openmp project's test suites. In all but `libomptarget/test`, it should be possible for a test author to insert `not` before a use of the lit substitution for running a test program. In `libomptarget/test`, that substitution is target-specific, and its value is `echo` when the target is not available. In that case, inserting `not` before a lit substitution would expect an `echo` fail, so this patch instead defines a separate lit substitution for expected runtime fails. Reviewed By: jdoerfert, Hahnfeld Differential Revision: https://reviews.llvm.org/D78566 --- openmp/README.rst | 4 ++++ openmp/cmake/OpenMPTesting.cmake | 12 ++++++++++++ openmp/libomptarget/deviceRTLs/nvptx/test/lit.cfg | 1 + .../deviceRTLs/nvptx/test/lit.site.cfg.in | 1 + openmp/libomptarget/test/lit.cfg | 7 +++++++ openmp/libomptarget/test/lit.site.cfg.in | 1 + openmp/runtime/test/lit.cfg | 1 + openmp/runtime/test/lit.site.cfg.in | 1 + openmp/tools/archer/tests/lit.cfg | 1 + openmp/tools/archer/tests/lit.site.cfg.in | 1 + 10 files changed, 30 insertions(+) diff --git a/openmp/README.rst b/openmp/README.rst index 55342e4dbac5..aac0f7fc10d3 100644 --- a/openmp/README.rst +++ b/openmp/README.rst @@ -130,6 +130,10 @@ Options for all Libraries Specify full path to ``FileCheck`` executable for running tests. The default is to search the ``PATH`` and the directory in **OPENMP_LLVM_TOOLS_DIR**. +**OPENMP_NOT_EXECUTABLE** = ``/path/to/not`` + Specify full path to ``not`` executable for running tests. The default + is to search the ``PATH`` and the directory in **OPENMP_LLVM_TOOLS_DIR**. + Options for ``libomp`` ---------------------- diff --git a/openmp/cmake/OpenMPTesting.cmake b/openmp/cmake/OpenMPTesting.cmake index c776b8ab6892..f854e4ddc38d 100644 --- a/openmp/cmake/OpenMPTesting.cmake +++ b/openmp/cmake/OpenMPTesting.cmake @@ -34,6 +34,17 @@ function(find_standalone_test_dependencies) set(ENABLE_CHECK_TARGETS FALSE PARENT_SCOPE) return() endif() + + find_program(OPENMP_NOT_EXECUTABLE + NAMES not + PATHS ${OPENMP_LLVM_TOOLS_DIR}) + if (NOT OPENMP_NOT_EXECUTABLE) + message(STATUS "Cannot find 'not'.") + message(STATUS "Please put 'not' in your PATH, set OPENMP_NOT_EXECUTABLE to its full path, or point OPENMP_LLVM_TOOLS_DIR to its directory.") + message(WARNING "The check targets will not be available!") + set(ENABLE_CHECK_TARGETS FALSE PARENT_SCOPE) + return() + endif() endfunction() if (${OPENMP_STANDALONE_BUILD}) @@ -55,6 +66,7 @@ if (${OPENMP_STANDALONE_BUILD}) separate_arguments(OPENMP_LIT_ARGS) else() set(OPENMP_FILECHECK_EXECUTABLE ${LLVM_RUNTIME_OUTPUT_INTDIR}/FileCheck) + set(OPENMP_NOT_EXECUTABLE ${LLVM_RUNTIME_OUTPUT_INTDIR}/not) endif() # Macro to extract information about compiler from file. (no own scope) diff --git a/openmp/libomptarget/deviceRTLs/nvptx/test/lit.cfg b/openmp/libomptarget/deviceRTLs/nvptx/test/lit.cfg index 0774c25af20c..d9f8bd779f2d 100644 --- a/openmp/libomptarget/deviceRTLs/nvptx/test/lit.cfg +++ b/openmp/libomptarget/deviceRTLs/nvptx/test/lit.cfg @@ -67,3 +67,4 @@ config.substitutions.append(("%openmp_flags", config.test_openmp_flags)) config.substitutions.append(("%flags", config.test_flags)) config.substitutions.append(("%run", "%t")) +config.substitutions.append((r"\bnot\b", config.libomptarget_not)) diff --git a/openmp/libomptarget/deviceRTLs/nvptx/test/lit.site.cfg.in b/openmp/libomptarget/deviceRTLs/nvptx/test/lit.site.cfg.in index d9c14cbc5326..f0e02e5d46ac 100644 --- a/openmp/libomptarget/deviceRTLs/nvptx/test/lit.site.cfg.in +++ b/openmp/libomptarget/deviceRTLs/nvptx/test/lit.site.cfg.in @@ -9,6 +9,7 @@ config.library_dir = "@LIBOMPTARGET_LIBRARY_DIR@" config.omp_header_directory = "@LIBOMPTARGET_OPENMP_HEADER_FOLDER@" config.omp_host_rtl_directory = "@LIBOMPTARGET_OPENMP_HOST_RTL_FOLDER@" config.libomptarget_filecheck = "@OPENMP_FILECHECK_EXECUTABLE@" +config.libomptarget_not = "@OPENMP_NOT_EXECUTABLE@" # Let the main config do the real work. lit_config.load_config(config, "@CMAKE_CURRENT_SOURCE_DIR@/lit.cfg") diff --git a/openmp/libomptarget/test/lit.cfg b/openmp/libomptarget/test/lit.cfg index 43116055c82b..68182261646c 100644 --- a/openmp/libomptarget/test/lit.cfg +++ b/openmp/libomptarget/test/lit.cfg @@ -101,6 +101,9 @@ for libomptarget_target in config.libomptarget_all_targets: config.substitutions.append(("%libomptarget-run-" + \ libomptarget_target, \ "%t-" + libomptarget_target)) + config.substitutions.append(("%libomptarget-run-fail-" + \ + libomptarget_target, \ + "not %t-" + libomptarget_target)) config.substitutions.append(("%clangxx-" + libomptarget_target, \ "%clangxx %openmp_flags %flags -fopenmp-targets=" + libomptarget_target)) config.substitutions.append(("%clang-" + libomptarget_target, \ @@ -129,6 +132,9 @@ for libomptarget_target in config.libomptarget_all_targets: config.substitutions.append(("%libomptarget-run-" + \ libomptarget_target, \ "echo ignored-command")) + config.substitutions.append(("%libomptarget-run-fail-" + \ + libomptarget_target, \ + "echo ignored-command")) config.substitutions.append(("%clang-" + libomptarget_target, \ "echo ignored-command")) config.substitutions.append(("%clangxx-" + libomptarget_target, \ @@ -140,3 +146,4 @@ config.substitutions.append(("%clangxx", config.test_cxx_compiler)) config.substitutions.append(("%clang", config.test_c_compiler)) config.substitutions.append(("%openmp_flags", config.test_openmp_flags)) config.substitutions.append(("%flags", config.test_flags)) +config.substitutions.append((r"\bnot\b", config.libomptarget_not)) diff --git a/openmp/libomptarget/test/lit.site.cfg.in b/openmp/libomptarget/test/lit.site.cfg.in index 26ef4920d91e..53c91c91def7 100644 --- a/openmp/libomptarget/test/lit.site.cfg.in +++ b/openmp/libomptarget/test/lit.site.cfg.in @@ -13,6 +13,7 @@ config.operating_system = "@CMAKE_SYSTEM_NAME@" config.libomptarget_all_targets = "@LIBOMPTARGET_ALL_TARGETS@".split() config.libomptarget_system_targets = "@LIBOMPTARGET_SYSTEM_TARGETS@".split() config.libomptarget_filecheck = "@OPENMP_FILECHECK_EXECUTABLE@" +config.libomptarget_not = "@OPENMP_NOT_EXECUTABLE@" config.libomptarget_debug = @LIBOMPTARGET_DEBUG@ # Let the main config do the real work. diff --git a/openmp/runtime/test/lit.cfg b/openmp/runtime/test/lit.cfg index 8e15a38e625b..9a9090660f8c 100644 --- a/openmp/runtime/test/lit.cfg +++ b/openmp/runtime/test/lit.cfg @@ -127,6 +127,7 @@ config.substitutions.append(("%clang", config.test_c_compiler)) config.substitutions.append(("%openmp_flags", config.test_openmp_flags)) config.substitutions.append(("%flags", config.test_flags)) config.substitutions.append(("%python", '"%s"' % (sys.executable))) +config.substitutions.append((r"\bnot\b", config.test_not)) if config.has_ompt: config.substitutions.append(("FileCheck", "tee %%t.out | %s" % config.test_filecheck)) diff --git a/openmp/runtime/test/lit.site.cfg.in b/openmp/runtime/test/lit.site.cfg.in index c2825ee4eab5..a77ecc3bbc68 100644 --- a/openmp/runtime/test/lit.site.cfg.in +++ b/openmp/runtime/test/lit.site.cfg.in @@ -4,6 +4,7 @@ config.test_c_compiler = "@OPENMP_TEST_C_COMPILER@" config.test_cxx_compiler = "@OPENMP_TEST_CXX_COMPILER@" config.test_compiler_features = @OPENMP_TEST_COMPILER_FEATURES@ config.test_filecheck = "@OPENMP_FILECHECK_EXECUTABLE@" +config.test_not = "@OPENMP_NOT_EXECUTABLE@" config.test_openmp_flags = "@OPENMP_TEST_OPENMP_FLAGS@" config.test_extra_flags = "@OPENMP_TEST_FLAGS@" config.libomp_obj_root = "@CMAKE_CURRENT_BINARY_DIR@" diff --git a/openmp/tools/archer/tests/lit.cfg b/openmp/tools/archer/tests/lit.cfg index 7ec88d3ca4e4..514976a9aaef 100644 --- a/openmp/tools/archer/tests/lit.cfg +++ b/openmp/tools/archer/tests/lit.cfg @@ -111,6 +111,7 @@ config.substitutions.append(("%suppression", "env TSAN_OPTIONS='ignore_noninstru config.substitutions.append(("%deflake", os.path.join(os.path.dirname(__file__), "deflake.bash"))) config.substitutions.append(("FileCheck", config.test_filecheck)) +config.substitutions.append((r"\bnot\b", config.test_not)) config.substitutions.append(("%sort-threads", "sort --numeric-sort --stable")) if config.operating_system == 'Windows': # No such environment variable on Windows. diff --git a/openmp/tools/archer/tests/lit.site.cfg.in b/openmp/tools/archer/tests/lit.site.cfg.in index cde10b2dd8dd..55edfde9738e 100644 --- a/openmp/tools/archer/tests/lit.site.cfg.in +++ b/openmp/tools/archer/tests/lit.site.cfg.in @@ -4,6 +4,7 @@ config.test_c_compiler = "@OPENMP_TEST_C_COMPILER@" config.test_cxx_compiler = "@OPENMP_TEST_CXX_COMPILER@" config.test_compiler_features = @OPENMP_TEST_COMPILER_FEATURES@ config.test_filecheck = "@OPENMP_FILECHECK_EXECUTABLE@" +config.test_not = "@OPENMP_NOT_EXECUTABLE@" config.test_openmp_flags = "@OPENMP_TEST_OPENMP_FLAGS@" config.test_extra_flags = "@OPENMP_TEST_FLAGS@" config.libomp_obj_root = "@CMAKE_CURRENT_BINARY_DIR@" -- GitLab From 5f6aa9680c19534a382cb652178e0ff6edbe78de Mon Sep 17 00:00:00 2001 From: "Joel E. Denny" Date: Tue, 21 Apr 2020 16:27:39 -0400 Subject: [PATCH 010/910] [OpenMP] target_data_begin: fail on device alloc fail Without this patch, target_data_begin continues after an illegal mapping or an out-of-memory error on the device. With this patch, it terminates the runtime with an error instead. The new test exercises only illegal mappings. I didn't think of a good way to exercise out-of-memory errors from the test suite. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D78170 --- openmp/libomptarget/src/omptarget.cpp | 1 + openmp/libomptarget/test/mapping/alloc_fail.c | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 openmp/libomptarget/test/mapping/alloc_fail.c diff --git a/openmp/libomptarget/src/omptarget.cpp b/openmp/libomptarget/src/omptarget.cpp index 3113bdc2a9d3..df7481a34805 100644 --- a/openmp/libomptarget/src/omptarget.cpp +++ b/openmp/libomptarget/src/omptarget.cpp @@ -286,6 +286,7 @@ int target_data_begin(DeviceTy &Device, int32_t arg_num, void **args_base, // NULL, so getOrAlloc() returning NULL is not an error. DP("Call to getOrAllocTgtPtr returned null pointer (device failure or " "illegal mapping).\n"); + return OFFLOAD_FAIL; } DP("There are %" PRId64 " bytes allocated at target address " DPxMOD " - is%s new\n", data_size, DPxPTR(TgtPtrBegin), diff --git a/openmp/libomptarget/test/mapping/alloc_fail.c b/openmp/libomptarget/test/mapping/alloc_fail.c new file mode 100644 index 000000000000..ca15a429f130 --- /dev/null +++ b/openmp/libomptarget/test/mapping/alloc_fail.c @@ -0,0 +1,25 @@ +// RUN: %libomptarget-compile-aarch64-unknown-linux-gnu +// RUN: %libomptarget-run-fail-aarch64-unknown-linux-gnu 2>&1 \ +// RUN: | %fcheck-aarch64-unknown-linux-gnu + +// RUN: %libomptarget-compile-powerpc64-ibm-linux-gnu +// RUN: %libomptarget-run-fail-powerpc64-ibm-linux-gnu 2>&1 \ +// RUN: | %fcheck-powerpc64-ibm-linux-gnu + +// RUN: %libomptarget-compile-powerpc64le-ibm-linux-gnu +// RUN: %libomptarget-run-fail-powerpc64le-ibm-linux-gnu 2>&1 \ +// RUN: | %fcheck-powerpc64le-ibm-linux-gnu + +// RUN: %libomptarget-compile-x86_64-pc-linux-gnu +// RUN: %libomptarget-run-fail-x86_64-pc-linux-gnu 2>&1 \ +// RUN: | %fcheck-x86_64-pc-linux-gnu + +// CHECK: Libomptarget fatal error 1: failure of target construct while offloading is mandatory + +int main() { + int arr[4] = {0, 1, 2, 3}; +#pragma omp target data map(alloc: arr[0:2]) +#pragma omp target data map(alloc: arr[1:2]) + ; + return 0; +} -- GitLab From 507d80fbd21ac5d4b67cb63d727c31e1cc89958e Mon Sep 17 00:00:00 2001 From: Amy Huang Date: Tue, 21 Apr 2020 14:14:32 -0700 Subject: [PATCH 011/910] Revert "Implement some NativeSession functions" along with some followup fixes. This reverts commits a6d8a055e92eb4853805d1ad1be0b1a6523524ef 4927ae085807731eb4052e0a682443fe9399b512 1e1f5eb7c978da3b062daaf3c32c459704e65a55 --- .../llvm/DebugInfo/PDB/Native/NativeSession.h | 9 -- .../DebugInfo/PDB/Native/NativeSession.cpp | 137 +----------------- llvm/lib/DebugInfo/PDB/PDB.cpp | 24 ++- llvm/unittests/DebugInfo/PDB/CMakeLists.txt | 1 - .../DebugInfo/PDB/Inputs/SimpleTest.cpp | 4 - .../DebugInfo/PDB/Inputs/SimpleTest.exe | Bin 7168 -> 0 bytes .../DebugInfo/PDB/Inputs/SimpleTest.pdb | Bin 94208 -> 0 bytes .../DebugInfo/PDB/NativeSessionTest.cpp | 93 ------------ 8 files changed, 18 insertions(+), 250 deletions(-) delete mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp delete mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.exe delete mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.pdb delete mode 100644 llvm/unittests/DebugInfo/PDB/NativeSessionTest.cpp diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h b/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h index 26b1992a03d7..ee7d8cdec93b 100644 --- a/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h +++ b/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h @@ -26,11 +26,6 @@ class PDBFile; class NativeExeSymbol; class NativeSession : public IPDBSession { - struct PdbSearchOptions { - StringRef ExePath; - // FIXME: Add other PDB search options (_NT_SYMBOL_PATH, symsrv) - }; - public: NativeSession(std::unique_ptr PdbFile, std::unique_ptr Allocator); @@ -38,11 +33,8 @@ public: static Error createFromPdb(std::unique_ptr MB, std::unique_ptr &Session); - static Error createFromPdbPath(StringRef PdbPath, - std::unique_ptr &Session); static Error createFromExe(StringRef Path, std::unique_ptr &Session); - static Expected searchForPdb(const PdbSearchOptions &Opts); uint64_t getLoadAddress() const override; bool setLoadAddress(uint64_t Address) override; @@ -117,7 +109,6 @@ private: SymbolCache Cache; SymIndexId ExeSymbol = 0; - uint64_t LoadAddress = 0; }; } // namespace pdb } // namespace llvm diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp index d12fec9c8329..b45a5881dcb5 100644 --- a/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp +++ b/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp @@ -12,7 +12,6 @@ #include "llvm/DebugInfo/CodeView/TypeIndex.h" #include "llvm/DebugInfo/PDB/IPDBEnumChildren.h" #include "llvm/DebugInfo/PDB/IPDBSourceFile.h" -#include "llvm/DebugInfo/PDB/Native/DbiStream.h" #include "llvm/DebugInfo/PDB/Native/NativeCompilandSymbol.h" #include "llvm/DebugInfo/PDB/Native/NativeEnumInjectedSources.h" #include "llvm/DebugInfo/PDB/Native/NativeEnumTypes.h" @@ -26,14 +25,11 @@ #include "llvm/DebugInfo/PDB/PDBSymbolCompiland.h" #include "llvm/DebugInfo/PDB/PDBSymbolExe.h" #include "llvm/DebugInfo/PDB/PDBSymbolTypeEnum.h" -#include "llvm/Object/COFF.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/BinaryByteStream.h" #include "llvm/Support/Error.h" #include "llvm/Support/ErrorOr.h" -#include "llvm/Support/FileSystem.h" #include "llvm/Support/MemoryBuffer.h" -#include "llvm/Support/Path.h" #include #include @@ -79,115 +75,14 @@ Error NativeSession::createFromPdb(std::unique_ptr Buffer, return Error::success(); } -static Expected> -loadPdbFile(StringRef PdbPath, std::unique_ptr &Allocator) { - ErrorOr> ErrorOrBuffer = - MemoryBuffer::getFile(PdbPath, /*FileSize=*/-1, - /*RequiresNullTerminator=*/false); - if (!ErrorOrBuffer) - return make_error(ErrorOrBuffer.getError()); - std::unique_ptr Buffer = std::move(*ErrorOrBuffer); - - PdbPath = Buffer->getBufferIdentifier(); - file_magic Magic; - auto EC = identify_magic(PdbPath, Magic); - if (EC || Magic != file_magic::pdb) - return make_error(EC); - - auto Stream = std::make_unique(std::move(Buffer), - llvm::support::little); - - auto File = std::make_unique(PdbPath, std::move(Stream), *Allocator); - if (auto EC = File->parseFileHeaders()) - return std::move(EC); - - if (auto EC = File->parseStreamData()) - return std::move(EC); - - return std::move(File); -} - -Error NativeSession::createFromPdbPath(StringRef PdbPath, - std::unique_ptr &Session) { - auto Allocator = std::make_unique(); - auto PdbFile = loadPdbFile(PdbPath, Allocator); - if (!PdbFile) - return PdbFile.takeError(); - - Session = std::make_unique(std::move(PdbFile.get()), - std::move(Allocator)); - return Error::success(); -} - -static Expected getPdbPathFromExe(StringRef ExePath) { - Expected> BinaryFile = - object::createBinary(ExePath); - if (!BinaryFile) - return BinaryFile.takeError(); - - const object::COFFObjectFile *ObjFile = - dyn_cast(BinaryFile->getBinary()); - if (!ObjFile) - return make_error(raw_error_code::invalid_format); - - StringRef PdbPath; - const llvm::codeview::DebugInfo *PdbInfo = nullptr; - if (auto EC = ObjFile->getDebugPDBInfo(PdbInfo, PdbPath)) - return make_error(EC); - - return std::string(PdbPath); -} - -Error NativeSession::createFromExe(StringRef ExePath, +Error NativeSession::createFromExe(StringRef Path, std::unique_ptr &Session) { - Expected PdbPath = getPdbPathFromExe(ExePath); - if (!PdbPath) - return PdbPath.takeError(); - - file_magic Magic; - auto EC = identify_magic(PdbPath.get(), Magic); - if (EC || Magic != file_magic::pdb) - return make_error(EC); - - auto Allocator = std::make_unique(); - auto File = loadPdbFile(PdbPath.get(), Allocator); - if (!File) - return File.takeError(); - - Session = std::make_unique(std::move(File.get()), - std::move(Allocator)); - - return Error::success(); + return make_error(raw_error_code::feature_unsupported); } -Expected -NativeSession::searchForPdb(const PdbSearchOptions &Opts) { - Expected PathOrErr = getPdbPathFromExe(Opts.ExePath); - if (!PathOrErr) - return PathOrErr.takeError(); - StringRef PdbName = sys::path::filename(PathOrErr.get()); +uint64_t NativeSession::getLoadAddress() const { return 0; } - // Check if pdb exists in the executable directory. - SmallString<128> PdbPath = StringRef(Opts.ExePath); - sys::path::remove_filename(PdbPath); - sys::path::append(PdbPath, PdbName); - - auto Allocator = std::make_unique(); - - if (auto File = loadPdbFile(PdbPath, Allocator)) - return std::string(PdbPath); - else - return File.takeError(); - - return make_error("PDB not found"); -} - -uint64_t NativeSession::getLoadAddress() const { return LoadAddress; } - -bool NativeSession::setLoadAddress(uint64_t Address) { - LoadAddress = Address; - return true; -} +bool NativeSession::setLoadAddress(uint64_t Address) { return false; } std::unique_ptr NativeSession::getGlobalScope() { return PDBSymbol::createAs(*this, getNativeGlobalScope()); @@ -200,30 +95,12 @@ NativeSession::getSymbolById(SymIndexId SymbolId) const { bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section, uint32_t &Offset) const { - uint32_t RVA = VA - getLoadAddress(); - return addressForRVA(RVA, Section, Offset); + return false; } -bool NativeSession::addressForRVA(uint32_t RVA, uint32_t &Section, +bool NativeSession::addressForRVA(uint32_t VA, uint32_t &Section, uint32_t &Offset) const { - auto Dbi = Pdb->getPDBDbiStream(); - if (!Dbi) - return false; - - Section = 0; - Offset = 0; - - if ((int32_t)RVA < 0) - return true; - - Offset = RVA; - for (; Section < Dbi->getSectionHeaders().size(); ++Section) { - auto &Sec = Dbi->getSectionHeaders()[Section]; - if (RVA < Sec.VirtualAddress) - return true; - Offset = RVA - Sec.VirtualAddress; - } - return true; + return false; } std::unique_ptr diff --git a/llvm/lib/DebugInfo/PDB/PDB.cpp b/llvm/lib/DebugInfo/PDB/PDB.cpp index a0d015c7839e..e7b968cb7bea 100644 --- a/llvm/lib/DebugInfo/PDB/PDB.cpp +++ b/llvm/lib/DebugInfo/PDB/PDB.cpp @@ -23,8 +23,15 @@ using namespace llvm::pdb; Error llvm::pdb::loadDataForPDB(PDB_ReaderType Type, StringRef Path, std::unique_ptr &Session) { // Create the correct concrete instance type based on the value of Type. - if (Type == PDB_ReaderType::Native) - return NativeSession::createFromPdbPath(Path, Session); + if (Type == PDB_ReaderType::Native) { + ErrorOr> ErrorOrBuffer = + MemoryBuffer::getFileOrSTDIN(Path, /*FileSize=*/-1, + /*RequiresNullTerminator=*/false); + if (!ErrorOrBuffer) + return errorCodeToError(ErrorOrBuffer.getError()); + + return NativeSession::createFromPdb(std::move(*ErrorOrBuffer), Session); + } #if LLVM_ENABLE_DIA_SDK return DIASession::createFromPdb(Path, Session); @@ -36,17 +43,8 @@ Error llvm::pdb::loadDataForPDB(PDB_ReaderType Type, StringRef Path, Error llvm::pdb::loadDataForEXE(PDB_ReaderType Type, StringRef Path, std::unique_ptr &Session) { // Create the correct concrete instance type based on the value of Type. - if (Type == PDB_ReaderType::Native) { - if (auto Err = NativeSession::createFromExe(Path, Session)) { - consumeError(std::move(Err)); - - Expected PdbPath = NativeSession::searchForPdb({Path}); - if (!PdbPath) - return PdbPath.takeError(); - return NativeSession::createFromPdbPath(PdbPath.get(), Session); - } - return Error::success(); - } + if (Type == PDB_ReaderType::Native) + return NativeSession::createFromExe(Path, Session); #if LLVM_ENABLE_DIA_SDK return DIASession::createFromExe(Path, Session); diff --git a/llvm/unittests/DebugInfo/PDB/CMakeLists.txt b/llvm/unittests/DebugInfo/PDB/CMakeLists.txt index c8c2659277a6..4edfd50c148d 100644 --- a/llvm/unittests/DebugInfo/PDB/CMakeLists.txt +++ b/llvm/unittests/DebugInfo/PDB/CMakeLists.txt @@ -6,7 +6,6 @@ set(LLVM_LINK_COMPONENTS add_llvm_unittest_with_input_files(DebugInfoPDBTests HashTableTest.cpp - NativeSessionTest.cpp NativeSymbolReuseTest.cpp StringTableBuilderTest.cpp PDBApiTest.cpp diff --git a/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp b/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp deleted file mode 100644 index 5cd4030802c6..000000000000 --- a/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp +++ /dev/null @@ -1,4 +0,0 @@ -// Compile with "cl /c /Zi SimpleTest.cpp" -// Link with "link SimpleTest.obj /debug /nodefaultlib /entry:main" - -int main() { return 0; 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-using namespace llvm::pdb; - -extern const char *TestMainArgv0; - -static std::string getExePath() { - SmallString<128> InputsDir = unittest::getInputFileDirectory(TestMainArgv0); - llvm::sys::path::append(InputsDir, "SimpleTest.exe"); - return std::string(InputsDir); -} - -TEST(NativeSessionTest, TestCreateFromExe) { - std::unique_ptr S; - Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); - ASSERT_THAT_ERROR(std::move(E), Succeeded()); -} - -TEST(NativeSessionTest, TestSetLoadAddress) { - std::unique_ptr S; - Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); - ASSERT_THAT_ERROR(std::move(E), Succeeded()); - - S->setLoadAddress(123); - EXPECT_EQ(S->getLoadAddress(), 123U); -} - -TEST(NativeSessionTest, TestAddressForVA) { - std::unique_ptr S; - Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); - ASSERT_THAT_ERROR(std::move(E), Succeeded()); - - uint64_t LoadAddr = S->getLoadAddress(); - uint32_t Section; - uint32_t Offset; - ASSERT_TRUE(S->addressForVA(LoadAddr + 5000, Section, Offset)); - EXPECT_EQ(1U, Section); - EXPECT_EQ(904U, Offset); - - ASSERT_TRUE(S->addressForVA(-1, Section, Offset)); - EXPECT_EQ(0U, Section); - EXPECT_EQ(0U, Offset); - - ASSERT_TRUE(S->addressForVA(4, Section, Offset)); - EXPECT_EQ(0U, Section); - EXPECT_EQ(4U, Offset); - - ASSERT_TRUE(S->addressForVA(LoadAddr + 100000, Section, Offset)); - EXPECT_EQ(3U, Section); - EXPECT_EQ(83616U, Offset); -} - -TEST(NativeSessionTest, TestAddressForRVA) { - std::unique_ptr S; - Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); - ASSERT_THAT_ERROR(std::move(E), Succeeded()); - - uint32_t Section; - uint32_t Offset; - ASSERT_TRUE(S->addressForVA(5000, Section, Offset)); - EXPECT_EQ(1U, Section); - EXPECT_EQ(904U, Offset); - - ASSERT_TRUE(S->addressForVA(-1, Section, Offset)); - EXPECT_EQ(0U, Section); - EXPECT_EQ(0U, Offset); - - ASSERT_TRUE(S->addressForVA(4, Section, Offset)); - EXPECT_EQ(0U, Section); - EXPECT_EQ(4U, Offset); - - ASSERT_TRUE(S->addressForVA(100000, Section, Offset)); - EXPECT_EQ(3U, Section); - EXPECT_EQ(83616U, Offset); -} -- GitLab From 73ea427818a6df066b5aa36555f3feb3c1269274 Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Tue, 21 Apr 2020 21:22:07 +0000 Subject: [PATCH 012/910] [gn build] Port 060efd24c7f --- llvm/utils/gn/secondary/lld/MachO/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/lld/MachO/BUILD.gn b/llvm/utils/gn/secondary/lld/MachO/BUILD.gn index 16a21037914d..f6e37a8243b7 100644 --- a/llvm/utils/gn/secondary/lld/MachO/BUILD.gn +++ b/llvm/utils/gn/secondary/lld/MachO/BUILD.gn @@ -26,6 +26,7 @@ static_library("MachO2") { "OutputSegment.cpp", "SymbolTable.cpp", "Symbols.cpp", + "SyntheticSections.cpp", "Target.cpp", "Writer.cpp", ] -- GitLab From 67c6b80569b0da004f47d3751cce203f014443c7 Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Tue, 21 Apr 2020 21:22:08 +0000 Subject: [PATCH 013/910] [gn build] Port 352fef3f11f --- llvm/utils/gn/secondary/llvm/lib/Transforms/InstCombine/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Transforms/InstCombine/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Transforms/InstCombine/BUILD.gn index d68a00712720..6e929a912d91 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Transforms/InstCombine/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Transforms/InstCombine/BUILD.gn @@ -23,6 +23,7 @@ static_library("InstCombine") { "InstCombineCompares.cpp", "InstCombineLoadStoreAlloca.cpp", "InstCombineMulDivRem.cpp", + "InstCombineNegator.cpp", "InstCombinePHI.cpp", "InstCombineSelect.cpp", "InstCombineShifts.cpp", -- GitLab From 400b6f2bc53915b61f1ed9408819fa898e4c8941 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Tue, 21 Apr 2020 14:34:18 -0700 Subject: [PATCH 014/910] [lldb/Test] Add skipIfReproducer for tests that are not expected to work Some tests are not expected to work with reproducers, for example tests that completely circumvent the reproducers (i.e. using the side_effects Python module) or that rely on changes to the file system. --- .../breakpoint/breakpoint_command/TestBreakpointCommand.py | 2 ++ .../API/functionalities/inferior-changed/TestInferiorChanged.py | 1 + .../test/API/lang/objc/modules-update/TestClangModulesUpdate.py | 1 + 3 files changed, 4 insertions(+) diff --git a/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py b/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py index 77db8f745d7e..9a66df9a798b 100644 --- a/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py +++ b/lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py @@ -17,12 +17,14 @@ class BreakpointCommandTestCase(TestBase): mydir = TestBase.compute_mydir(__file__) @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr24528") + @skipIfReproducer # side_effect bypasses reproducer def not_test_breakpoint_command_sequence(self): """Test a sequence of breakpoint command add, list, and delete.""" self.build() self.breakpoint_command_sequence() @skipIf(oslist=["windows"], bugnumber="llvm.org/pr44431") + @skipIfReproducer # side_effect bypasses reproducer def test_script_parameters(self): """Test a sequence of breakpoint command add, list, and delete.""" self.build() diff --git a/lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py b/lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py index 95cdfb5591fa..16ab1aaeb593 100644 --- a/lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py +++ b/lldb/test/API/functionalities/inferior-changed/TestInferiorChanged.py @@ -16,6 +16,7 @@ class ChangedInferiorTestCase(TestBase): @skipIf(hostoslist=["windows"]) @no_debug_info_test + @skipIfReproducer # VFS is a snapshot. def test_inferior_crashing(self): """Test lldb reloads the inferior after it was changed during the session.""" self.build() diff --git a/lldb/test/API/lang/objc/modules-update/TestClangModulesUpdate.py b/lldb/test/API/lang/objc/modules-update/TestClangModulesUpdate.py index e36a2278daac..13820b56688b 100644 --- a/lldb/test/API/lang/objc/modules-update/TestClangModulesUpdate.py +++ b/lldb/test/API/lang/objc/modules-update/TestClangModulesUpdate.py @@ -14,6 +14,7 @@ class TestClangModuleUpdate(TestBase): @skipUnlessDarwin @skipIf(debug_info=no_match(["gmodules"])) + @skipIfReproducer # VFS is a snapshot. def test_expr(self): with open(self.getBuildArtifact("module.modulemap"), "w") as f: f.write(""" -- GitLab From 1e566f6b47fb77812d99c93e0a1b8613d288058c Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Tue, 21 Apr 2020 14:36:31 -0700 Subject: [PATCH 015/910] [lldb/Test] Add skipIfReproducer for tests that diverge during replay Add the skipIfReproducer decorator to the remaining tests that fail to replay because the GDB remote packets diverge during replay. This is *not* expected and should be fixed, but figuring out exactly what caused the divergence has proven pretty difficult to track down. I've marked these tests as skipped for now so we can get clean results and detect new regressions. I have no evidence to believe that these failures have the same root cause, so I've not assigned them a PR. --- lldb/test/API/commands/command/script/TestCommandScript.py | 1 + lldb/test/API/commands/expression/issue_11588/Test11588.py | 1 + .../API/commands/process/attach-resume/TestAttachResume.py | 1 + lldb/test/API/commands/process/attach/TestProcessAttach.py | 1 + .../breakpoint/scripted_bkpt/TestScriptedResolver.py | 1 + .../conditional_break/TestConditionalBreak.py | 1 + .../functionalities/gdb_remote_client/TestGDBRemoteClient.py | 1 + lldb/test/API/functionalities/signal/TestSendSignal.py | 1 + .../API/functionalities/step_scripted/TestStepScripted.py | 5 +++++ lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py | 1 + lldb/test/API/lang/objc/modules/TestObjCModules.py | 1 + lldb/test/API/lang/objc/print-obj/TestPrintObj.py | 1 + lldb/test/API/python_api/hello_world/TestHelloWorld.py | 1 + 13 files changed, 17 insertions(+) diff --git a/lldb/test/API/commands/command/script/TestCommandScript.py b/lldb/test/API/commands/command/script/TestCommandScript.py index b103298f24e1..6663c3641452 100644 --- a/lldb/test/API/commands/command/script/TestCommandScript.py +++ b/lldb/test/API/commands/command/script/TestCommandScript.py @@ -14,6 +14,7 @@ class CmdPythonTestCase(TestBase): mydir = TestBase.compute_mydir(__file__) NO_DEBUG_INFO_TESTCASE = True + @skipIfReproducer # Unexpected packet during replay def test(self): self.build() self.pycmd_tests() diff --git a/lldb/test/API/commands/expression/issue_11588/Test11588.py b/lldb/test/API/commands/expression/issue_11588/Test11588.py index 626eef6f5511..8ed7797d5fff 100644 --- a/lldb/test/API/commands/expression/issue_11588/Test11588.py +++ b/lldb/test/API/commands/expression/issue_11588/Test11588.py @@ -17,6 +17,7 @@ class Issue11581TestCase(TestBase): mydir = TestBase.compute_mydir(__file__) @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr24778") + @skipIfReproducer # Unexpected packet during replay def test_11581_commands(self): # This is the function to remove the custom commands in order to have a # clean slate for the next test case. diff --git a/lldb/test/API/commands/process/attach-resume/TestAttachResume.py b/lldb/test/API/commands/process/attach-resume/TestAttachResume.py index b559f44a6b3d..ebb4345aca91 100644 --- a/lldb/test/API/commands/process/attach-resume/TestAttachResume.py +++ b/lldb/test/API/commands/process/attach-resume/TestAttachResume.py @@ -21,6 +21,7 @@ class AttachResumeTestCase(TestBase): @expectedFailureAll(oslist=['freebsd'], bugnumber='llvm.org/pr19310') @expectedFailureNetBSD @skipIfWindows # llvm.org/pr24778, llvm.org/pr21753 + @skipIfReproducer # Unexpected packet during replay def test_attach_continue_interrupt_detach(self): """Test attach/continue/interrupt/detach""" self.build() diff --git a/lldb/test/API/commands/process/attach/TestProcessAttach.py b/lldb/test/API/commands/process/attach/TestProcessAttach.py index b85d57133507..792a8cee61f9 100644 --- a/lldb/test/API/commands/process/attach/TestProcessAttach.py +++ b/lldb/test/API/commands/process/attach/TestProcessAttach.py @@ -39,6 +39,7 @@ class ProcessAttachTestCase(TestBase): self.assertTrue(process, PROCESS_IS_VALID) @expectedFailureNetBSD + @skipIfReproducer # Unexpected packet during replay def test_attach_to_process_from_different_dir_by_id(self): """Test attach by process id""" newdir = self.getBuildArtifact("newdir") diff --git a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py index 02c0aab9149e..ce1328d86d79 100644 --- a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py +++ b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py @@ -45,6 +45,7 @@ class TestScriptedResolver(TestBase): self.build() self.do_test_copy_from_dummy_target() + @skipIfReproducer # Unexpected packet during replay def make_target_and_import(self): target = self.make_target() self.import_resolver_script() diff --git a/lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py b/lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py index cc48a6397242..c1184d22cf15 100644 --- a/lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py +++ b/lldb/test/API/functionalities/conditional_break/TestConditionalBreak.py @@ -26,6 +26,7 @@ class ConditionalBreakTestCase(TestBase): self.build() self.do_conditional_break() + @skipIfReproducer # Unexpected packet during replay def test_with_command(self): """Simulate a user using lldb commands to break on c() if called from a().""" self.build() diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py index 5f21e3b2adc4..0fe3d6290f42 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py @@ -17,6 +17,7 @@ class TestGDBRemoteClient(GDBRemoteTestBase): process = self.connect(target) self.assertPacketLogContains(["qProcessInfo", "qfThreadInfo"]) + @skipIfReproducer # Unexpected packet during replay def test_attach_fail(self): error_msg = "mock-error-msg" diff --git a/lldb/test/API/functionalities/signal/TestSendSignal.py b/lldb/test/API/functionalities/signal/TestSendSignal.py index 64abfd23629d..84c41d7def64 100644 --- a/lldb/test/API/functionalities/signal/TestSendSignal.py +++ b/lldb/test/API/functionalities/signal/TestSendSignal.py @@ -23,6 +23,7 @@ class SendSignalTestCase(TestBase): bugnumber="llvm.org/pr23318: does not report running state") @expectedFailureNetBSD(bugnumber='llvm.org/pr43959') @skipIfWindows # Windows does not support signals + @skipIfReproducer # Unexpected packet during replay def test_with_run_command(self): """Test that lldb command 'process signal SIGUSR1' sends a signal to the inferior process.""" self.build() diff --git a/lldb/test/API/functionalities/step_scripted/TestStepScripted.py b/lldb/test/API/functionalities/step_scripted/TestStepScripted.py index eb1b58225806..9cc63f46e806 100644 --- a/lldb/test/API/functionalities/step_scripted/TestStepScripted.py +++ b/lldb/test/API/functionalities/step_scripted/TestStepScripted.py @@ -4,6 +4,7 @@ Tests stepping with scripted thread plans. import lldb import lldbsuite.test.lldbutil as lldbutil +from lldbsuite.test.decorators import * from lldbsuite.test.lldbtest import * class StepScriptedTestCase(TestBase): @@ -17,12 +18,14 @@ class StepScriptedTestCase(TestBase): self.main_source_file = lldb.SBFileSpec("main.c") self.runCmd("command script import Steps.py") + @skipIfReproducer # Unexpected packet during replay def test_standard_step_out(self): """Tests stepping with the scripted thread plan laying over a standard thread plan for stepping out.""" self.build() self.step_out_with_scripted_plan("Steps.StepOut") + @skipIfReproducer # Unexpected packet during replay def test_scripted_step_out(self): """Tests stepping with the scripted thread plan laying over an another scripted thread plan for stepping out.""" @@ -62,10 +65,12 @@ class StepScriptedTestCase(TestBase): # Make sure we didn't let the process run: self.assertEqual(stop_id, process.GetStopID(), "Process didn't run") + @skipIfReproducer # Unexpected packet during replay def test_checking_variable(self): """Test that we can call SBValue API's from a scripted thread plan - using SBAPI's to step""" self.do_test_checking_variable(False) + @skipIfReproducer # Unexpected packet during replay def test_checking_variable_cli(self): """Test that we can call SBValue API's from a scripted thread plan - using cli to step""" self.do_test_checking_variable(True) diff --git a/lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py b/lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py index f5cb75b4a6dc..7ddaf63f3450 100644 --- a/lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py +++ b/lldb/test/API/lang/objc/foundation/TestRuntimeTypes.py @@ -19,6 +19,7 @@ class RuntimeTypesTestCase(TestBase): oslist=["macosx"], debug_info="gmodules", bugnumber="llvm.org/pr27862") + @skipIfReproducer # Unexpected packet during replay def test_break(self): """Test setting objc breakpoints using '_regexp-break' and 'breakpoint set'.""" if self.getArchitecture() != 'x86_64': diff --git a/lldb/test/API/lang/objc/modules/TestObjCModules.py b/lldb/test/API/lang/objc/modules/TestObjCModules.py index 695eac9ee856..30535409a30f 100644 --- a/lldb/test/API/lang/objc/modules/TestObjCModules.py +++ b/lldb/test/API/lang/objc/modules/TestObjCModules.py @@ -22,6 +22,7 @@ class ObjCModulesTestCase(TestBase): @skipUnlessDarwin @skipIf(macos_version=["<", "10.12"]) + @skipIfReproducer # Unexpected packet during replay def test_expr(self): self.build() exe = self.getBuildArtifact("a.out") diff --git a/lldb/test/API/lang/objc/print-obj/TestPrintObj.py b/lldb/test/API/lang/objc/print-obj/TestPrintObj.py index 9b3ec33db4e7..b908079eefcd 100644 --- a/lldb/test/API/lang/objc/print-obj/TestPrintObj.py +++ b/lldb/test/API/lang/objc/print-obj/TestPrintObj.py @@ -24,6 +24,7 @@ class PrintObjTestCase(TestBase): # Find the line numbers to break at. self.line = line_number(self.source, '// Set a breakpoint here.') + @skipIfReproducer # Unexpected packet during replay def test_print_obj(self): """ Test "print object" where another thread blocks the print object from making progress. diff --git a/lldb/test/API/python_api/hello_world/TestHelloWorld.py b/lldb/test/API/python_api/hello_world/TestHelloWorld.py index fc6ef4882a06..5b189b36d7f9 100644 --- a/lldb/test/API/python_api/hello_world/TestHelloWorld.py +++ b/lldb/test/API/python_api/hello_world/TestHelloWorld.py @@ -109,6 +109,7 @@ class HelloWorldTestCase(TestBase): @skipIfiOSSimulator @skipIfAsan # FIXME: Hangs indefinitely. @expectedFailureNetBSD + @skipIfReproducer # Unexpected packet during replay def test_with_attach_to_process_with_name_api(self): """Create target, spawn a process, and attach to it with process name.""" exe = '%s_%d'%(self.testMethodName, os.getpid()) -- GitLab From b707cf096dda9592a2ae1d874f4e760e36c6f1e5 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Tue, 21 Apr 2020 15:05:32 -0700 Subject: [PATCH 016/910] [lldb/Test] Add decorator to the right method --- .../breakpoint/scripted_bkpt/TestScriptedResolver.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py index ce1328d86d79..b08dfc78cea3 100644 --- a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py +++ b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/TestScriptedResolver.py @@ -16,6 +16,7 @@ class TestScriptedResolver(TestBase): NO_DEBUG_INFO_TESTCASE = True @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr24528") + @skipIfReproducer # Unexpected packet during replay def test_scripted_resolver(self): """Use a scripted resolver to set a by symbol name breakpoint""" self.build() @@ -45,7 +46,6 @@ class TestScriptedResolver(TestBase): self.build() self.do_test_copy_from_dummy_target() - @skipIfReproducer # Unexpected packet during replay def make_target_and_import(self): target = self.make_target() self.import_resolver_script() -- GitLab From c860262bd20d37c23053f14a82e8e4aa8827cc10 Mon Sep 17 00:00:00 2001 From: Dan Liew Date: Tue, 21 Apr 2020 15:13:15 -0700 Subject: [PATCH 017/910] Disable a Darwin test under LSan. * Changing source lines seems to cause us to hit rdar://problem/62132428. * Even if I workaround the above issue sometimes the source line in the dylib reported by atos is off by one. It's simpler to just disable the test for now. rdar://problem/61793759 --- .../Darwin/print-stack-trace-in-code-loaded-after-fork.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler-rt/test/sanitizer_common/TestCases/Darwin/print-stack-trace-in-code-loaded-after-fork.cpp b/compiler-rt/test/sanitizer_common/TestCases/Darwin/print-stack-trace-in-code-loaded-after-fork.cpp index db4cdf8f9b6d..ec8155365496 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Darwin/print-stack-trace-in-code-loaded-after-fork.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/Darwin/print-stack-trace-in-code-loaded-after-fork.cpp @@ -3,6 +3,8 @@ // RUN: %env_tool_opts=verbosity=3 %run %t_loader %t_shared_lib.dylib > %t_loader_output.txt 2>&1 // RUN: FileCheck -input-file=%t_loader_output.txt %s // RUN: FileCheck -check-prefix=CHECK-STACKTRACE -input-file=%t_loader_output.txt %s +// rdar://problem/61793759 and rdar://problem/62126022. +// UNSUPPORTED: lsan #include -- GitLab From 01d2a01e79d3d83f18cf3e54c2bf55bba523b77a Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 21 Apr 2020 14:44:03 -0700 Subject: [PATCH 018/910] [ELF] Fix a null pointer dereference when relocating a Local-Exec TLS relocation for a lazy symbol If there is no SHF_TLS section, there will be no PT_TLS and Out::tlsPhdr may be a nullptr. If the symbol referenced by an R_TLS is lazy, we should treat the symbol as undefined. Also reorganize tls-in-archive.s and tls-weak-undef.s . They do not test what they intended to test. --- lld/ELF/InputSection.cpp | 2 +- lld/test/ELF/Inputs/tls-in-archive.s | 3 --- lld/test/ELF/tls-in-archive.s | 12 ------------ lld/test/ELF/tls-le-weak-undef.s | 18 ++++++++++++++++++ lld/test/ELF/tls-weak-undef.s | 17 ----------------- lld/test/ELF/x86-64-tls-le-undef.s | 5 +---- 6 files changed, 20 insertions(+), 37 deletions(-) delete mode 100644 lld/test/ELF/Inputs/tls-in-archive.s delete mode 100644 lld/test/ELF/tls-in-archive.s create mode 100644 lld/test/ELF/tls-le-weak-undef.s delete mode 100644 lld/test/ELF/tls-weak-undef.s diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index e150cb8f118d..b9b6fef9dc48 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -807,7 +807,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, // --noinhibit-exec, even a non-weak undefined reference may reach here. // Just return A, which matches R_ABS, and the behavior of some dynamic // loaders. - if (sym.isUndefined()) + if (sym.isUndefined() || sym.isLazy()) return a; return getTlsTpOffset(sym) + a; case R_RELAX_TLS_GD_TO_LE_NEG: diff --git a/lld/test/ELF/Inputs/tls-in-archive.s b/lld/test/ELF/Inputs/tls-in-archive.s deleted file mode 100644 index 0474a417659e..000000000000 --- a/lld/test/ELF/Inputs/tls-in-archive.s +++ /dev/null @@ -1,3 +0,0 @@ - .type foo, @tls_object - .globl foo -foo: diff --git a/lld/test/ELF/tls-in-archive.s b/lld/test/ELF/tls-in-archive.s deleted file mode 100644 index 5a8791dd2b3c..000000000000 --- a/lld/test/ELF/tls-in-archive.s +++ /dev/null @@ -1,12 +0,0 @@ -// REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/tls-in-archive.s -o %t1.o -// RUN: rm -f %t.a -// RUN: llvm-ar cru %t.a %t1.o -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t2.o -// RUN: ld.lld %t2.o %t.a -o /dev/null - - .globl _start -_start: - movq foo@gottpoff(%rip), %rax - .section .tbss,"awT",@nobits - .weak foo diff --git a/lld/test/ELF/tls-le-weak-undef.s b/lld/test/ELF/tls-le-weak-undef.s new file mode 100644 index 000000000000..fefda9da9816 --- /dev/null +++ b/lld/test/ELF/tls-le-weak-undef.s @@ -0,0 +1,18 @@ +# REQUIRES: x86 +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +# RUN: echo '.tbss; .globl tls; tls:' | llvm-mc -filetype=obj -triple=x86_64 - -o %tdef.o +# RUN: ld.lld %t.o -o - | llvm-objdump -d - | FileCheck %s + +## A weak symbol does not fetch a lazy definition. +# RUN: ld.lld %t.o --start-lib %tdef.o --end-lib -o - | llvm-objdump -d - | FileCheck %s + +## Undefined TLS symbols arbitrarily resolve to 0. +# CHECK: leaq 16(%rax), %rdx + +# RUN: ld.lld -shared %tdef.o -o %tdef.so +# RUN: not ld.lld %t.o %tdef.so -o /dev/null 2>&1 | FileCheck --check-prefix=COPYRELOC %s + +# COPYRELOC: symbol 'tls' has no type + +.weak tls +leaq tls@tpoff+16(%rax), %rdx diff --git a/lld/test/ELF/tls-weak-undef.s b/lld/test/ELF/tls-weak-undef.s deleted file mode 100644 index 1023aebbc258..000000000000 --- a/lld/test/ELF/tls-weak-undef.s +++ /dev/null @@ -1,17 +0,0 @@ -// REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: ld.lld %t.o -o %t --gc-sections - -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux \ -// RUN: %p/Inputs/tls-in-archive.s -o %t1.o -// RUN: rm -f %t.a -// RUN: llvm-ar cru %t.a %t1.o -// RUN: ld.lld %t.o %t.a -o %t - -// Check that lld doesn't crash because we don't reference -// the TLS phdr when it's not created. - .globl _start -_start: - movq foo@gottpoff(%rip), %rax - .section .tbss,"awT",@nobits - .weak foo diff --git a/lld/test/ELF/x86-64-tls-le-undef.s b/lld/test/ELF/x86-64-tls-le-undef.s index 8feb267c0915..4c8e1c59bd02 100644 --- a/lld/test/ELF/x86-64-tls-le-undef.s +++ b/lld/test/ELF/x86-64-tls-le-undef.s @@ -6,10 +6,7 @@ ## Undefined TLS symbols resolve to 0. ## In --noinhibit-exec mode, a non-weak undefined symbol is not an error. -# CHECK: leaq 16(%rax), %rdx -# CHECK-NEXT: leaq 32(%rax), %rdx +# CHECK: leaq 32(%rax), %rdx -.weak weak movq %fs:0, %rax -leaq weak@tpoff+16(%rax), %rdx leaq global@tpoff+32(%rax), %rdx -- GitLab From d892eec710caae84099f38fdb89d32ca15a23c1a Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Tue, 21 Apr 2020 15:30:54 -0700 Subject: [PATCH 019/910] Reapply: Make header inclusion order from umbrella dirs deterministic Sort the headers by name before adding the includes in collectModuleHeaderIncludes. This makes the include order for building umbrellas deterministic across different filesystems and also guarantees that the ASTWriter always dump top headers in the same order. There's currently no good way to test for this behavior. This was first introduced in r289478 and reverted few times because of ASANifed test failures on open source bots (both from LLVM and Swift). Finally reproduced the problem in a Linux machine and use std::sort as a fix, since we are not dealing with POD-like types. rdar://problem/28116411 --- clang/lib/Frontend/FrontendAction.cpp | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/clang/lib/Frontend/FrontendAction.cpp b/clang/lib/Frontend/FrontendAction.cpp index 6168057d115d..dc361b2fdd24 100644 --- a/clang/lib/Frontend/FrontendAction.cpp +++ b/clang/lib/Frontend/FrontendAction.cpp @@ -364,6 +364,7 @@ static std::error_code collectModuleHeaderIncludes( llvm::sys::path::native(UmbrellaDir.Entry->getName(), DirNative); llvm::vfs::FileSystem &FS = FileMgr.getVirtualFileSystem(); + SmallVector, 8> Headers; for (llvm::vfs::recursive_directory_iterator Dir(FS, DirNative, EC), End; Dir != End && !EC; Dir.increment(EC)) { // Check whether this entry has an extension typically associated with @@ -394,13 +395,25 @@ static std::error_code collectModuleHeaderIncludes( ++It) llvm::sys::path::append(RelativeHeader, *It); - // Include this header as part of the umbrella directory. - Module->addTopHeader(*Header); - addHeaderInclude(RelativeHeader, Includes, LangOpts, Module->IsExternC); + std::string RelName = RelativeHeader.c_str(); + Headers.push_back(std::make_pair(RelName, *Header)); } if (EC) return EC; + + // Sort header paths and make the header inclusion order deterministic + // across different OSs and filesystems. + llvm::sort(Headers.begin(), Headers.end(), []( + const std::pair &LHS, + const std::pair &RHS) { + return LHS.first < RHS.first; + }); + for (auto &H : Headers) { + // Include this header as part of the umbrella directory. + Module->addTopHeader(H.second); + addHeaderInclude(H.first, Includes, LangOpts, Module->IsExternC); + } } // Recurse into submodules. -- GitLab From 9ee02aef62870850c957354def8cff9644b4e6c9 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Tue, 21 Apr 2020 13:13:23 -0700 Subject: [PATCH 020/910] [llvm][NFC][CallSite] Remove CallSite from FunctionAttrs Reviewers: dblaikie, craig.topper Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78584 --- llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 81 +++++++++++------------ 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp index 6b1107545324..0701dbc50958 100644 --- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp +++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp @@ -33,7 +33,6 @@ #include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" @@ -160,8 +159,7 @@ static MemoryAccessKind checkFunctionMemoryAccess(Function &F, bool ThisBody, // Check whether all pointer arguments point to local memory, and // ignore calls that only access local memory. - for (CallSite::arg_iterator CI = Call->arg_begin(), CE = Call->arg_end(); - CI != CE; ++CI) { + for (auto CI = Call->arg_begin(), CE = Call->arg_end(); CI != CE; ++CI) { Value *Arg = *CI; if (!Arg->getType()->isPtrOrPtrVectorTy()) continue; @@ -362,13 +360,13 @@ struct ArgumentUsesTracker : public CaptureTracker { void tooManyUses() override { Captured = true; } bool captured(const Use *U) override { - CallSite CS(U->getUser()); - if (!CS.getInstruction()) { + CallBase *CB = dyn_cast(U->getUser()); + if (!CB) { Captured = true; return true; } - Function *F = CS.getCalledFunction(); + Function *F = CB->getCalledFunction(); if (!F || !F->hasExactDefinition() || !SCCNodes.count(F)) { Captured = true; return true; @@ -379,14 +377,14 @@ struct ArgumentUsesTracker : public CaptureTracker { // these. unsigned UseIndex = - std::distance(const_cast(CS.arg_begin()), U); + std::distance(const_cast(CB->arg_begin()), U); - assert(UseIndex < CS.data_operands_size() && + assert(UseIndex < CB->data_operands_size() && "Indirect function calls should have been filtered above!"); - if (UseIndex >= CS.getNumArgOperands()) { + if (UseIndex >= CB->getNumArgOperands()) { // Data operand, but not a argument operand -- must be a bundle operand - assert(CS.hasOperandBundles() && "Must be!"); + assert(CB->hasOperandBundles() && "Must be!"); // CaptureTracking told us that we're being captured by an operand bundle // use. In this case it does not matter if the callee is within our SCC @@ -490,15 +488,15 @@ determinePointerReadAttrs(Argument *A, Worklist.push_back(&UU); }; - CallSite CS(I); - if (CS.doesNotAccessMemory()) { + CallBase &CB = cast(*I); + if (CB.doesNotAccessMemory()) { AddUsersToWorklistIfCapturing(); continue; } - Function *F = CS.getCalledFunction(); + Function *F = CB.getCalledFunction(); if (!F) { - if (CS.onlyReadsMemory()) { + if (CB.onlyReadsMemory()) { IsRead = true; AddUsersToWorklistIfCapturing(); continue; @@ -510,23 +508,23 @@ determinePointerReadAttrs(Argument *A, // operands. This means there is no need to adjust UseIndex to account // for these. - unsigned UseIndex = std::distance(CS.arg_begin(), U); + unsigned UseIndex = std::distance(CB.arg_begin(), U); // U cannot be the callee operand use: since we're exploring the // transitive uses of an Argument, having such a use be a callee would - // imply the CallSite is an indirect call or invoke; and we'd take the + // imply the call site is an indirect call or invoke; and we'd take the // early exit above. - assert(UseIndex < CS.data_operands_size() && + assert(UseIndex < CB.data_operands_size() && "Data operand use expected!"); - bool IsOperandBundleUse = UseIndex >= CS.getNumArgOperands(); + bool IsOperandBundleUse = UseIndex >= CB.getNumArgOperands(); if (UseIndex >= F->arg_size() && !IsOperandBundleUse) { assert(F->isVarArg() && "More params than args in non-varargs call"); return Attribute::None; } - Captures &= !CS.doesNotCapture(UseIndex); + Captures &= !CB.doesNotCapture(UseIndex); // Since the optimizer (by design) cannot see the data flow corresponding // to a operand bundle use, these cannot participate in the optimistic SCC @@ -535,12 +533,12 @@ determinePointerReadAttrs(Argument *A, if (IsOperandBundleUse || !SCCNodes.count(&*std::next(F->arg_begin(), UseIndex))) { - // The accessors used on CallSite here do the right thing for calls and + // The accessors used on call site here do the right thing for calls and // invokes with operand bundles. - if (!CS.onlyReadsMemory() && !CS.onlyReadsMemory(UseIndex)) + if (!CB.onlyReadsMemory() && !CB.onlyReadsMemory(UseIndex)) return Attribute::None; - if (!CS.doesNotAccessMemory(UseIndex)) + if (!CB.doesNotAccessMemory(UseIndex)) IsRead = true; } @@ -638,8 +636,8 @@ static bool addArgumentAttrsFromCallsites(Function &F) { // callsite. BasicBlock &Entry = F.getEntryBlock(); for (Instruction &I : Entry) { - if (auto CS = CallSite(&I)) { - if (auto *CalledFunc = CS.getCalledFunction()) { + if (auto *CB = dyn_cast(&I)) { + if (auto *CalledFunc = CB->getCalledFunction()) { for (auto &CSArg : CalledFunc->args()) { if (!CSArg.hasNonNullAttr()) continue; @@ -647,7 +645,7 @@ static bool addArgumentAttrsFromCallsites(Function &F) { // If the non-null callsite argument operand is an argument to 'F' // (the caller) and the call is guaranteed to execute, then the value // must be non-null throughout 'F'. - auto *FArg = dyn_cast(CS.getArgOperand(CSArg.getArgNo())); + auto *FArg = dyn_cast(CB->getArgOperand(CSArg.getArgNo())); if (FArg && !FArg->hasNonNullAttr()) { FArg->addAttr(Attribute::NonNull); Changed = true; @@ -904,10 +902,10 @@ static bool isFunctionMallocLike(Function *F, const SCCNodeSet &SCCNodes) { break; case Instruction::Call: case Instruction::Invoke: { - CallSite CS(RVI); - if (CS.hasRetAttr(Attribute::NoAlias)) + CallBase &CB = cast(*RVI); + if (CB.hasRetAttr(Attribute::NoAlias)) break; - if (CS.getCalledFunction() && SCCNodes.count(CS.getCalledFunction())) + if (CB.getCalledFunction() && SCCNodes.count(CB.getCalledFunction())) break; LLVM_FALLTHROUGH; } @@ -1013,8 +1011,8 @@ static bool isReturnNonNull(Function *F, const SCCNodeSet &SCCNodes, } case Instruction::Call: case Instruction::Invoke: { - CallSite CS(RVI); - Function *Callee = CS.getCalledFunction(); + CallBase &CB = cast(*RVI); + Function *Callee = CB.getCalledFunction(); // A call to a node within the SCC is assumed to return null until // proven otherwise if (Callee && SCCNodes.count(Callee)) { @@ -1223,10 +1221,11 @@ bool AttributeInferer::run(const SCCNodeSet &SCCNodes) { /// Helper for non-Convergent inference predicate InstrBreaksAttribute. static bool InstrBreaksNonConvergent(Instruction &I, const SCCNodeSet &SCCNodes) { - const CallSite CS(&I); + const CallBase *CB = dyn_cast(&I); // Breaks non-convergent assumption if CS is a convergent call to a function // not in the SCC. - return CS && CS.isConvergent() && SCCNodes.count(CS.getCalledFunction()) == 0; + return CB && CB->isConvergent() && + SCCNodes.count(CB->getCalledFunction()) == 0; } /// Helper for NoUnwind inference predicate InstrBreaksAttribute. @@ -1247,11 +1246,11 @@ static bool InstrBreaksNonThrowing(Instruction &I, const SCCNodeSet &SCCNodes) { /// Helper for NoFree inference predicate InstrBreaksAttribute. static bool InstrBreaksNoFree(Instruction &I, const SCCNodeSet &SCCNodes) { - CallSite CS(&I); - if (!CS) + CallBase *CB = dyn_cast(&I); + if (!CB) return false; - Function *Callee = CS.getCalledFunction(); + Function *Callee = CB->getCalledFunction(); if (!Callee) return true; @@ -1368,8 +1367,8 @@ static bool addNoRecurseAttrs(const SCCNodeSet &SCCNodes) { // marked norecurse, so any called from F to F will not be marked norecurse. for (auto &BB : *F) for (auto &I : BB.instructionsWithoutDebug()) - if (auto CS = CallSite(&I)) { - Function *Callee = CS.getCalledFunction(); + if (auto *CB = dyn_cast(&I)) { + Function *Callee = CB->getCalledFunction(); if (!Callee || Callee == F || !Callee->doesNotRecurse()) // Function calls a potentially recursive function. return false; @@ -1439,8 +1438,8 @@ PreservedAnalyses PostOrderFunctionAttrsPass::run(LazyCallGraph::SCC &C, // function. if (!HasUnknownCall) for (Instruction &I : instructions(F)) - if (auto CS = CallSite(&I)) - if (!CS.getCalledFunction()) { + if (auto *CB = dyn_cast(&I)) + if (!CB->getCalledFunction()) { HasUnknownCall = true; break; } @@ -1575,8 +1574,8 @@ static bool addNoRecurseAttrsTopDown(Function &F) { auto *I = dyn_cast(U); if (!I) return false; - CallSite CS(I); - if (!CS || !CS.getParent()->getParent()->doesNotRecurse()) + CallBase *CB = dyn_cast(I); + if (!CB || !CB->getParent()->getParent()->doesNotRecurse()) return false; } return setDoesNotRecurse(F); -- GitLab From 23609331472be22be3be134f6facd8f086c5ea49 Mon Sep 17 00:00:00 2001 From: Amy Huang Date: Tue, 21 Apr 2020 14:25:32 -0700 Subject: [PATCH 021/910] Reland "Implement some functions in NativeSession." with fixes so that the tests pass on Linux. Summary: This change implements readFromExe, and calculating VA and RVA, which are some of the functionalities that will be used for native PDB reading for llvm symbolizer. bug: https://bugs.llvm.org/show_bug.cgi?id=41795 --- .../llvm/DebugInfo/PDB/Native/NativeSession.h | 9 ++ .../DebugInfo/PDB/Native/NativeSession.cpp | 141 +++++++++++++++++- llvm/lib/DebugInfo/PDB/PDB.cpp | 24 +-- llvm/unittests/DebugInfo/PDB/CMakeLists.txt | 1 + .../DebugInfo/PDB/Inputs/SimpleTest.cpp | 4 + .../DebugInfo/PDB/Inputs/SimpleTest.exe | Bin 0 -> 7168 bytes .../DebugInfo/PDB/Inputs/SimpleTest.pdb | Bin 0 -> 94208 bytes .../DebugInfo/PDB/NativeSessionTest.cpp | 95 ++++++++++++ 8 files changed, 256 insertions(+), 18 deletions(-) create mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp create mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.exe create mode 100644 llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.pdb create mode 100644 llvm/unittests/DebugInfo/PDB/NativeSessionTest.cpp diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h b/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h index ee7d8cdec93b..26b1992a03d7 100644 --- a/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h +++ b/llvm/include/llvm/DebugInfo/PDB/Native/NativeSession.h @@ -26,6 +26,11 @@ class PDBFile; class NativeExeSymbol; class NativeSession : public IPDBSession { + struct PdbSearchOptions { + StringRef ExePath; + // FIXME: Add other PDB search options (_NT_SYMBOL_PATH, symsrv) + }; + public: NativeSession(std::unique_ptr PdbFile, std::unique_ptr Allocator); @@ -33,8 +38,11 @@ public: static Error createFromPdb(std::unique_ptr MB, std::unique_ptr &Session); + static Error createFromPdbPath(StringRef PdbPath, + std::unique_ptr &Session); static Error createFromExe(StringRef Path, std::unique_ptr &Session); + static Expected searchForPdb(const PdbSearchOptions &Opts); uint64_t getLoadAddress() const override; bool setLoadAddress(uint64_t Address) override; @@ -109,6 +117,7 @@ private: SymbolCache Cache; SymIndexId ExeSymbol = 0; + uint64_t LoadAddress = 0; }; } // namespace pdb } // namespace llvm diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp index b45a5881dcb5..9a9254f4302d 100644 --- a/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp +++ b/llvm/lib/DebugInfo/PDB/Native/NativeSession.cpp @@ -12,6 +12,7 @@ #include "llvm/DebugInfo/CodeView/TypeIndex.h" #include "llvm/DebugInfo/PDB/IPDBEnumChildren.h" #include "llvm/DebugInfo/PDB/IPDBSourceFile.h" +#include "llvm/DebugInfo/PDB/Native/DbiStream.h" #include "llvm/DebugInfo/PDB/Native/NativeCompilandSymbol.h" #include "llvm/DebugInfo/PDB/Native/NativeEnumInjectedSources.h" #include "llvm/DebugInfo/PDB/Native/NativeEnumTypes.h" @@ -25,11 +26,14 @@ #include "llvm/DebugInfo/PDB/PDBSymbolCompiland.h" #include "llvm/DebugInfo/PDB/PDBSymbolExe.h" #include "llvm/DebugInfo/PDB/PDBSymbolTypeEnum.h" +#include "llvm/Object/COFF.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/BinaryByteStream.h" #include "llvm/Support/Error.h" #include "llvm/Support/ErrorOr.h" +#include "llvm/Support/FileSystem.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Path.h" #include #include @@ -75,14 +79,119 @@ Error NativeSession::createFromPdb(std::unique_ptr Buffer, return Error::success(); } -Error NativeSession::createFromExe(StringRef Path, +static Expected> +loadPdbFile(StringRef PdbPath, std::unique_ptr &Allocator) { + ErrorOr> ErrorOrBuffer = + MemoryBuffer::getFile(PdbPath, /*FileSize=*/-1, + /*RequiresNullTerminator=*/false); + if (!ErrorOrBuffer) + return make_error(ErrorOrBuffer.getError()); + std::unique_ptr Buffer = std::move(*ErrorOrBuffer); + + PdbPath = Buffer->getBufferIdentifier(); + file_magic Magic; + auto EC = identify_magic(PdbPath, Magic); + if (EC || Magic != file_magic::pdb) + return make_error(EC); + + auto Stream = std::make_unique(std::move(Buffer), + llvm::support::little); + + auto File = std::make_unique(PdbPath, std::move(Stream), *Allocator); + if (auto EC = File->parseFileHeaders()) + return std::move(EC); + + if (auto EC = File->parseStreamData()) + return std::move(EC); + + return std::move(File); +} + +Error NativeSession::createFromPdbPath(StringRef PdbPath, + std::unique_ptr &Session) { + auto Allocator = std::make_unique(); + auto PdbFile = loadPdbFile(PdbPath, Allocator); + if (!PdbFile) + return PdbFile.takeError(); + + Session = std::make_unique(std::move(PdbFile.get()), + std::move(Allocator)); + return Error::success(); +} + +static Expected getPdbPathFromExe(StringRef ExePath) { + Expected> BinaryFile = + object::createBinary(ExePath); + if (!BinaryFile) + return BinaryFile.takeError(); + + const object::COFFObjectFile *ObjFile = + dyn_cast(BinaryFile->getBinary()); + if (!ObjFile) + return make_error(raw_error_code::invalid_format); + + StringRef PdbPath; + const llvm::codeview::DebugInfo *PdbInfo = nullptr; + if (auto EC = ObjFile->getDebugPDBInfo(PdbInfo, PdbPath)) + return make_error(EC); + + return std::string(PdbPath); +} + +Error NativeSession::createFromExe(StringRef ExePath, std::unique_ptr &Session) { - return make_error(raw_error_code::feature_unsupported); + Expected PdbPath = getPdbPathFromExe(ExePath); + if (!PdbPath) + return PdbPath.takeError(); + + file_magic Magic; + auto EC = identify_magic(PdbPath.get(), Magic); + if (EC || Magic != file_magic::pdb) + return make_error(EC); + + auto Allocator = std::make_unique(); + auto File = loadPdbFile(PdbPath.get(), Allocator); + if (!File) + return File.takeError(); + + Session = std::make_unique(std::move(File.get()), + std::move(Allocator)); + + return Error::success(); } -uint64_t NativeSession::getLoadAddress() const { return 0; } +Expected +NativeSession::searchForPdb(const PdbSearchOptions &Opts) { + Expected PathOrErr = getPdbPathFromExe(Opts.ExePath); + if (!PathOrErr) + return PathOrErr.takeError(); + StringRef PathFromExe = PathOrErr.get(); + sys::path::Style Style = PathFromExe.startswith("/") + ? sys::path::Style::posix + : sys::path::Style::windows; + StringRef PdbName = sys::path::filename(PathFromExe, Style); + + // Check if pdb exists in the executable directory. + SmallString<128> PdbPath = StringRef(Opts.ExePath); + sys::path::remove_filename(PdbPath); + sys::path::append(PdbPath, PdbName); -bool NativeSession::setLoadAddress(uint64_t Address) { return false; } + auto Allocator = std::make_unique(); + + if (auto File = loadPdbFile(PdbPath, Allocator)) + return std::string(PdbPath); + else + return File.takeError(); + + return make_error("PDB not found"); +} + +uint64_t NativeSession::getLoadAddress() const { return LoadAddress; } + +bool NativeSession::setLoadAddress(uint64_t Address) { + LoadAddress = Address; + return true; +} std::unique_ptr NativeSession::getGlobalScope() { return PDBSymbol::createAs(*this, getNativeGlobalScope()); @@ -95,12 +204,30 @@ NativeSession::getSymbolById(SymIndexId SymbolId) const { bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section, uint32_t &Offset) const { - return false; + uint32_t RVA = VA - getLoadAddress(); + return addressForRVA(RVA, Section, Offset); } -bool NativeSession::addressForRVA(uint32_t VA, uint32_t &Section, +bool NativeSession::addressForRVA(uint32_t RVA, uint32_t &Section, uint32_t &Offset) const { - return false; + auto Dbi = Pdb->getPDBDbiStream(); + if (!Dbi) + return false; + + Section = 0; + Offset = 0; + + if ((int32_t)RVA < 0) + return true; + + Offset = RVA; + for (; Section < Dbi->getSectionHeaders().size(); ++Section) { + auto &Sec = Dbi->getSectionHeaders()[Section]; + if (RVA < Sec.VirtualAddress) + return true; + Offset = RVA - Sec.VirtualAddress; + } + return true; } std::unique_ptr diff --git a/llvm/lib/DebugInfo/PDB/PDB.cpp b/llvm/lib/DebugInfo/PDB/PDB.cpp index e7b968cb7bea..a0d015c7839e 100644 --- a/llvm/lib/DebugInfo/PDB/PDB.cpp +++ b/llvm/lib/DebugInfo/PDB/PDB.cpp @@ -23,15 +23,8 @@ using namespace llvm::pdb; Error llvm::pdb::loadDataForPDB(PDB_ReaderType Type, StringRef Path, std::unique_ptr &Session) { // Create the correct concrete instance type based on the value of Type. - if (Type == PDB_ReaderType::Native) { - ErrorOr> ErrorOrBuffer = - MemoryBuffer::getFileOrSTDIN(Path, /*FileSize=*/-1, - /*RequiresNullTerminator=*/false); - if (!ErrorOrBuffer) - return errorCodeToError(ErrorOrBuffer.getError()); - - return NativeSession::createFromPdb(std::move(*ErrorOrBuffer), Session); - } + if (Type == PDB_ReaderType::Native) + return NativeSession::createFromPdbPath(Path, Session); #if LLVM_ENABLE_DIA_SDK return DIASession::createFromPdb(Path, Session); @@ -43,8 +36,17 @@ Error llvm::pdb::loadDataForPDB(PDB_ReaderType Type, StringRef Path, Error llvm::pdb::loadDataForEXE(PDB_ReaderType Type, StringRef Path, std::unique_ptr &Session) { // Create the correct concrete instance type based on the value of Type. - if (Type == PDB_ReaderType::Native) - return NativeSession::createFromExe(Path, Session); + if (Type == PDB_ReaderType::Native) { + if (auto Err = NativeSession::createFromExe(Path, Session)) { + consumeError(std::move(Err)); + + Expected PdbPath = NativeSession::searchForPdb({Path}); + if (!PdbPath) + return PdbPath.takeError(); + return NativeSession::createFromPdbPath(PdbPath.get(), Session); + } + return Error::success(); + } #if LLVM_ENABLE_DIA_SDK return DIASession::createFromExe(Path, Session); diff --git a/llvm/unittests/DebugInfo/PDB/CMakeLists.txt b/llvm/unittests/DebugInfo/PDB/CMakeLists.txt index 4edfd50c148d..c8c2659277a6 100644 --- a/llvm/unittests/DebugInfo/PDB/CMakeLists.txt +++ b/llvm/unittests/DebugInfo/PDB/CMakeLists.txt @@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_unittest_with_input_files(DebugInfoPDBTests HashTableTest.cpp + NativeSessionTest.cpp NativeSymbolReuseTest.cpp StringTableBuilderTest.cpp PDBApiTest.cpp diff --git a/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp b/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp new file mode 100644 index 000000000000..5cd4030802c6 --- /dev/null +++ b/llvm/unittests/DebugInfo/PDB/Inputs/SimpleTest.cpp @@ -0,0 +1,4 @@ +// Compile with "cl /c /Zi SimpleTest.cpp" +// Link with "link SimpleTest.obj /debug /nodefaultlib /entry:main" + +int main() { return 0; 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+using namespace llvm::pdb; + +extern const char *TestMainArgv0; + +static std::string getExePath() { + SmallString<128> InputsDir = unittest::getInputFileDirectory(TestMainArgv0); + llvm::sys::path::append(InputsDir, "SimpleTest.exe"); + return std::string(InputsDir); +} + +TEST(NativeSessionTest, TestCreateFromExe) { + std::unique_ptr S; + // Tests that the PDB file can be found if it is in the same directory as the + // executable. + Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); + ASSERT_THAT_ERROR(std::move(E), Succeeded()); +} + +TEST(NativeSessionTest, TestSetLoadAddress) { + std::unique_ptr S; + Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); + ASSERT_THAT_ERROR(std::move(E), Succeeded()); + + S->setLoadAddress(123); + EXPECT_EQ(S->getLoadAddress(), 123U); +} + +TEST(NativeSessionTest, TestAddressForVA) { + std::unique_ptr S; + Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); + ASSERT_THAT_ERROR(std::move(E), Succeeded()); + + uint64_t LoadAddr = S->getLoadAddress(); + uint32_t Section; + uint32_t Offset; + ASSERT_TRUE(S->addressForVA(LoadAddr + 5000, Section, Offset)); + EXPECT_EQ(1U, Section); + EXPECT_EQ(904U, Offset); + + ASSERT_TRUE(S->addressForVA(-1, Section, Offset)); + EXPECT_EQ(0U, Section); + EXPECT_EQ(0U, Offset); + + ASSERT_TRUE(S->addressForVA(4, Section, Offset)); + EXPECT_EQ(0U, Section); + EXPECT_EQ(4U, Offset); + + ASSERT_TRUE(S->addressForVA(LoadAddr + 100000, Section, Offset)); + EXPECT_EQ(3U, Section); + EXPECT_EQ(83616U, Offset); +} + +TEST(NativeSessionTest, TestAddressForRVA) { + std::unique_ptr S; + Error E = pdb::loadDataForEXE(PDB_ReaderType::Native, getExePath(), S); + ASSERT_THAT_ERROR(std::move(E), Succeeded()); + + uint32_t Section; + uint32_t Offset; + ASSERT_TRUE(S->addressForVA(5000, Section, Offset)); + EXPECT_EQ(1U, Section); + EXPECT_EQ(904U, Offset); + + ASSERT_TRUE(S->addressForVA(-1, Section, Offset)); + EXPECT_EQ(0U, Section); + EXPECT_EQ(0U, Offset); + + ASSERT_TRUE(S->addressForVA(4, Section, Offset)); + EXPECT_EQ(0U, Section); + EXPECT_EQ(4U, Offset); + + ASSERT_TRUE(S->addressForVA(100000, Section, Offset)); + EXPECT_EQ(3U, Section); + EXPECT_EQ(83616U, Offset); +} -- GitLab From dad6de411227faed9b15cd85d916e96e751b8528 Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Tue, 21 Apr 2020 23:36:07 +0000 Subject: [PATCH 022/910] [gn build] Port 23609331472 --- llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn index cfb92c6c57a9..16a5461494d5 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn @@ -9,6 +9,7 @@ unittest("DebugInfoPDBTests") { ] sources = [ "HashTableTest.cpp", + "NativeSessionTest.cpp", "NativeSymbolReuseTest.cpp", "PDBApiTest.cpp", "StringTableBuilderTest.cpp", -- GitLab From 7375212172951d2fc283c81d03c1a8588c3280c6 Mon Sep 17 00:00:00 2001 From: Lawrence D'Anna Date: Tue, 21 Apr 2020 16:53:47 -0700 Subject: [PATCH 023/910] get rid of PythonInteger::GetInteger() Summary: One small step in my long running quest to improve python exception handling in LLDB. Replace GetInteger() which just returns an int with As and friends, which return Expected types that can track python exceptions Reviewers: labath, jasonmolenda, JDevlieghere, vadimcn Reviewed By: labath Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D78462 --- lldb/bindings/python/python-typemaps.swig | 36 +++------ lldb/bindings/python/python-wrapper.swig | 41 +++++----- .../Python/PythonDataObjects.cpp | 40 +++++----- .../Python/PythonDataObjects.h | 27 ++++++- .../Python/ScriptInterpreterPython.cpp | 13 +--- .../Python/PythonDataObjectsTests.cpp | 74 +++++++++---------- 6 files changed, 114 insertions(+), 117 deletions(-) diff --git a/lldb/bindings/python/python-typemaps.swig b/lldb/bindings/python/python-typemaps.swig index 46dcaf611a4f..c08aeab71f78 100644 --- a/lldb/bindings/python/python-typemaps.swig +++ b/lldb/bindings/python/python-typemaps.swig @@ -59,37 +59,25 @@ $result = list.release(); } - %typemap(in) lldb::tid_t { - if (PythonInteger::Check($input)) - { - PythonInteger py_int(PyRefType::Borrowed, $input); - $1 = static_cast(py_int.GetInteger()); - } - else - { - PyErr_SetString(PyExc_ValueError, "Expecting an integer"); + PythonObject obj = Retain($input); + lldb::tid_t value = unwrapOrSetPythonException(As(obj)); + if (PyErr_Occurred()) return nullptr; - } + $1 = value; } %typemap(in) lldb::StateType { - if (PythonInteger::Check($input)) - { - PythonInteger py_int(PyRefType::Borrowed, $input); - int64_t state_type_value = py_int.GetInteger() ; - - if (state_type_value > lldb::StateType::kLastStateType) { - PyErr_SetString(PyExc_ValueError, "Not a valid StateType value"); - return nullptr; - } - $1 = static_cast(state_type_value); - } - else - { - PyErr_SetString(PyExc_ValueError, "Expecting an integer"); + PythonObject obj = Retain($input); + unsigned long long state_type_value = + unwrapOrSetPythonException(As(obj)); + if (PyErr_Occurred()) + return nullptr; + if (state_type_value > lldb::StateType::kLastStateType) { + PyErr_SetString(PyExc_ValueError, "Not a valid StateType value"); return nullptr; } + $1 = static_cast(state_type_value); } /* Typemap definitions to allow SWIG to properly handle char buffer. */ diff --git a/lldb/bindings/python/python-wrapper.swig b/lldb/bindings/python/python-wrapper.swig index 3a63165cf58d..f9e89373fe25 100644 --- a/lldb/bindings/python/python-wrapper.swig +++ b/lldb/bindings/python/python-wrapper.swig @@ -444,6 +444,7 @@ LLDBSwigPythonCallBreakpointResolver if (PyErr_Occurred()) { PyErr_Print(); + PyErr_Clear(); return 0; } @@ -457,11 +458,13 @@ LLDBSwigPythonCallBreakpointResolver return 1; } - PythonInteger int_result = result.AsType(); - if (!int_result.IsAllocated()) - return 0; + long long ret_val = unwrapOrSetPythonException(As(result)); - unsigned int ret_val = int_result.GetInteger(); + if (PyErr_Occurred()) { + PyErr_Print(); + PyErr_Clear(); + return 0; + } return ret_val; } @@ -515,26 +518,17 @@ LLDBSwigPython_CalculateNumChildren return 0; } - PythonObject result; - + size_t ret_val; if (arg_info.get().max_positional_args < 1) - result = pfunc(); + ret_val = unwrapOrSetPythonException(As(pfunc.Call())); else - result = pfunc(PythonInteger(max)); - - if (!result.IsAllocated()) - return 0; - - PythonInteger int_result = result.AsType(); - if (!int_result.IsAllocated()) - return 0; - - size_t ret_val = int_result.GetInteger(); + ret_val = unwrapOrSetPythonException(As(pfunc.Call(PythonInteger(max)))); - if (PyErr_Occurred()) //FIXME use Expected to catch python exceptions + if (PyErr_Occurred()) { PyErr_Print(); PyErr_Clear(); + return 0; } if (arg_info.get().max_positional_args < 1) @@ -588,16 +582,15 @@ LLDBSwigPython_GetIndexOfChildWithName if (!pfunc.IsAllocated()) return UINT32_MAX; - PythonObject result = pfunc(PythonString(child_name)); + llvm::Expected result = pfunc.Call(PythonString(child_name)); - if (!result.IsAllocated()) - return UINT32_MAX; + long long retval = unwrapOrSetPythonException(As(std::move(result))); - PythonInteger int_result = result.AsType(); - if (!int_result.IsAllocated()) + if (PyErr_Occurred()) { + PyErr_Clear(); // FIXME print this? do something else return UINT32_MAX; + } - int64_t retval = int_result.GetInteger(); if (retval >= 0) return (uint32_t)retval; diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp b/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp index 40ed22aceebf..3f00f671d88d 100644 --- a/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp +++ b/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp @@ -44,7 +44,15 @@ template <> Expected python::As(Expected &&obj) { if (!obj) return obj.takeError(); - return obj.get().AsLongLong(); + return obj->AsLongLong(); +} + +template <> +Expected +python::As(Expected &&obj) { + if (!obj) + return obj.takeError(); + return obj->AsUnsignedLongLong(); } template <> @@ -463,32 +471,22 @@ void PythonInteger::Convert(PyRefType &type, PyObject *&py_obj) { #endif } -int64_t PythonInteger::GetInteger() const { - if (m_py_obj) { - assert(PyLong_Check(m_py_obj) && - "PythonInteger::GetInteger has a PyObject that isn't a PyLong"); - - int overflow = 0; - int64_t result = PyLong_AsLongLongAndOverflow(m_py_obj, &overflow); - if (overflow != 0) { - // We got an integer that overflows, like 18446744072853913392L we can't - // use PyLong_AsLongLong() as it will return 0xffffffffffffffff. If we - // use the unsigned long long it will work as expected. - const uint64_t uval = PyLong_AsUnsignedLongLong(m_py_obj); - result = static_cast(uval); - } - return result; - } - return UINT64_MAX; -} - void PythonInteger::SetInteger(int64_t value) { *this = Take(PyLong_FromLongLong(value)); } StructuredData::IntegerSP PythonInteger::CreateStructuredInteger() const { StructuredData::IntegerSP result(new StructuredData::Integer); - result->SetValue(GetInteger()); + // FIXME this is really not ideal. Errors are silently converted to 0 + // and overflows are silently wrapped. But we'd need larger changes + // to StructuredData to fix it, so that's how it is for now. + llvm::Expected value = AsModuloUnsignedLongLong(); + if (!value) { + llvm::consumeError(value.takeError()); + result->SetValue(0); + } else { + result->SetValue(value.get()); + } return result; } diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h b/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h index 16896803e136..b09f42e0d540 100644 --- a/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h +++ b/lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h @@ -370,6 +370,27 @@ public: return r; } + llvm::Expected AsUnsignedLongLong() { + if (!m_py_obj) + return nullDeref(); + assert(!PyErr_Occurred()); + long long r = PyLong_AsUnsignedLongLong(m_py_obj); + if (PyErr_Occurred()) + return exception(); + return r; + } + + llvm::Expected AsModuloUnsignedLongLong() const { + // wraps on overflow, instead of raising an error. + if (!m_py_obj) + return nullDeref(); + assert(!PyErr_Occurred()); + unsigned long long r = PyLong_AsUnsignedLongLongMask(m_py_obj); + if (PyErr_Occurred()) + return exception(); + return r; + } + llvm::Expected IsInstance(const PythonObject &cls) { if (!m_py_obj || !cls.IsValid()) return nullDeref(); @@ -399,6 +420,10 @@ template <> llvm::Expected As(llvm::Expected &&obj); template <> llvm::Expected As(llvm::Expected &&obj); +template <> +llvm::Expected +As(llvm::Expected &&obj); + template <> llvm::Expected As(llvm::Expected &&obj); @@ -491,8 +516,6 @@ public: static bool Check(PyObject *py_obj); static void Convert(PyRefType &type, PyObject *&py_obj); - int64_t GetInteger() const; - void SetInteger(int64_t value); StructuredData::IntegerSP CreateStructuredInteger() const; diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp index c53b3bd0fb65..6f266772624a 100644 --- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp +++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp @@ -3150,20 +3150,15 @@ uint32_t ScriptInterpreterPythonImpl::GetFlagsForCommandObject( if (PyErr_Occurred()) PyErr_Clear(); - // right now we know this function exists and is callable.. - PythonObject py_return( - PyRefType::Owned, - PyObject_CallMethod(implementor.get(), callee_name, nullptr)); + long long py_return = unwrapOrSetPythonException( + As(implementor.CallMethod(callee_name))); // if it fails, print the error but otherwise go on if (PyErr_Occurred()) { PyErr_Print(); PyErr_Clear(); - } - - if (py_return.IsAllocated() && PythonInteger::Check(py_return.get())) { - PythonInteger int_value(PyRefType::Borrowed, py_return.get()); - result = int_value.GetInteger(); + } else { + result = py_return; } return result; diff --git a/lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp b/lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp index fe3b423b4842..75a1f5e67d32 100644 --- a/lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp +++ b/lldb/unittests/ScriptInterpreter/Python/PythonDataObjectsTests.cpp @@ -123,13 +123,11 @@ TEST_F(PythonDataObjectsTest, TestInstanceNameResolutionNoDot) { EXPECT_TRUE(major_version_field.IsAllocated()); EXPECT_TRUE(minor_version_field.IsAllocated()); - PythonInteger major_version_value = - major_version_field.AsType(); - PythonInteger minor_version_value = - minor_version_field.AsType(); + auto major_version_value = As(major_version_field); + auto minor_version_value = As(minor_version_field); - EXPECT_EQ(PY_MAJOR_VERSION, major_version_value.GetInteger()); - EXPECT_EQ(PY_MINOR_VERSION, minor_version_value.GetInteger()); + EXPECT_THAT_EXPECTED(major_version_value, llvm::HasValue(PY_MAJOR_VERSION)); + EXPECT_THAT_EXPECTED(minor_version_value, llvm::HasValue(PY_MINOR_VERSION)); } TEST_F(PythonDataObjectsTest, TestGlobalNameResolutionWithDot) { @@ -137,16 +135,14 @@ TEST_F(PythonDataObjectsTest, TestGlobalNameResolutionWithDot) { EXPECT_TRUE(sys_path.IsAllocated()); EXPECT_TRUE(PythonList::Check(sys_path.get())); - PythonInteger version_major = - m_main_module.ResolveName("sys.version_info.major") - .AsType(); - PythonInteger version_minor = - m_main_module.ResolveName("sys.version_info.minor") - .AsType(); - EXPECT_TRUE(version_major.IsAllocated()); - EXPECT_TRUE(version_minor.IsAllocated()); - EXPECT_EQ(PY_MAJOR_VERSION, version_major.GetInteger()); - EXPECT_EQ(PY_MINOR_VERSION, version_minor.GetInteger()); + auto version_major = + As(m_main_module.ResolveName("sys.version_info.major")); + + auto version_minor = + As(m_main_module.ResolveName("sys.version_info.minor")); + + EXPECT_THAT_EXPECTED(version_major, llvm::HasValue(PY_MAJOR_VERSION)); + EXPECT_THAT_EXPECTED(version_minor, llvm::HasValue(PY_MINOR_VERSION)); } TEST_F(PythonDataObjectsTest, TestDictionaryResolutionWithDot) { @@ -155,14 +151,14 @@ TEST_F(PythonDataObjectsTest, TestDictionaryResolutionWithDot) { dict.SetItemForKey(PythonString("sys"), m_sys_module); // Now use that dictionary to resolve `sys.version_info.major` - PythonInteger version_major = - PythonObject::ResolveNameWithDictionary("sys.version_info.major", dict) - .AsType(); - PythonInteger version_minor = - PythonObject::ResolveNameWithDictionary("sys.version_info.minor", dict) - .AsType(); - EXPECT_EQ(PY_MAJOR_VERSION, version_major.GetInteger()); - EXPECT_EQ(PY_MINOR_VERSION, version_minor.GetInteger()); + auto version_major = As( + PythonObject::ResolveNameWithDictionary("sys.version_info.major", dict)); + + auto version_minor = As( + PythonObject::ResolveNameWithDictionary("sys.version_info.minor", dict)); + + EXPECT_THAT_EXPECTED(version_major, llvm::HasValue(PY_MAJOR_VERSION)); + EXPECT_THAT_EXPECTED(version_minor, llvm::HasValue(PY_MINOR_VERSION)); } TEST_F(PythonDataObjectsTest, TestPythonInteger) { @@ -176,7 +172,8 @@ TEST_F(PythonDataObjectsTest, TestPythonInteger) { PythonInteger python_int(PyRefType::Owned, py_int); EXPECT_EQ(PyObjectType::Integer, python_int.GetObjectType()); - EXPECT_EQ(12, python_int.GetInteger()); + auto python_int_value = As(python_int); + EXPECT_THAT_EXPECTED(python_int_value, llvm::HasValue(12)); #endif // Verify that `PythonInteger` works correctly when given a PyLong object. @@ -187,12 +184,14 @@ TEST_F(PythonDataObjectsTest, TestPythonInteger) { // Verify that you can reset the value and that it is reflected properly. python_long.SetInteger(40); - EXPECT_EQ(40, python_long.GetInteger()); + auto e = As(python_long); + EXPECT_THAT_EXPECTED(e, llvm::HasValue(40)); // Test that creating a `PythonInteger` object works correctly with the // int constructor. PythonInteger constructed_int(7); - EXPECT_EQ(7, constructed_int.GetInteger()); + auto value = As(constructed_int); + EXPECT_THAT_EXPECTED(value, llvm::HasValue(7)); } TEST_F(PythonDataObjectsTest, TestPythonBoolean) { @@ -339,7 +338,8 @@ TEST_F(PythonDataObjectsTest, TestPythonListValueEquality) { PythonInteger chk_int(PyRefType::Borrowed, chk_value1.get()); PythonString chk_str(PyRefType::Borrowed, chk_value2.get()); - EXPECT_EQ(long_value0, chk_int.GetInteger()); + auto chkint = As(chk_value1); + ASSERT_THAT_EXPECTED(chkint, llvm::HasValue(long_value0)); EXPECT_EQ(string_value1, chk_str.GetString()); } @@ -367,7 +367,8 @@ TEST_F(PythonDataObjectsTest, TestPythonListManipulation) { PythonInteger chk_int(PyRefType::Borrowed, chk_value1.get()); PythonString chk_str(PyRefType::Borrowed, chk_value2.get()); - EXPECT_EQ(long_value0, chk_int.GetInteger()); + auto e = As(chk_int); + EXPECT_THAT_EXPECTED(e, llvm::HasValue(long_value0)); EXPECT_EQ(string_value1, chk_str.GetString()); } @@ -487,10 +488,10 @@ TEST_F(PythonDataObjectsTest, TestPythonDictionaryValueEquality) { EXPECT_TRUE(PythonInteger::Check(chk_value1.get())); EXPECT_TRUE(PythonString::Check(chk_value2.get())); - PythonInteger chk_int(PyRefType::Borrowed, chk_value1.get()); PythonString chk_str(PyRefType::Borrowed, chk_value2.get()); + auto chkint = As(chk_value1); - EXPECT_EQ(value_0, chk_int.GetInteger()); + EXPECT_THAT_EXPECTED(chkint, llvm::HasValue(value_0)); EXPECT_EQ(value_1, chk_str.GetString()); } @@ -524,10 +525,10 @@ TEST_F(PythonDataObjectsTest, TestPythonDictionaryManipulation) { EXPECT_TRUE(PythonInteger::Check(chk_value1.get())); EXPECT_TRUE(PythonString::Check(chk_value2.get())); - PythonInteger chk_int(PyRefType::Borrowed, chk_value1.get()); + auto chkint = As(chk_value1); PythonString chk_str(PyRefType::Borrowed, chk_value2.get()); - EXPECT_EQ(value_0, chk_int.GetInteger()); + EXPECT_THAT_EXPECTED(chkint, llvm::HasValue(value_0)); EXPECT_EQ(value_1, chk_str.GetString()); } @@ -594,10 +595,9 @@ TEST_F(PythonDataObjectsTest, TestObjectAttributes) { EXPECT_TRUE(py_int.HasAttribute("numerator")); EXPECT_FALSE(py_int.HasAttribute("this_should_not_exist")); - PythonInteger numerator_attr = - py_int.GetAttributeValue("numerator").AsType(); - EXPECT_TRUE(numerator_attr.IsAllocated()); - EXPECT_EQ(42, numerator_attr.GetInteger()); + auto numerator_attr = As(py_int.GetAttributeValue("numerator")); + + EXPECT_THAT_EXPECTED(numerator_attr, llvm::HasValue(42)); } TEST_F(PythonDataObjectsTest, TestExtractingUInt64ThroughStructuredData) { -- GitLab From a30e7ea88e75568feed020aedae73c52de888835 Mon Sep 17 00:00:00 2001 From: Andrew Browne Date: Mon, 6 Apr 2020 14:42:57 -0700 Subject: [PATCH 024/910] Make SmallVector assert if it cannot grow. Context: /// Double the size of the allocated memory, guaranteeing space for at /// least one more element or MinSize if specified. void grow(size_t MinSize = 0) { this->grow_pod(MinSize, sizeof(T)); } void push_back(const T &Elt) { if (LLVM_UNLIKELY(this->size() >= this->capacity())) this->grow(); memcpy(reinterpret_cast(this->end()), &Elt, sizeof(T)); this->set_size(this->size() + 1); } When grow is called in push_back() without a MinSize specified, this is relying on the guarantee of space for at least one more element. There is an edge case bug where the SmallVector is already at its maximum size and push_back() calls grow() with default MinSize of zero. Grow is unable to provide space for one more element, but push_back() assumes the additional element it will be available. This can result in silent memory corruption, as this->end() will be an invalid pointer and the program may continue executing. Another alternative to fix would be to remove the default argument from grow(), which would mean several changing grow() to grow(this->size()+1) in several places. No test case added because it would require allocating ~4GB. Reviewers: echristo Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77601 --- llvm/include/llvm/ADT/SmallVector.h | 7 +++++++ llvm/lib/Support/SmallVector.cpp | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/llvm/include/llvm/ADT/SmallVector.h b/llvm/include/llvm/ADT/SmallVector.h index 28b514d530dc..12a58761955b 100644 --- a/llvm/include/llvm/ADT/SmallVector.h +++ b/llvm/include/llvm/ADT/SmallVector.h @@ -46,6 +46,7 @@ protected: /// This is an implementation of the grow() method which only works /// on POD-like data types and is out of line to reduce code duplication. + /// This function will report a fatal error if it cannot increase capacity. void grow_pod(void *FirstEl, size_t MinCapacity, size_t TSize); public: @@ -234,6 +235,12 @@ void SmallVectorTemplateBase::grow(size_t MinSize) { if (MinSize > UINT32_MAX) report_bad_alloc_error("SmallVector capacity overflow during allocation"); + // Ensure we can meet the guarantee of space for at least one more element. + // The above check alone will not catch the case where grow is called with a + // default MinCapacity of 0, but the current capacity cannot be increased. + if (this->capacity() == size_t(UINT32_MAX)) + report_bad_alloc_error("SmallVector capacity unable to grow"); + // Always grow, even from zero. size_t NewCapacity = size_t(NextPowerOf2(this->capacity() + 2)); NewCapacity = std::min(std::max(NewCapacity, MinSize), size_t(UINT32_MAX)); diff --git a/llvm/lib/Support/SmallVector.cpp b/llvm/lib/Support/SmallVector.cpp index 36f0a81f6b00..9ece0c5a3b62 100644 --- a/llvm/lib/Support/SmallVector.cpp +++ b/llvm/lib/Support/SmallVector.cpp @@ -39,12 +39,19 @@ static_assert(sizeof(SmallVector) == /// grow_pod - This is an implementation of the grow() method which only works /// on POD-like datatypes and is out of line to reduce code duplication. +/// This function will report a fatal error if it cannot increase capacity. void SmallVectorBase::grow_pod(void *FirstEl, size_t MinCapacity, size_t TSize) { // Ensure we can fit the new capacity in 32 bits. if (MinCapacity > UINT32_MAX) report_bad_alloc_error("SmallVector capacity overflow during allocation"); + // Ensure we can meet the guarantee of space for at least one more element. + // The above check alone will not catch the case where grow is called with a + // default MinCapacity of 0, but the current capacity cannot be increased. + if (capacity() == size_t(UINT32_MAX)) + report_bad_alloc_error("SmallVector capacity unable to grow"); + size_t NewCapacity = 2 * capacity() + 1; // Always grow. NewCapacity = std::min(std::max(NewCapacity, MinCapacity), size_t(UINT32_MAX)); -- GitLab From 4ca2cad947d09ba0402f5b85d165aa7fcfbd9e3e Mon Sep 17 00:00:00 2001 From: Justin Hibbits Date: Tue, 21 Apr 2020 15:36:08 -0500 Subject: [PATCH 025/910] [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF Summary: Change the default ABI to be compatible with GCC. For 32-bit ELF targets other than Linux, Clang now returns small structs in registers r3/r4. This affects FreeBSD, NetBSD, OpenBSD. There is no change for 32-bit Linux, where Clang continues to return all structs in memory. Add clang options -maix-struct-return (to return structs in memory) and -msvr4-struct-return (to return structs in registers) to be compatible with gcc. These options are only for PPC32; reject them on PPC64 and other targets. The options are like -fpcc-struct-return and -freg-struct-return for X86_32, and use similar code. To actually return a struct in registers, coerce it to an integer of the same size. LLVM may optimize the code to remove unnecessary accesses to memory, and will return i32 in r3 or i64 in r3:r4. Fixes PR#40736 Patch by George Koehler! Reviewed By: jhibbits, nemanjai Differential Revision: https://reviews.llvm.org/D73290 --- clang/docs/ClangCommandLineReference.rst | 10 +++ clang/include/clang/Driver/Options.td | 6 ++ clang/lib/CodeGen/TargetInfo.cpp | 82 +++++++++++++++++++-- clang/lib/Driver/ToolChains/Clang.cpp | 13 ++++ clang/lib/Frontend/CompilerInvocation.cpp | 13 +++- clang/test/CodeGen/ppc32-struct-return.c | 88 +++++++++++++++++++++++ clang/test/Driver/ppc-unsupported.c | 10 +++ 7 files changed, 212 insertions(+), 10 deletions(-) create mode 100644 clang/test/CodeGen/ppc32-struct-return.c create mode 100644 clang/test/Driver/ppc-unsupported.c diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst index e5a649702037..c7afcf7cf605 100644 --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -2973,6 +2973,11 @@ Enable MT ASE (MIPS only) PowerPC ------- +.. option:: -maix-struct-return + +Override the default ABI for 32-bit targets to return all structs in memory, +as in the Power 32-bit ABI for Linux (2011), and on AIX and Darwin. + .. option:: -maltivec, -mno-altivec .. option:: -mcmpb, -mno-cmpb @@ -3009,6 +3014,11 @@ PowerPC .. option:: -mspe, -mno-spe +.. option:: -msvr4-struct-return + +Override the default ABI for 32-bit targets to return small structs in +registers, as in the System V ABI (1995). + .. option:: -mvsx, -mno-vsx WebAssembly diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index fcfc3a387de8..889880cc86d6 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2510,6 +2510,12 @@ def mlongcall: Flag<["-"], "mlongcall">, Group; def mno_longcall : Flag<["-"], "mno-longcall">, Group; +def maix_struct_return : Flag<["-"], "maix-struct-return">, + Group, Flags<[CC1Option]>, + HelpText<"Return all structs in memory (PPC32 only)">; +def msvr4_struct_return : Flag<["-"], "msvr4-struct-return">, + Group, Flags<[CC1Option]>, + HelpText<"Return small structs in registers (PPC32 only)">; def mvx : Flag<["-"], "mvx">, Group; def mno_vx : Flag<["-"], "mno-vx">, Group; diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 22128534beda..0a5fb27ba015 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -4177,12 +4177,24 @@ namespace { /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information. class PPC32_SVR4_ABIInfo : public DefaultABIInfo { bool IsSoftFloatABI; + bool IsRetSmallStructInRegABI; CharUnits getParamTypeAlignment(QualType Ty) const; public: - PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI) - : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {} + PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI, + bool RetSmallStructInRegABI) + : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI), + IsRetSmallStructInRegABI(RetSmallStructInRegABI) {} + + ABIArgInfo classifyReturnType(QualType RetTy) const; + + void computeInfo(CGFunctionInfo &FI) const override { + if (!getCXXABI().classifyReturnType(FI)) + FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); + for (auto &I : FI.arguments()) + I.info = classifyArgumentType(I.type); + } Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty) const override; @@ -4190,8 +4202,13 @@ public: class PPC32TargetCodeGenInfo : public TargetCodeGenInfo { public: - PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI) - : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {} + PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI, + bool RetSmallStructInRegABI) + : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI, + RetSmallStructInRegABI)) {} + + static bool isStructReturnInRegABI(const llvm::Triple &Triple, + const CodeGenOptions &Opts); int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { // This is recovered from gcc output. @@ -4227,6 +4244,34 @@ CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const { return CharUnits::fromQuantity(4); } +ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { + uint64_t Size; + + // -msvr4-struct-return puts small aggregates in GPR3 and GPR4. + if (isAggregateTypeForABI(RetTy) && IsRetSmallStructInRegABI && + (Size = getContext().getTypeSize(RetTy)) <= 64) { + // System V ABI (1995), page 3-22, specified: + // > A structure or union whose size is less than or equal to 8 bytes + // > shall be returned in r3 and r4, as if it were first stored in the + // > 8-byte aligned memory area and then the low addressed word were + // > loaded into r3 and the high-addressed word into r4. Bits beyond + // > the last member of the structure or union are not defined. + // + // GCC for big-endian PPC32 inserts the pad before the first member, + // not "beyond the last member" of the struct. To stay compatible + // with GCC, we coerce the struct to an integer of the same size. + // LLVM will extend it and return i32 in r3, or i64 in r3:r4. + if (Size == 0) + return ABIArgInfo::getIgnore(); + else { + llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size); + return ABIArgInfo::getDirect(CoerceTy); + } + } + + return DefaultABIInfo::classifyReturnType(RetTy); +} + // TODO: this implementation is now likely redundant with // DefaultABIInfo::EmitVAArg. Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList, @@ -4382,6 +4427,25 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList, return Result; } +bool PPC32TargetCodeGenInfo::isStructReturnInRegABI( + const llvm::Triple &Triple, const CodeGenOptions &Opts) { + assert(Triple.getArch() == llvm::Triple::ppc); + + switch (Opts.getStructReturnConvention()) { + case CodeGenOptions::SRCK_Default: + break; + case CodeGenOptions::SRCK_OnStack: // -maix-struct-return + return false; + case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return + return true; + } + + if (Triple.isOSBinFormatELF() && !Triple.isOSLinux()) + return true; + + return false; +} + bool PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const { @@ -10264,10 +10328,14 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind)); } - case llvm::Triple::ppc: + case llvm::Triple::ppc: { + bool IsSoftFloat = + CodeGenOpts.FloatABI == "soft" || getTarget().hasFeature("spe"); + bool RetSmallStructInRegABI = + PPC32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts); return SetCGInfo( - new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft" || - getTarget().hasFeature("spe"))); + new PPC32TargetCodeGenInfo(Types, IsSoftFloat, RetSmallStructInRegABI)); + } case llvm::Triple::ppc64: if (Triple.isOSBinFormatELF()) { PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 415ef27eee0a..2c44b2a4e9b4 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -4535,6 +4535,19 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back(A->getValue()); } + if (Arg *A = Args.getLastArg(options::OPT_maix_struct_return, + options::OPT_msvr4_struct_return)) { + if (TC.getArch() != llvm::Triple::ppc) { + D.Diag(diag::err_drv_unsupported_opt_for_target) + << A->getSpelling() << RawTriple.str(); + } else if (A->getOption().matches(options::OPT_maix_struct_return)) { + CmdArgs.push_back("-maix-struct-return"); + } else { + assert(A->getOption().matches(options::OPT_msvr4_struct_return)); + CmdArgs.push_back("-msvr4-struct-return"); + } + } + if (Arg *A = Args.getLastArg(options::OPT_fpcc_struct_return, options::OPT_freg_struct_return)) { if (TC.getArch() != llvm::Triple::x86) { diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index fc93dfafc5fc..6a988670eb02 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1297,11 +1297,18 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Val; } - if (Arg *A = Args.getLastArg(OPT_fpcc_struct_return, OPT_freg_struct_return)) { - if (A->getOption().matches(OPT_fpcc_struct_return)) { + // X86_32 has -fppc-struct-return and -freg-struct-return. + // PPC32 has -maix-struct-return and -msvr4-struct-return. + if (Arg *A = + Args.getLastArg(OPT_fpcc_struct_return, OPT_freg_struct_return, + OPT_maix_struct_return, OPT_msvr4_struct_return)) { + const Option &O = A->getOption(); + if (O.matches(OPT_fpcc_struct_return) || + O.matches(OPT_maix_struct_return)) { Opts.setStructReturnConvention(CodeGenOptions::SRCK_OnStack); } else { - assert(A->getOption().matches(OPT_freg_struct_return)); + assert(O.matches(OPT_freg_struct_return) || + O.matches(OPT_msvr4_struct_return)); Opts.setStructReturnConvention(CodeGenOptions::SRCK_InRegs); } } diff --git a/clang/test/CodeGen/ppc32-struct-return.c b/clang/test/CodeGen/ppc32-struct-return.c new file mode 100644 index 000000000000..30a6a26820b0 --- /dev/null +++ b/clang/test/CodeGen/ppc32-struct-return.c @@ -0,0 +1,88 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -triple powerpc-unknown-freebsd \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-SVR4 +// RUN: %clang_cc1 -triple powerpc-unknown-linux \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-AIX +// RUN: %clang_cc1 -triple powerpc-unknown-linux -maix-struct-return \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-AIX +// RUN: %clang_cc1 -triple powerpc-unknown-linux -msvr4-struct-return \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-SVR4 +// RUN: %clang_cc1 -triple powerpc-unknown-netbsd \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-SVR4 +// RUN: %clang_cc1 -triple powerpc-unknown-openbsd \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-SVR4 +// RUN: %clang_cc1 -triple powerpc-unknown-openbsd -maix-struct-return \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-AIX +// RUN: %clang_cc1 -triple powerpc-unknown-openbsd -msvr4-struct-return \ +// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-SVR4 + +typedef struct { +} Zero; +typedef struct { + char c; +} One; +typedef struct { + short s; +} Two; +typedef struct { + char c[3]; +} Three; +typedef struct { + float f; +} Four; // svr4 to return i32, not float +typedef struct { + char c[5]; +} Five; +typedef struct { + short s[3]; +} Six; +typedef struct { + char c[7]; +} Seven; +typedef struct { + int i; + char c; +} Eight; // padded for alignment +typedef struct { + char c[9]; +} Nine; + +// CHECK-AIX-LABEL: define void @ret0(%struct.Zero* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define void @ret0() +Zero ret0(void) { return (Zero){}; } + +// CHECK-AIX-LABEL: define void @ret1(%struct.One* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i8 @ret1() +One ret1(void) { return (One){'a'}; } + +// CHECK-AIX-LABEL: define void @ret2(%struct.Two* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i16 @ret2() +Two ret2(void) { return (Two){123}; } + +// CHECK-AIX-LABEL: define void @ret3(%struct.Three* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i24 @ret3() +Three ret3(void) { return (Three){"abc"}; } + +// CHECK-AIX-LABEL: define void @ret4(%struct.Four* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i32 @ret4() +Four ret4(void) { return (Four){0.4}; } + +// CHECK-AIX-LABEL: define void @ret5(%struct.Five* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i40 @ret5() +Five ret5(void) { return (Five){"abcde"}; } + +// CHECK-AIX-LABEL: define void @ret6(%struct.Six* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i48 @ret6() +Six ret6(void) { return (Six){12, 34, 56}; } + +// CHECK-AIX-LABEL: define void @ret7(%struct.Seven* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i56 @ret7() +Seven ret7(void) { return (Seven){"abcdefg"}; } + +// CHECK-AIX-LABEL: define void @ret8(%struct.Eight* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define i64 @ret8() +Eight ret8(void) { return (Eight){123, 'a'}; } + +// CHECK-AIX-LABEL: define void @ret9(%struct.Nine* noalias sret {{[^,]*}}) +// CHECK-SVR4-LABEL: define void @ret9(%struct.Nine* noalias sret {{[^,]*}}) +Nine ret9(void) { return (Nine){"abcdefghi"}; } diff --git a/clang/test/Driver/ppc-unsupported.c b/clang/test/Driver/ppc-unsupported.c new file mode 100644 index 000000000000..84760c8c435b --- /dev/null +++ b/clang/test/Driver/ppc-unsupported.c @@ -0,0 +1,10 @@ +// REQUIRES: powerpc-registered-target +// RUN: not %clang -target powerpc64-unknown-freebsd -maix-struct-return \ +// RUN: -c %s 2>&1 | FileCheck %s +// RUN: not %clang -target powerpc64-unknown-freebsd -msvr4-struct-return \ +// RUN: -c %s 2>&1 | FileCheck %s +// RUN: not %clang -target powerpc64le-unknown-linux -maix-struct-return \ +// RUN: -c %s 2>&1 | FileCheck %s +// RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \ +// RUN: -c %s 2>&1 | FileCheck %s +// CHECK: unsupported option -- GitLab From 564530e50ad4870801a2080a08645cc1cc2df805 Mon Sep 17 00:00:00 2001 From: Dan Liew Date: Mon, 20 Apr 2020 18:27:43 -0700 Subject: [PATCH 026/910] Add missing call to `Symbolizer::LateInitialize()` in UBSan's standalone init. Summary: This fixes symbolization in Standalone UBSan mode for the Darwin simulators. 861b69faee5df8d4e13ef316c7474a10e4069e81 (rdar://problem/58789439) tried to fix symbolization for all sanitizers on Darwin simulators but unfortunately it only fixed the problem for TSan. For UBSan in standalone mode the fix wasn't sufficient because UBSan's standalone init doesn't call `Symbolizer::LateInitialize()` like ASan and TSan do. This meant that `AtosSymbolizerProcess::LateInitialize()` was never being called before `AtosSymbolizerProcess::StartSymbolizerSubprocess()` which breaks an invariant we expect to hold. The missing call to `Symbolizer::LateInitialize()` during UBSan's standalone init seems like an accidently omission so this patch simply adds it. rdar://problem/62083617 Reviewers: vitalybuka, kubamracek, yln, samsonov Subscribers: #sanitizers, llvm-commits Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D78530 --- compiler-rt/lib/ubsan/ubsan_init.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/lib/ubsan/ubsan_init.cpp b/compiler-rt/lib/ubsan/ubsan_init.cpp index 1a3b7d372674..26b6227aa484 100644 --- a/compiler-rt/lib/ubsan/ubsan_init.cpp +++ b/compiler-rt/lib/ubsan/ubsan_init.cpp @@ -41,6 +41,7 @@ static void CommonStandaloneInit() { AndroidLogInit(); InitializeCoverage(common_flags()->coverage, common_flags()->coverage_dir); CommonInit(); + Symbolizer::LateInitialize(); } void __ubsan::InitAsStandalone() { -- GitLab From da820f4f5753062501a14ae4336b1c055535e54f Mon Sep 17 00:00:00 2001 From: Dan Liew Date: Mon, 20 Apr 2020 18:52:26 -0700 Subject: [PATCH 027/910] Add missing call to `__sanitizer::InitializePlatformEarly()` in UBSan's standalone init. Summary: While working on rdar://problem/62083617 I noticed this call was missing. This is a no-op for all platforms except Darwin. For Darwin this means the `use_xnu_fast_mmap` flag is initialized as it was intended when using UBSan in standalone mode. Reviewers: vitalybuka, vsk, kubamracek, yln, samsonov Subscribers: #sanitizers, llvm-commits Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D78532 --- compiler-rt/lib/ubsan/ubsan_init.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/lib/ubsan/ubsan_init.cpp b/compiler-rt/lib/ubsan/ubsan_init.cpp index 26b6227aa484..e0be5a72ec42 100644 --- a/compiler-rt/lib/ubsan/ubsan_init.cpp +++ b/compiler-rt/lib/ubsan/ubsan_init.cpp @@ -37,6 +37,7 @@ static void CommonStandaloneInit() { SanitizerToolName = GetSanititizerToolName(); CacheBinaryName(); InitializeFlags(); + __sanitizer::InitializePlatformEarly(); __sanitizer_set_report_path(common_flags()->log_path); AndroidLogInit(); InitializeCoverage(common_flags()->coverage, common_flags()->coverage_dir); -- GitLab From 5a7a6382bc066b93cdd4c60a489b480d0e74a254 Mon Sep 17 00:00:00 2001 From: Sameer Sahasrabuddhe Date: Wed, 22 Apr 2020 07:27:26 +0530 Subject: [PATCH 028/910] FixIrreducible: don't crash when moving a child loop Summary: When an irreducible SCC is converted into a new natural loop, existing loops included in that SCC now become children of the new loop. The logic that moves these loops from the parent loop to the new loop invoked undefined behaviour when it modified the container that it was iterating over. Fixed this by first extracting all the loops that are to be removed from the parent. Fixes bug 45623. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D78544 --- llvm/lib/Transforms/Utils/FixIrreducible.cpp | 23 +++-- .../Transforms/FixIrreducible/bug45623.ll | 89 +++++++++++++++++++ 2 files changed, 100 insertions(+), 12 deletions(-) create mode 100644 llvm/test/Transforms/FixIrreducible/bug45623.ll diff --git a/llvm/lib/Transforms/Utils/FixIrreducible.cpp b/llvm/lib/Transforms/Utils/FixIrreducible.cpp index ef8b80cecac9..df646b70a145 100644 --- a/llvm/lib/Transforms/Utils/FixIrreducible.cpp +++ b/llvm/lib/Transforms/Utils/FixIrreducible.cpp @@ -118,14 +118,17 @@ static void reconnectChildLoops(LoopInfo &LI, Loop *ParentLoop, Loop *NewLoop, SetVector &Headers) { auto &CandidateLoops = ParentLoop ? ParentLoop->getSubLoopsVector() : LI.getTopLevelLoopsVector(); - // Partition the candidate loops into two ranges. The first part - // contains loops that are not children of the new loop. The second - // part contains children that need to be moved to the new loop. - auto FirstChild = - std::partition(CandidateLoops.begin(), CandidateLoops.end(), [&](Loop *L) { + // The new loop cannot be its own child, and any candidate is a + // child iff its header is owned by the new loop. Move all the + // children to a new vector. + auto FirstChild = std::partition( + CandidateLoops.begin(), CandidateLoops.end(), [&](Loop *L) { return L == NewLoop || Blocks.count(L->getHeader()) == 0; }); - for (auto II = FirstChild, IE = CandidateLoops.end(); II != IE; ++II) { + SmallVector ChildLoops(FirstChild, CandidateLoops.end()); + CandidateLoops.erase(FirstChild, CandidateLoops.end()); + + for (auto II = ChildLoops.begin(), IE = ChildLoops.end(); II != IE; ++II) { auto Child = *II; LLVM_DEBUG(dbgs() << "child loop: " << Child->getHeader()->getName() << "\n"); @@ -143,14 +146,10 @@ static void reconnectChildLoops(LoopInfo &LI, Loop *ParentLoop, Loop *NewLoop, continue; } - if (ParentLoop) { - LLVM_DEBUG(dbgs() << "removed child loop from parent\n"); - ParentLoop->removeChildLoop(Child); - } - LLVM_DEBUG(dbgs() << "added child loop to new loop\n"); + Child->setParentLoop(nullptr); NewLoop->addChildLoop(Child); + LLVM_DEBUG(dbgs() << "added child loop to new loop\n"); } - CandidateLoops.erase(FirstChild, CandidateLoops.end()); } // Given a set of blocks and headers in an irreducible SCC, convert it into a diff --git a/llvm/test/Transforms/FixIrreducible/bug45623.ll b/llvm/test/Transforms/FixIrreducible/bug45623.ll new file mode 100644 index 000000000000..89d31dd4fea6 --- /dev/null +++ b/llvm/test/Transforms/FixIrreducible/bug45623.ll @@ -0,0 +1,89 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -fix-irreducible -S | FileCheck %s + +define dso_local void @tre_tnfa_run_backtrack() { +; CHECK-LABEL: @tre_tnfa_run_backtrack( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[RETRY:%.*]] +; CHECK: retry: +; CHECK-NEXT: br label [[IRR_GUARD:%.*]] +; CHECK: while.body248: +; CHECK-NEXT: br i1 undef, label [[IF_THEN250:%.*]], label [[IF_END275:%.*]] +; CHECK: if.then250: +; CHECK-NEXT: br label [[FOR_COND264:%.*]] +; CHECK: for.cond264: +; CHECK-NEXT: br i1 undef, label [[FOR_BODY267:%.*]], label [[IRR_GUARD]] +; CHECK: for.body267: +; CHECK-NEXT: br label [[FOR_COND264]] +; CHECK: if.end275: +; CHECK-NEXT: br label [[FOR_COND342:%.*]] +; CHECK: for.cond342: +; CHECK-NEXT: br i1 undef, label [[FOR_BODY345:%.*]], label [[FOR_END580:%.*]] +; CHECK: for.body345: +; CHECK-NEXT: br label [[FOR_COND342]] +; CHECK: for.end580: +; CHECK-NEXT: br label [[IRR_GUARD]] +; CHECK: backtrack: +; CHECK-NEXT: br i1 undef, label [[IF_THEN595:%.*]], label [[IF_ELSE629:%.*]] +; CHECK: if.then595: +; CHECK-NEXT: br label [[FOR_COND616:%.*]] +; CHECK: for.cond616: +; CHECK-NEXT: br i1 undef, label [[FOR_BODY619:%.*]], label [[FOR_END626:%.*]] +; CHECK: for.body619: +; CHECK-NEXT: br label [[FOR_COND616]] +; CHECK: for.end626: +; CHECK-NEXT: br label [[IRR_GUARD]] +; CHECK: if.else629: +; CHECK-NEXT: br label [[RETRY]] +; CHECK: irr.guard: +; CHECK-NEXT: [[GUARD_BACKTRACK:%.*]] = phi i1 [ true, [[FOR_END580]] ], [ true, [[FOR_COND264]] ], [ undef, [[RETRY]] ], [ false, [[FOR_END626]] ] +; CHECK-NEXT: br i1 [[GUARD_BACKTRACK]], label [[BACKTRACK:%.*]], label [[WHILE_BODY248:%.*]] +; +entry: + br label %retry + +retry: + br i1 undef, label %backtrack, label %while.body248 + +while.body248: ; preds = %for.end626, %retry + br i1 undef, label %if.then250, label %if.end275 + +if.then250: ; preds = %while.body248 + br label %for.cond264 + +for.cond264: ; preds = %for.body267, %if.then250 + br i1 undef, label %for.body267, label %backtrack + +for.body267: ; preds = %for.cond264 + br label %for.cond264 + +if.end275: ; preds = %while.body248 + br label %for.cond342 + +for.cond342: ; preds = %for.body345, %if.end275 + br i1 undef, label %for.body345, label %for.end580 + +for.body345: ; preds = %for.cond342 + br label %for.cond342 + +for.end580: ; preds = %for.cond342 + br label %backtrack + +backtrack: ; preds = %for.end580, %for.cond264, %retry + br i1 undef, label %if.then595, label %if.else629 + +if.then595: ; preds = %backtrack + br label %for.cond616 + +for.cond616: ; preds = %for.body619, %if.then595 + br i1 undef, label %for.body619, label %for.end626 + +for.body619: ; preds = %for.cond616 + br label %for.cond616 + +for.end626: ; preds = %for.cond616 + br label %while.body248 + +if.else629: ; preds = %backtrack + br label %retry +} -- GitLab From 8d45d6e39d5cfd1196b8601704ff8066b809e3c7 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 21 Apr 2020 18:27:40 -0700 Subject: [PATCH 029/910] [Frontend] Drop unneeded CC1 options --- clang/include/clang/Driver/Options.td | 19 ++++++++----------- clang/lib/Frontend/CompilerInvocation.cpp | 4 +--- clang/test/CodeGenObjCXX/return.mm | 5 +++-- 3 files changed, 12 insertions(+), 16 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 889880cc86d6..2ec7269372b1 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2002,7 +2002,6 @@ def fno_unique_section_names : Flag <["-"], "fno-unique-section-names">, Group, Flags<[CC1Option]>; def fstrict_return : Flag<["-"], "fstrict-return">, Group, - Flags<[CC1Option]>, HelpText<"Always treat control flow paths that fall off the end of a " "non-void function as unreachable">; def fno_strict_return : Flag<["-"], "fno-strict-return">, Group, @@ -2015,15 +2014,13 @@ def fno_allow_editor_placeholders : Flag<["-"], "fno-allow-editor-placeholders">, Group; def fdebug_types_section: Flag <["-"], "fdebug-types-section">, Group, - Flags<[CC1Option]>, HelpText<"Place debug types in their own section (ELF Only)">; -def fno_debug_types_section: Flag<["-"], "fno-debug-types-section">, Group, - Flags<[CC1Option]>; + HelpText<"Place debug types in their own section (ELF Only)">; +def fno_debug_types_section: Flag<["-"], "fno-debug-types-section">, Group; def fdebug_ranges_base_address: Flag <["-"], "fdebug-ranges-base-address">, Group, Flags<[CC1Option]>, HelpText<"Use DWARF base address selection entries in debug_ranges">; -def fno_debug_ranges_base_address: Flag <["-"], "fno-debug-ranges-base-address">, Group, - Flags<[CC1Option]>; +def fno_debug_ranges_base_address: Flag <["-"], "fno-debug-ranges-base-address">, Group; def fsplit_dwarf_inlining: Flag <["-"], "fsplit-dwarf-inlining">, Group, - Flags<[CC1Option]>, HelpText<"Provide minimal debug info in the object/executable to facilitate online symbolication/stack traces in the absence of .dwo/.dwp files when using Split DWARF">; + HelpText<"Provide minimal debug info in the object/executable to facilitate online symbolication/stack traces in the absence of .dwo/.dwp files when using Split DWARF">; def fno_split_dwarf_inlining: Flag<["-"], "fno-split-dwarf-inlining">, Group, Flags<[CC1Option]>; def fdebug_default_version: Joined<["-"], "fdebug-default-version=">, Group, @@ -2033,14 +2030,14 @@ def fdebug_prefix_map_EQ Flags<[CC1Option,CC1AsOption]>, HelpText<"remap file source paths in debug info">; def ffile_prefix_map_EQ - : Joined<["-"], "ffile-prefix-map=">, Group, Flags<[CC1Option]>, + : Joined<["-"], "ffile-prefix-map=">, Group, HelpText<"remap file source paths in debug info and predefined preprocessor macros">; def fmacro_prefix_map_EQ : Joined<["-"], "fmacro-prefix-map=">, Group, Flags<[CC1Option]>, HelpText<"remap file source paths in predefined preprocessor macros">; def fforce_dwarf_frame : Flag<["-"], "fforce-dwarf-frame">, Group, Flags<[CC1Option]>, HelpText<"Always emit a debug frame section">; -def fno_force_dwarf_frame : Flag<["-"], "fno-force-dwarf-frame">, Group, Flags<[CC1Option]>, +def fno_force_dwarf_frame : Flag<["-"], "fno-force-dwarf-frame">, Group, HelpText<"Don't always emit a debug frame section">; def g_Flag : Flag<["-"], "g">, Group, HelpText<"Generate source-level debug information">; @@ -2106,9 +2103,9 @@ def gsplit_dwarf_EQ : Joined<["-"], "gsplit-dwarf=">, Group, HelpText<"Set DWARF fission mode to either 'split' or 'single'">, Values<"split,single">; def ggnu_pubnames : Flag<["-"], "ggnu-pubnames">, Group, Flags<[CC1Option]>; -def gno_gnu_pubnames : Flag<["-"], "gno-gnu-pubnames">, Group, Flags<[CC1Option]>; +def gno_gnu_pubnames : Flag<["-"], "gno-gnu-pubnames">, Group; def gpubnames : Flag<["-"], "gpubnames">, Group, Flags<[CC1Option]>; -def gno_pubnames : Flag<["-"], "gno-pubnames">, Group, Flags<[CC1Option]>; +def gno_pubnames : Flag<["-"], "gno-pubnames">, Group; def gdwarf_aranges : Flag<["-"], "gdwarf-aranges">, Group; def gmodules : Flag <["-"], "gmodules">, Group, HelpText<"Generate debug info with external references to clang modules" diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 6a988670eb02..b327fa902f67 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -766,9 +766,7 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, Opts.DebugExplicitImport = Args.hasArg(OPT_dwarf_explicit_import); Opts.DebugFwdTemplateParams = Args.hasArg(OPT_debug_forward_template_params); Opts.EmbedSource = Args.hasArg(OPT_gembed_source); - - Opts.ForceDwarfFrameSection = - Args.hasFlag(OPT_fforce_dwarf_frame, OPT_fno_force_dwarf_frame, false); + Opts.ForceDwarfFrameSection = Args.hasArg(OPT_fforce_dwarf_frame); for (const auto &Arg : Args.getAllArgValues(OPT_fdebug_prefix_map_EQ)) { auto Split = StringRef(Arg).split('='); diff --git a/clang/test/CodeGenObjCXX/return.mm b/clang/test/CodeGenObjCXX/return.mm index 53343e12b2f7..fb77f336dfc0 100644 --- a/clang/test/CodeGenObjCXX/return.mm +++ b/clang/test/CodeGenObjCXX/return.mm @@ -1,5 +1,6 @@ -// RUN: %clang_cc1 -emit-llvm -fblocks -triple x86_64-apple-darwin -fstrict-return -o - %s | FileCheck %s -// RUN: %clang_cc1 -emit-llvm -fblocks -triple x86_64-apple-darwin -fstrict-return -O -o - %s | FileCheck %s +/// -fstrict-return is the default. +// RUN: %clang_cc1 -emit-llvm -fblocks -triple x86_64-apple-darwin -o - %s | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -fblocks -triple x86_64-apple-darwin -O -o - %s | FileCheck %s @interface I @end -- GitLab From eeaabe64e3079d2847c0b94e398b5203ad2ab839 Mon Sep 17 00:00:00 2001 From: Ian Levesque Date: Tue, 21 Apr 2020 18:18:23 -0400 Subject: [PATCH 030/910] [xray] Use hidden symbol visibility for xray trampolines Summary: We load multiple copies of the trampolines into memory when instrumenting DSOs. Hidden visibility prevents conflicts in this scenario. Reviewers: MaskRay, dberris, johnislarry Subscribers: #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D78593 --- compiler-rt/lib/xray/xray_trampoline_AArch64.S | 3 +++ compiler-rt/lib/xray/xray_trampoline_arm.S | 3 +++ compiler-rt/lib/xray/xray_trampoline_x86_64.S | 6 ++++++ 3 files changed, 12 insertions(+) diff --git a/compiler-rt/lib/xray/xray_trampoline_AArch64.S b/compiler-rt/lib/xray/xray_trampoline_AArch64.S index 4d1b04fb7d90..8f8ab35ce2fb 100644 --- a/compiler-rt/lib/xray/xray_trampoline_AArch64.S +++ b/compiler-rt/lib/xray/xray_trampoline_AArch64.S @@ -7,6 +7,7 @@ .p2align 2 /* Let C/C++ see the symbol */ .global __xray_FunctionEntry + .hidden __xray_FunctionEntry .type __xray_FunctionEntry, %function /* In C++ it is void extern "C" __xray_FunctionEntry(uint32_t FuncId) with FuncId passed in W0 register. */ @@ -54,6 +55,7 @@ FunctionEntry_restore: .p2align 2 /* Let C/C++ see the symbol */ .global __xray_FunctionExit + .hidden __xray_FunctionExit .type __xray_FunctionExit, %function /* In C++ it is void extern "C" __xray_FunctionExit(uint32_t FuncId) with FuncId passed in W0 register. */ @@ -94,6 +96,7 @@ FunctionExit_restore: .p2align 2 /* Let C/C++ see the symbol */ .global __xray_FunctionTailExit + .hidden __xray_FunctionTailExit .type __xray_FunctionTailExit, %function /* In C++ it is void extern "C" __xray_FunctionTailExit(uint32_t FuncId) with FuncId passed in W0 register. */ diff --git a/compiler-rt/lib/xray/xray_trampoline_arm.S b/compiler-rt/lib/xray/xray_trampoline_arm.S index 71dbee65d825..528bc6c72fdd 100644 --- a/compiler-rt/lib/xray/xray_trampoline_arm.S +++ b/compiler-rt/lib/xray/xray_trampoline_arm.S @@ -10,6 +10,7 @@ .p2align 2 @ Let C/C++ see the symbol .global __xray_FunctionEntry + .hidden __xray_FunctionEntry @ It preserves all registers except r0, r12(ip), r14(lr) and r15(pc) @ Assume that "q" part of the floating-point registers is not used @ for passing parameters to C/C++ functions. @@ -40,6 +41,7 @@ FunctionEntry_restore: .p2align 2 @ Let C/C++ see the symbol .global __xray_FunctionExit + .hidden __xray_FunctionExit @ Assume that d1-d7 are not used for the return value. @ Assume that "q" part of the floating-point registers is not used for the @ return value in C/C++. @@ -71,6 +73,7 @@ FunctionExit_restore: .p2align 2 @ Let C/C++ see the symbol .global __xray_FunctionTailExit + .hidden __xray_FunctionTailExit @ It preserves all registers except r0, r12(ip), r14(lr) and r15(pc) @ Assume that "q" part of the floating-point registers is not used @ for passing parameters to C/C++ functions. diff --git a/compiler-rt/lib/xray/xray_trampoline_x86_64.S b/compiler-rt/lib/xray/xray_trampoline_x86_64.S index 1e58362cdc80..12c5a6ccd9a4 100644 --- a/compiler-rt/lib/xray/xray_trampoline_x86_64.S +++ b/compiler-rt/lib/xray/xray_trampoline_x86_64.S @@ -98,6 +98,7 @@ //===----------------------------------------------------------------------===// .globl ASM_SYMBOL(__xray_FunctionEntry) + ASM_HIDDEN(__xray_FunctionEntry) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_FunctionEntry) # LLVM-MCA-BEGIN __xray_FunctionEntry @@ -126,6 +127,7 @@ ASM_SYMBOL(__xray_FunctionEntry): //===----------------------------------------------------------------------===// .globl ASM_SYMBOL(__xray_FunctionExit) + ASM_HIDDEN(__xray_FunctionExit) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_FunctionExit) # LLVM-MCA-BEGIN __xray_FunctionExit @@ -166,6 +168,7 @@ ASM_SYMBOL(__xray_FunctionExit): //===----------------------------------------------------------------------===// .globl ASM_SYMBOL(__xray_FunctionTailExit) + ASM_HIDDEN(__xray_FunctionTailExit) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_FunctionTailExit) # LLVM-MCA-BEGIN __xray_FunctionTailExit @@ -192,6 +195,7 @@ ASM_SYMBOL(__xray_FunctionTailExit): //===----------------------------------------------------------------------===// .globl ASM_SYMBOL(__xray_ArgLoggerEntry) + ASM_HIDDEN(__xray_ArgLoggerEntry) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_ArgLoggerEntry) # LLVM-MCA-BEGIN __xray_ArgLoggerEntry @@ -231,6 +235,7 @@ ASM_SYMBOL(__xray_ArgLoggerEntry): //===----------------------------------------------------------------------===// .global ASM_SYMBOL(__xray_CustomEvent) + ASM_HIDDEN(__xray_CustomEvent) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_CustomEvent) # LLVM-MCA-BEGIN __xray_CustomEvent @@ -256,6 +261,7 @@ ASM_SYMBOL(__xray_CustomEvent): //===----------------------------------------------------------------------===// .global ASM_SYMBOL(__xray_TypedEvent) + ASM_HIDDEN(__xray_TypedEvent) .align 16, 0x90 ASM_TYPE_FUNCTION(__xray_TypedEvent) # LLVM-MCA-BEGIN __xray_TypedEvent -- GitLab From 5081468a669236fded73b2ca9fad2a8b8e6b7bf9 Mon Sep 17 00:00:00 2001 From: Ian Levesque Date: Tue, 21 Apr 2020 18:37:39 -0400 Subject: [PATCH 031/910] [xray] Avoid text relocations in trampolines for ARM/AArch64 Summary: Switch to pc-relative lookup of the xray handler function to avoid text relocations. Reviewers: MaskRay, dberris, johnislarry Subscribers: kristof.beyls, danielkiss, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D78595 --- compiler-rt/lib/xray/xray_trampoline_AArch64.S | 18 +++++++++--------- compiler-rt/lib/xray/xray_trampoline_arm.S | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/compiler-rt/lib/xray/xray_trampoline_AArch64.S b/compiler-rt/lib/xray/xray_trampoline_AArch64.S index 8f8ab35ce2fb..9dc862bb55f6 100644 --- a/compiler-rt/lib/xray/xray_trampoline_AArch64.S +++ b/compiler-rt/lib/xray/xray_trampoline_AArch64.S @@ -27,10 +27,10 @@ __xray_FunctionEntry: STP Q2, Q3, [SP, #-32]! STP Q4, Q5, [SP, #-32]! STP Q6, Q7, [SP, #-32]! - /* Load the address of _ZN6__xray19XRayPatchedFunctionE into X1 */ - LDR X1, =_ZN6__xray19XRayPatchedFunctionE + /* Load the page address of _ZN6__xray19XRayPatchedFunctionE into X1 */ + ADRP X1, _ZN6__xray19XRayPatchedFunctionE /* Load the handler function pointer into X2 */ - LDR X2, [X1] + LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE] /* Handler address is nullptr if handler is not set */ CMP X2, #0 BEQ FunctionEntry_restore @@ -72,10 +72,10 @@ __xray_FunctionExit: STP X5, X6, [SP, #-16]! STP X7, X30, [SP, #-16]! STR Q0, [SP, #-16]! - /* Load the address of _ZN6__xray19XRayPatchedFunctionE into X1 */ - LDR X1, =_ZN6__xray19XRayPatchedFunctionE + /* Load the page address of _ZN6__xray19XRayPatchedFunctionE into X1 */ + ADRP X1, _ZN6__xray19XRayPatchedFunctionE /* Load the handler function pointer into X2 */ - LDR X2, [X1] + LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE] /* Handler address is nullptr if handler is not set */ CMP X2, #0 BEQ FunctionExit_restore @@ -117,10 +117,10 @@ __xray_FunctionTailExit: STP Q2, Q3, [SP, #-32]! STP Q4, Q5, [SP, #-32]! STP Q6, Q7, [SP, #-32]! - /* Load the address of _ZN6__xray19XRayPatchedFunctionE into X1 */ - LDR X1, =_ZN6__xray19XRayPatchedFunctionE + /* Load the page address of _ZN6__xray19XRayPatchedFunctionE into X1 */ + ADRP X1, _ZN6__xray19XRayPatchedFunctionE /* Load the handler function pointer into X2 */ - LDR X2, [X1] + LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE] /* Handler address is nullptr if handler is not set */ CMP X2, #0 BEQ FunctionTailExit_restore diff --git a/compiler-rt/lib/xray/xray_trampoline_arm.S b/compiler-rt/lib/xray/xray_trampoline_arm.S index 528bc6c72fdd..3ffc1e443761 100644 --- a/compiler-rt/lib/xray/xray_trampoline_arm.S +++ b/compiler-rt/lib/xray/xray_trampoline_arm.S @@ -21,9 +21,9 @@ __xray_FunctionEntry: PUSH {r1-r3,lr} @ Save floating-point parameters of the instrumented function VPUSH {d0-d7} - MOVW r1,#:lower16:_ZN6__xray19XRayPatchedFunctionE - MOVT r1,#:upper16:_ZN6__xray19XRayPatchedFunctionE - LDR r2, [r1] + MOVW r1, #:lower16:_ZN6__xray19XRayPatchedFunctionE - (. + 16) + MOVT r1, #:upper16:_ZN6__xray19XRayPatchedFunctionE - (. + 12) + LDR r2, [pc, r1] @ Handler address is nullptr if handler is not set CMP r2, #0 BEQ FunctionEntry_restore @@ -53,9 +53,9 @@ __xray_FunctionExit: @ Save the floating-point return value of the instrumented function VPUSH {d0} @ Load the handler address - MOVW r1,#:lower16:_ZN6__xray19XRayPatchedFunctionE - MOVT r1,#:upper16:_ZN6__xray19XRayPatchedFunctionE - LDR r2, [r1] + MOVW r1, #:lower16:_ZN6__xray19XRayPatchedFunctionE - (. + 16) + MOVT r1, #:upper16:_ZN6__xray19XRayPatchedFunctionE - (. + 12) + LDR r2, [pc, r1] @ Handler address is nullptr if handler is not set CMP r2, #0 BEQ FunctionExit_restore @@ -84,9 +84,9 @@ __xray_FunctionTailExit: PUSH {r1-r3,lr} @ Save floating-point parameters of the instrumented function VPUSH {d0-d7} - MOVW r1,#:lower16:_ZN6__xray19XRayPatchedFunctionE - MOVT r1,#:upper16:_ZN6__xray19XRayPatchedFunctionE - LDR r2, [r1] + MOVW r1, #:lower16:_ZN6__xray19XRayPatchedFunctionE - (. + 16) + MOVT r1, #:upper16:_ZN6__xray19XRayPatchedFunctionE - (. + 12) + LDR r2, [pc, r1] @ Handler address is nullptr if handler is not set CMP r2, #0 BEQ FunctionTailExit_restore -- GitLab From 46a52ff9eda0750ff05311310774d954bcaf3408 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 21 Apr 2020 21:00:19 -0700 Subject: [PATCH 032/910] [TargetPassConfig] Run MachineVerifier after more passes. We were disabling verification for no reason in a bunch of places; just turn it on. At this point, there are two key places where we don't run verification: during register allocation, and after addPreEmitPass. Regalloc probably isn't worth messing with; it has its own invariants, and verifying afterwards is probably good enough. For after addPreEmitPass, it's probably worth investigating improvements. --- llvm/lib/CodeGen/TargetPassConfig.cpp | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 336b1a883cf2..4432c3fa8f1f 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -934,7 +934,7 @@ void TargetPassConfig::addMachinePasses() { } else { // If the target requests it, assign local variables to stack slots relative // to one another and simplify frame index references where possible. - addPass(&LocalStackSlotAllocationID, false); + addPass(&LocalStackSlotAllocationID); } if (TM->Options.EnableIPRA) @@ -1006,10 +1006,10 @@ void TargetPassConfig::addMachinePasses() { addBlockPlacement(); // Insert before XRay Instrumentation. - addPass(&FEntryInserterID, false); + addPass(&FEntryInserterID); - addPass(&XRayInstrumentationID, false); - addPass(&PatchableFunctionID, false); + addPass(&XRayInstrumentationID); + addPass(&PatchableFunctionID); addPreEmitPass(); @@ -1018,6 +1018,8 @@ void TargetPassConfig::addMachinePasses() { // clobbered registers, to be used to optimize call sites. addPass(createRegUsageInfoCollector()); + // FIXME: Some backends are incompatible with running the verifier after + // addPreEmitPass. Maybe only pass "false" here for those targets? addPass(&FuncletLayoutID, false); addPass(&StackMapLivenessID, false); @@ -1048,15 +1050,15 @@ void TargetPassConfig::addMachineSSAOptimization() { // Optimize PHIs before DCE: removing dead PHI cycles may make more // instructions dead. - addPass(&OptimizePHIsID, false); + addPass(&OptimizePHIsID); // This pass merges large allocas. StackSlotColoring is a different pass // which merges spill slots. - addPass(&StackColoringID, false); + addPass(&StackColoringID); // If the target requests it, assign local variables to stack slots relative // to one another and simplify frame index references where possible. - addPass(&LocalStackSlotAllocationID, false); + addPass(&LocalStackSlotAllocationID); // With optimization, dead code should already be eliminated. However // there is one known exception: lowered code for arguments that are only @@ -1069,8 +1071,8 @@ void TargetPassConfig::addMachineSSAOptimization() { // loop info, just like LICM and CSE below. addILPOpts(); - addPass(&EarlyMachineLICMID, false); - addPass(&MachineCSEID, false); + addPass(&EarlyMachineLICMID); + addPass(&MachineCSEID); addPass(&MachineSinkingID); -- GitLab From 8dc790b9331eab1ba632aa7329d096db295d3348 Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Wed, 22 Apr 2020 00:31:59 +0000 Subject: [PATCH 033/910] Add `//` before the banner displayed in `--print-ir-before/after-all` This is making the output file (when the stream is a file) a valid MLIR file. Differential Revision: https://reviews.llvm.org/D78604 --- mlir/lib/Pass/IRPrinting.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mlir/lib/Pass/IRPrinting.cpp b/mlir/lib/Pass/IRPrinting.cpp index b1792c497620..3398005d8bfa 100644 --- a/mlir/lib/Pass/IRPrinting.cpp +++ b/mlir/lib/Pass/IRPrinting.cpp @@ -141,7 +141,7 @@ void IRPrinterInstrumentation::runBeforePass(Pass *pass, Operation *op) { beforePassFingerPrints.try_emplace(pass, op); config->printBeforeIfEnabled(pass, op, [&](raw_ostream &out) { - out << formatv("*** IR Dump Before {0} ***", pass->getName()); + out << formatv("// *** IR Dump Before {0} ***", pass->getName()); printIR(op, config->shouldPrintAtModuleScope(), out, OpPrintingFlags()); out << "\n\n"; }); @@ -165,7 +165,7 @@ void IRPrinterInstrumentation::runAfterPass(Pass *pass, Operation *op) { } config->printAfterIfEnabled(pass, op, [&](raw_ostream &out) { - out << formatv("*** IR Dump After {0} ***", pass->getName()); + out << formatv("// *** IR Dump After {0} ***", pass->getName()); printIR(op, config->shouldPrintAtModuleScope(), out, OpPrintingFlags()); out << "\n\n"; }); @@ -178,7 +178,7 @@ void IRPrinterInstrumentation::runAfterPassFailed(Pass *pass, Operation *op) { beforePassFingerPrints.erase(pass); config->printAfterIfEnabled(pass, op, [&](raw_ostream &out) { - out << formatv("*** IR Dump After {0} Failed ***", pass->getName()); + out << formatv("// *** IR Dump After {0} Failed ***", pass->getName()); printIR(op, config->shouldPrintAtModuleScope(), out, OpPrintingFlags().printGenericOpForm()); out << "\n\n"; -- GitLab From 1f48e22df8027b6884b94981303d913e0c00f149 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Wed, 22 Apr 2020 12:11:17 +0700 Subject: [PATCH 034/910] [DebugInfo] Simplify DWARFUnit::determineStringOffsetsTableContribution(). NFC. The method is called from only one place and the call is already guarded by a condition which checks that IsDWO is false. Differential Revision: https://reviews.llvm.org/D78482 --- llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp b/llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp index 30eb0174fc9c..fb24576620f4 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp @@ -962,18 +962,12 @@ parseDWARFStringOffsetsTableHeader(DWARFDataExtractor &DA, Expected> DWARFUnit::determineStringOffsetsTableContribution(DWARFDataExtractor &DA) { - uint64_t Offset; - if (IsDWO) { - Offset = 0; - if (DA.getData().data() == nullptr) - return None; - } else { - auto OptOffset = toSectionOffset(getUnitDIE().find(DW_AT_str_offsets_base)); - if (!OptOffset) - return None; - Offset = *OptOffset; - } - auto DescOrError = parseDWARFStringOffsetsTableHeader(DA, Header.getFormat(), Offset); + assert(!IsDWO); + auto OptOffset = toSectionOffset(getUnitDIE().find(DW_AT_str_offsets_base)); + if (!OptOffset) + return None; + auto DescOrError = + parseDWARFStringOffsetsTableHeader(DA, Header.getFormat(), *OptOffset); if (!DescOrError) return DescOrError.takeError(); return *DescOrError; @@ -981,6 +975,7 @@ DWARFUnit::determineStringOffsetsTableContribution(DWARFDataExtractor &DA) { Expected> DWARFUnit::determineStringOffsetsTableContributionDWO(DWARFDataExtractor & DA) { + assert(IsDWO); uint64_t Offset = 0; auto IndexEntry = Header.getIndexEntry(); const auto *C = -- GitLab From c08af2c11ad1f3bedef4a2dd307d98e162f19f4e Mon Sep 17 00:00:00 2001 From: Siva Chandra Reddy Date: Tue, 21 Apr 2020 09:58:12 -0700 Subject: [PATCH 035/910] [libc][NFC] Cleanup dependencies in src/signal and test/src/signal. Reviewers: abrachet Differential Revision: https://reviews.llvm.org/D78585 --- libc/src/signal/linux/CMakeLists.txt | 2 +- libc/test/src/signal/CMakeLists.txt | 16 ++++++---------- libc/test/src/signal/sigaddset_test.cpp | 1 - 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/libc/src/signal/linux/CMakeLists.txt b/libc/src/signal/linux/CMakeLists.txt index 47442f6a1b6f..fc4a7aa32bf2 100644 --- a/libc/src/signal/linux/CMakeLists.txt +++ b/libc/src/signal/linux/CMakeLists.txt @@ -38,10 +38,10 @@ add_entrypoint_object( ../sigaction.h DEPENDS .__restore - .raise libc.config.linux.linux_syscall_h libc.include.signal libc.include.sys_syscall + libc.src.errno.__errno_location ) add_entrypoint_object( diff --git a/libc/test/src/signal/CMakeLists.txt b/libc/test/src/signal/CMakeLists.txt index 2a9dce860f6e..b5c1281b8102 100644 --- a/libc/test/src/signal/CMakeLists.txt +++ b/libc/test/src/signal/CMakeLists.txt @@ -18,11 +18,10 @@ add_libc_unittest( SRCS sigaction_test.cpp DEPENDS - libc.src.signal.sigaction - libc.src.signal.raise - libc.include.signal libc.include.errno - libc.src.errno.__errno_location + libc.include.signal + libc.src.signal.raise + libc.src.signal.sigaction ) add_libc_unittest( @@ -32,12 +31,12 @@ add_libc_unittest( SRCS sigprocmask_test.cpp DEPENDS - libc.include.signal + libc.include.errno libc.src.errno.__errno_location libc.src.signal.raise - libc.src.signal.sigprocmask libc.src.signal.sigaddset libc.src.signal.sigemptyset + libc.src.signal.sigprocmask ) add_libc_unittest( @@ -47,8 +46,8 @@ add_libc_unittest( SRCS sigaddset_test.cpp DEPENDS + libc.include.errno libc.include.signal - libc.src.errno.__errno_location libc.src.signal.sigaddset ) @@ -63,7 +62,6 @@ add_libc_unittest( libc.include.signal libc.src.errno.__errno_location libc.src.signal.raise - libc.src.signal.sigaction libc.src.signal.signal ) @@ -76,7 +74,6 @@ add_libc_unittest( DEPENDS libc.include.errno libc.include.signal - libc.src.errno.__errno_location libc.src.signal.raise libc.src.signal.sigfillset libc.src.signal.sigprocmask @@ -91,7 +88,6 @@ add_libc_unittest( DEPENDS libc.include.errno libc.include.signal - libc.src.errno.__errno_location libc.src.signal.raise libc.src.signal.sigdelset libc.src.signal.sigfillset diff --git a/libc/test/src/signal/sigaddset_test.cpp b/libc/test/src/signal/sigaddset_test.cpp index d0e67ea01e95..f106edb57f90 100644 --- a/libc/test/src/signal/sigaddset_test.cpp +++ b/libc/test/src/signal/sigaddset_test.cpp @@ -8,7 +8,6 @@ #include "include/errno.h" #include "include/signal.h" -#include "src/errno/llvmlibc_errno.h" #include "src/signal/sigaddset.h" #include "utils/UnitTest/ErrnoSetterMatcher.h" -- GitLab From daadb4855399f27c8e5af18c3ae51169df4c6d5a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 21 Apr 2020 00:55:35 -0700 Subject: [PATCH 036/910] [CallSite removal][TargetTransformInfoImpl] Replace CallSite with CallBase. NFC --- llvm/include/llvm/Analysis/TargetTransformInfoImpl.h | 7 +++---- llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp | 3 +-- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 1cf625e60d3f..773608fa84c8 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -17,7 +17,6 @@ #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/VectorUtils.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Function.h" #include "llvm/IR/GetElementPtrTypeIterator.h" @@ -796,8 +795,8 @@ public: unsigned getUserCost(const User *U, ArrayRef Operands) { auto *TargetTTI = static_cast(this); - if (auto CS = ImmutableCallSite(U)) { - const Function *F = CS.getCalledFunction(); + if (const auto *CB = dyn_cast(U)) { + const Function *F = CB->getCalledFunction(); if (F) { FunctionType *FTy = F->getFunctionType(); if (Intrinsic::ID IID = F->getIntrinsicID()) { @@ -811,7 +810,7 @@ public: return TTI::TCC_Basic * (FTy->getNumParams() + 1); } - return TTI::TCC_Basic * (CS.arg_size() + 1); + return TTI::TCC_Basic * (CB->arg_size() + 1); } Type *Ty = U->getType(); diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index d597dcf79517..32a28c5f4e67 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -246,8 +246,7 @@ void SystemZTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, for (auto &BB : L->blocks()) for (auto &I : *BB) { if (isa(&I) || isa(&I)) { - ImmutableCallSite CS(&I); - if (const Function *F = CS.getCalledFunction()) { + if (const Function *F = cast(I).getCalledFunction()) { if (isLoweredToCall(F)) HasCall = true; if (F->getIntrinsicID() == Intrinsic::memcpy || -- GitLab From c12722cde83212581d14a6fdd6a52ebed04ac4df Mon Sep 17 00:00:00 2001 From: Qiu Chaofan Date: Fri, 17 Apr 2020 15:08:58 +0800 Subject: [PATCH 037/910] [PowerPC] Exploit RLDIMI for OR with large immediates This patch exploits rldimi instruction for patterns like `or %a, 0b000011110000`, which saves number of instructions when the operand has only one use, compared with `li-ori-sldi-or`. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D77850 --- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 31 +++++++++++++++++++++ llvm/test/CodeGen/PowerPC/ori_imm32.ll | 5 ++-- llvm/test/CodeGen/PowerPC/ori_imm64.ll | 28 ++++++++++++++----- 3 files changed, 54 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index dd6d9249ab4d..8a5603dc274a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -352,6 +352,7 @@ private: bool tryAsSingleRLWINM8(SDNode *N); bool tryAsSingleRLWIMI(SDNode *N); bool tryAsPairOfRLDICL(SDNode *N); + bool tryAsSingleRLDIMI(SDNode *N); void PeepholePPC64(); void PeepholePPC64ZExt(); @@ -4597,6 +4598,31 @@ bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) { return true; } +bool PPCDAGToDAGISel::tryAsSingleRLDIMI(SDNode *N) { + assert(N->getOpcode() == ISD::OR && "ISD::OR SDNode expected"); + uint64_t Imm64; + unsigned MB, ME; + SDValue N0 = N->getOperand(0); + + // We won't get fewer instructions if the imm is 32-bit integer. + // rldimi requires the imm to have consecutive ones with both sides zero. + // Also, make sure the first Op has only one use, otherwise this may increase + // register pressure since rldimi is destructive. + if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || + isUInt<32>(Imm64) || !isRunOfOnes64(Imm64, MB, ME) || !N0.hasOneUse()) + return false; + + unsigned SH = 63 - ME; + SDLoc Dl(N); + // Use select64Imm for making LI instr instead of directly putting Imm64 + SDValue Ops[] = { + N->getOperand(0), + SDValue(selectI64Imm(CurDAG, getI64Imm(-1, Dl).getNode()), 0), + getI32Imm(SH, Dl), getI32Imm(MB, Dl)}; + CurDAG->SelectNodeTo(N, PPC::RLDIMI, MVT::i64, Ops); + return true; +} + // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. void PPCDAGToDAGISel::Select(SDNode *N) { @@ -4844,6 +4870,11 @@ void PPCDAGToDAGISel::Select(SDNode *N) { } } + // If this is 'or' against an imm with consecutive ones and both sides zero, + // try to emit rldimi + if (tryAsSingleRLDIMI(N)) + return; + // OR with a 32-bit immediate can be handled by ori + oris // without creating an immediate in a GPR. uint64_t Imm64 = 0; diff --git a/llvm/test/CodeGen/PowerPC/ori_imm32.ll b/llvm/test/CodeGen/PowerPC/ori_imm32.ll index 245c9bdbce77..3077c4e0fe35 100644 --- a/llvm/test/CodeGen/PowerPC/ori_imm32.ll +++ b/llvm/test/CodeGen/PowerPC/ori_imm32.ll @@ -16,9 +16,8 @@ entry: define i64 @ori_test_b(i64 %a) { ; CHECK-LABEL: ori_test_b: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: li 4, 1 -; CHECK-NEXT: sldi 4, 4, 32 -; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: li 4, -1 +; CHECK-NEXT: rldimi 3, 4, 32, 31 ; CHECK-NEXT: blr entry: %or = or i64 %a, 4294967296 diff --git a/llvm/test/CodeGen/PowerPC/ori_imm64.ll b/llvm/test/CodeGen/PowerPC/ori_imm64.ll index d2ea911c6f14..b1bb42e3f805 100644 --- a/llvm/test/CodeGen/PowerPC/ori_imm64.ll +++ b/llvm/test/CodeGen/PowerPC/ori_imm64.ll @@ -15,10 +15,8 @@ entry: define i64 @ori_test_2(i64 %a) { ; CHECK-LABEL: ori_test_2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lis 4, 15 -; CHECK-NEXT: ori 4, 4, 65535 -; CHECK-NEXT: sldi 4, 4, 29 -; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: li 4, -1 +; CHECK-NEXT: rldimi 3, 4, 29, 15 ; CHECK-NEXT: blr entry: %or = or i64 %a, 562949416550400 ; 0x1ffffe0000000 @@ -28,9 +26,8 @@ entry: define i64 @ori_test_3(i64 %a) { ; CHECK-LABEL: ori_test_3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lis 4, -32768 -; CHECK-NEXT: rldicr 4, 4, 36, 63 -; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: li 4, -1 +; CHECK-NEXT: rldimi 3, 4, 3, 28 ; CHECK-NEXT: blr entry: %or = or i64 %a, 68719476728 ; 0xffffffff8 @@ -50,3 +47,20 @@ entry: %or = or i64 %a, 17661175070719 ; 0x10101010ffff ret i64 %or } + +; Don't exploit rldimi if operand has multiple uses +define i64 @test_test_5(i64 %a, i64 %b) { +; CHECK-LABEL: test_test_5: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li 5, 1 +; CHECK-NEXT: sldi 5, 5, 32 +; CHECK-NEXT: or 5, 3, 5 +; CHECK-NEXT: add 4, 5, 4 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: blr +entry: + %or = or i64 %a, 4294967296 + %add = add i64 %or, %b + %div = sub i64 %a, %add + ret i64 %div +} -- GitLab From d22989c34ede9ebe1cdb52c30407d35a1d117f2e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 21 Apr 2020 23:29:17 -0700 Subject: [PATCH 038/910] [CallSite removal][Target] Replace CallSite with CallBase. NFC In some cases just delete an unneeded include. --- llvm/lib/Target/ARM/ARMFastISel.cpp | 37 +++++++++---------- .../lib/Target/ARM/ARMTargetTransformInfo.cpp | 4 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 1 - llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 - .../WebAssemblyLowerEmscriptenEHSjLj.cpp | 1 - 5 files changed, 18 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 11bff747837c..0939d890f36b 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -48,7 +48,6 @@ #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" @@ -2298,12 +2297,11 @@ bool ARMFastISel::SelectCall(const Instruction *I, if (CI->isTailCall()) return false; // Check the calling convention. - ImmutableCallSite CS(CI); - CallingConv::ID CC = CS.getCallingConv(); + CallingConv::ID CC = CI->getCallingConv(); // TODO: Avoid some calling conventions? - FunctionType *FTy = CS.getFunctionType(); + FunctionType *FTy = CI->getFunctionType(); bool isVarArg = FTy->isVarArg(); // Handle *simple* calls for now. @@ -2330,47 +2328,46 @@ bool ARMFastISel::SelectCall(const Instruction *I, SmallVector ArgRegs; SmallVector ArgVTs; SmallVector ArgFlags; - unsigned arg_size = CS.arg_size(); + unsigned arg_size = CI->arg_size(); Args.reserve(arg_size); ArgRegs.reserve(arg_size); ArgVTs.reserve(arg_size); ArgFlags.reserve(arg_size); - for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); - i != e; ++i) { + for (auto ArgI = CI->arg_begin(), ArgE = CI->arg_end(); ArgI != ArgE; ++ArgI) { // If we're lowering a memory intrinsic instead of a regular call, skip the // last argument, which shouldn't be passed to the underlying function. - if (IntrMemName && e - i <= 1) + if (IntrMemName && ArgE - ArgI <= 1) break; ISD::ArgFlagsTy Flags; - unsigned ArgIdx = i - CS.arg_begin(); - if (CS.paramHasAttr(ArgIdx, Attribute::SExt)) + unsigned ArgIdx = ArgI - CI->arg_begin(); + if (CI->paramHasAttr(ArgIdx, Attribute::SExt)) Flags.setSExt(); - if (CS.paramHasAttr(ArgIdx, Attribute::ZExt)) + if (CI->paramHasAttr(ArgIdx, Attribute::ZExt)) Flags.setZExt(); // FIXME: Only handle *easy* calls for now. - if (CS.paramHasAttr(ArgIdx, Attribute::InReg) || - CS.paramHasAttr(ArgIdx, Attribute::StructRet) || - CS.paramHasAttr(ArgIdx, Attribute::SwiftSelf) || - CS.paramHasAttr(ArgIdx, Attribute::SwiftError) || - CS.paramHasAttr(ArgIdx, Attribute::Nest) || - CS.paramHasAttr(ArgIdx, Attribute::ByVal)) + if (CI->paramHasAttr(ArgIdx, Attribute::InReg) || + CI->paramHasAttr(ArgIdx, Attribute::StructRet) || + CI->paramHasAttr(ArgIdx, Attribute::SwiftSelf) || + CI->paramHasAttr(ArgIdx, Attribute::SwiftError) || + CI->paramHasAttr(ArgIdx, Attribute::Nest) || + CI->paramHasAttr(ArgIdx, Attribute::ByVal)) return false; - Type *ArgTy = (*i)->getType(); + Type *ArgTy = (*ArgI)->getType(); MVT ArgVT; if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && ArgVT != MVT::i1) return false; - Register Arg = getRegForValue(*i); + Register Arg = getRegForValue(*ArgI); if (!Arg.isValid()) return false; Flags.setOrigAlign(Align(DL.getABITypeAlignment(ArgTy))); - Args.push_back(*i); + Args.push_back(*ArgI); ArgRegs.push_back(Arg); ArgVTs.push_back(ArgVT); ArgFlags.push_back(Flags); diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 34d819696e1a..bab6d224b84d 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -16,7 +16,6 @@ #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Instruction.h" @@ -1354,8 +1353,7 @@ void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, return; if (isa(I) || isa(I)) { - ImmutableCallSite CS(&I); - if (const Function *F = CS.getCalledFunction()) { + if (const Function *F = cast(I).getCalledFunction()) { if (!isLoweredToCall(F)) continue; } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 472625290d40..1fbbed770c5c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -31,7 +31,6 @@ #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 22f148e4b745..3c3a144a9b98 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -55,7 +55,6 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp index b35652898c3b..be4fe0b31226 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp @@ -208,7 +208,6 @@ ///===----------------------------------------------------------------------===// #include "WebAssembly.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/IRBuilder.h" -- GitLab From f20ff4b17d1927eeffadf3f2fdb1cd6401d94890 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 21 Apr 2020 11:13:20 -0500 Subject: [PATCH 039/910] [Attributor] Run IRPosition::verify only with EXPENSIVE_CHECKS --- llvm/lib/Transforms/IPO/Attributor.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index e715d04c0d1e..ba08061be9d3 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -400,6 +400,7 @@ bool IRPosition::getAttrsFromAssumes(Attribute::AttrKind AK, } void IRPosition::verify() { +#ifdef EXPENSIVE_CHECKS switch (KindOrArgNo) { default: assert(KindOrArgNo >= 0 && "Expected argument or call site argument!"); @@ -447,6 +448,7 @@ void IRPosition::verify() { assert(AnchorVal == &getAssociatedValue() && "Associated value mismatch!"); break; } +#endif } Optional -- GitLab From ca59ff5af9dac8238ef5eadaadcf7994516d95d8 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 17 Apr 2020 20:47:38 -0500 Subject: [PATCH 040/910] [Attributor] Replace AccessKind2Accesses map with an "array map" The number of different access location kinds we track is relatively small (8 so far). With this patch we replace the DenseMap that mapped from index (0-7) to the access set pointer with an array of access set pointers. This reduces memory consumption. No functional change is intended. --- Single run of the Attributor module and then CGSCC pass (oldPM) for SPASS/clause.c (~10k LLVM-IR loc): Before: ``` calls to allocation functions: 472499 (215654/s) temporary memory allocations: 77794 (35506/s) peak heap memory consumption: 35.28MB peak RSS (including heaptrack overhead): 125.46MB total memory leaked: 269.04KB ``` After: ``` calls to allocation functions: 472270 (308673/s) temporary memory allocations: 77578 (50704/s) peak heap memory consumption: 32.70MB peak RSS (including heaptrack overhead): 121.78MB total memory leaked: 269.04KB ``` Difference: ``` calls to allocation functions: -229 (346/s) temporary memory allocations: -216 (326/s) peak heap memory consumption: -2.58MB peak RSS (including heaptrack overhead): 0B total memory leaked: 0B ``` --- --- .../Transforms/IPO/AttributorAttributes.cpp | 23 +++++++++++-------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 1052dda05f47..4210e4681cf5 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -6010,13 +6010,17 @@ std::string AAMemoryLocation::getMemoryLocationsAsStr( struct AAMemoryLocationImpl : public AAMemoryLocation { AAMemoryLocationImpl(const IRPosition &IRP, Attributor &A) - : AAMemoryLocation(IRP, A), Allocator(A.Allocator) {} + : AAMemoryLocation(IRP, A), Allocator(A.Allocator) { + for (unsigned u = 0; u < llvm::CTLog2(); ++u) + AccessKind2Accesses[u] = nullptr; + } ~AAMemoryLocationImpl() { // The AccessSets are allocated via a BumpPtrAllocator, we call // the destructor manually. - for (auto &It : AccessKind2Accesses) - It.getSecond()->~AccessSet(); + for (unsigned u = 0; u < llvm::CTLog2(); ++u) + if (AccessKind2Accesses[u]) + AccessKind2Accesses[u]->~AccessSet(); } /// See AbstractAttribute::initialize(...). @@ -6106,11 +6110,13 @@ struct AAMemoryLocationImpl : public AAMemoryLocation { if (AssumedMLK == NO_LOCATIONS) return true; - for (MemoryLocationsKind CurMLK = 1; CurMLK < NO_LOCATIONS; CurMLK *= 2) { + unsigned Idx = 0; + for (MemoryLocationsKind CurMLK = 1; CurMLK < NO_LOCATIONS; + CurMLK *= 2, ++Idx) { if (CurMLK & RequestedMLK) continue; - if (const AccessSet *Accesses = AccessKind2Accesses.lookup(CurMLK)) + if (const AccessSet *Accesses = AccessKind2Accesses[Idx]) for (const AccessInfo &AI : *Accesses) if (!Pred(AI.I, AI.Ptr, AI.Kind, CurMLK)) return false; @@ -6163,9 +6169,8 @@ protected: /// Mapping from *single* memory location kinds, e.g., LOCAL_MEM with the /// value of NO_LOCAL_MEM, to the accesses encountered for this memory kind. - using AccessSet = SmallSet; - using AccessKind2AccessSetTy = DenseMap; - AccessKind2AccessSetTy AccessKind2Accesses; + using AccessSet = SmallSet; + AccessSet *AccessKind2Accesses[llvm::CTLog2()]; /// Return the kind(s) of location that may be accessed by \p V. AAMemoryLocation::MemoryLocationsKind @@ -6185,7 +6190,7 @@ protected: } assert(isPowerOf2_32(MLK) && "Expected a single location set!"); - auto *&Accesses = AccessKind2Accesses[MLK]; + auto *&Accesses = AccessKind2Accesses[llvm::Log2_32(MLK)]; if (!Accesses) Accesses = new (Allocator) AccessSet(); Changed |= Accesses->insert(AccessInfo{I, Ptr, Kind}).second; -- GitLab From 84e4c09995a779d5057e2ce831ced9307a8164af Mon Sep 17 00:00:00 2001 From: Alexander Belyaev Date: Tue, 21 Apr 2020 16:00:28 +0200 Subject: [PATCH 041/910] [MLIR] Update documentation for loop.parallel. Differential Revision: https://reviews.llvm.org/D78562 --- mlir/include/mlir/Dialect/LoopOps/LoopOps.td | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td index 4548f5aae2e8..856725747369 100644 --- a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td +++ b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td @@ -294,9 +294,10 @@ def ParallelOp : Loop_Op<"parallel", Example: ```mlir - loop.parallel (%iv) = (%lb) to (%ub) step (%step) -> f32 { - %zero = constant 0.0 : f32 - loop.reduce(%zero) : f32 { + %init = constant 0.0 : f32 + loop.parallel (%iv) = (%lb) to (%ub) step (%step) init (%init) -> f32 { + %elem_to_reduce = load %buffer[%iv] : memref<100xf32> + loop.reduce(%elem_to_reduce) : f32 { ^bb0(%lhs : f32, %rhs: f32): %res = addf %lhs, %rhs : f32 loop.reduce.return %res : f32 -- GitLab From c22876b550f5905b1cb7a4a0f329e76fac3e0232 Mon Sep 17 00:00:00 2001 From: Stephan Herhut Date: Tue, 21 Apr 2020 21:21:37 +0200 Subject: [PATCH 042/910] [MLIR] Add extra locking during cubin generation. We also need to lock the LLVMDialect mutex when initializing LLVM targets or destroying llvm modules concurrently. Added another scoped lock to that effect. Differential Revision: https://reviews.llvm.org/D78580 --- mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp b/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp index 7cdb0dda4454..3f99c56c4716 100644 --- a/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp +++ b/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp @@ -31,6 +31,7 @@ #include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/Module.h" #include "llvm/Support/Error.h" +#include "llvm/Support/Mutex.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Target/TargetMachine.h" @@ -57,6 +58,12 @@ public: void runOnOperation() override { gpu::GPUModuleOp module = getOperation(); + // Lock access to the llvm context. + llvm::sys::SmartScopedLock scopedLock( + module.getContext() + ->getRegisteredDialect() + ->getLLVMContextMutex()); + // Make sure the NVPTX target is initialized. LLVMInitializeNVPTXTarget(); LLVMInitializeNVPTXTargetInfo(); -- GitLab From 146d52e732877d9d74b81b7559fe6a7647351d52 Mon Sep 17 00:00:00 2001 From: Alexander Belyaev Date: Wed, 22 Apr 2020 09:02:00 +0200 Subject: [PATCH 043/910] [MLIR] Verify there are no side-effecting ops in GenericAtomicRMWOp body. Differential Revision: https://reviews.llvm.org/D78559 --- mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 3 ++- mlir/lib/Dialect/StandardOps/IR/Ops.cpp | 13 ++++++++++++- mlir/test/IR/invalid-ops.mlir | 12 ++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td index 38cb8dcb3d55..e5a1af544e09 100644 --- a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td +++ b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td @@ -499,7 +499,8 @@ def GenericAtomicRMWOp : Std_Op<"generic_atomic_rmw", [ The result represents the latest value that was stored. The region contains the code for the modification itself. The entry block has a single argument that represents the value stored in `memref[indices]` before the write is - performed. + performed. No side-effecting ops are allowed in the body of + `GenericAtomicRMWOp`. Example: diff --git a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp index 9ac2f4ba35e4..0a96c9a5bf44 100644 --- a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp +++ b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp @@ -507,7 +507,18 @@ static LogicalResult verify(GenericAtomicRMWOp op) { if (op.getResult().getType() != block.getArgument(0).getType()) return op.emitOpError( "expected block argument of the same type result type"); - return success(); + + bool hasSideEffects = + op.body() + .walk([&](Operation *nestedOp) { + if (MemoryEffectOpInterface::hasNoEffect(nestedOp)) + return WalkResult::advance(); + nestedOp->emitError("body of 'generic_atomic_rmw' should contain " + "only operations with no side effects"); + return WalkResult::interrupt(); + }) + .wasInterrupted(); + return hasSideEffects ? failure() : success(); } static ParseResult parseGenericAtomicRMWOp(OpAsmParser &parser, diff --git a/mlir/test/IR/invalid-ops.mlir b/mlir/test/IR/invalid-ops.mlir index 17eaded116e6..fe2556d0a9d9 100644 --- a/mlir/test/IR/invalid-ops.mlir +++ b/mlir/test/IR/invalid-ops.mlir @@ -1179,6 +1179,18 @@ func @generic_atomic_rmw_result_type_mismatch(%I: memref<10xf32>, %i : index) { // ----- +func @generic_atomic_rmw_has_side_effects(%I: memref<10xf32>, %i : index) { + // expected-error@+4 {{should contain only operations with no side effects}} + %x = generic_atomic_rmw %I[%i] : memref<10xf32> { + ^bb0(%old_value : f32): + %c1 = constant 1.0 : f32 + %buf = alloc() : memref<2048xf32> + atomic_yield %c1 : f32 + } +} + +// ----- + func @atomic_yield_type_mismatch(%I: memref<10xf32>, %i : index) { // expected-error@+4 {{op types mismatch between yield op: 'i32' and its parent: 'f32'}} %x = generic_atomic_rmw %I[%i] : memref<10xf32> { -- GitLab From 05a11974ae9f8fc03b7cc8d679031ebba8e6a12b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 22 Apr 2020 00:03:59 -0700 Subject: [PATCH 044/910] [CallSite removal] Remove unneeded includes of CallSite.h. NFC --- llvm/include/llvm/Analysis/PtrUseVisitor.h | 1 - llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp | 1 - llvm/lib/Analysis/MemDerefPrinter.cpp | 1 - llvm/lib/Analysis/ProfileSummaryInfo.cpp | 2 +- llvm/lib/Analysis/SyntheticCountsUtils.cpp | 1 - llvm/lib/Analysis/TargetTransformInfo.cpp | 1 - llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 1 - llvm/lib/ExecutionEngine/Interpreter/Interpreter.h | 1 - llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp | 1 - llvm/lib/Transforms/Coroutines/Coroutines.cpp | 1 - llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 1 - llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp | 1 - llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp | 1 - llvm/lib/Transforms/ObjCARC/ObjCARC.h | 1 - llvm/lib/Transforms/Scalar/GVN.cpp | 1 - llvm/lib/Transforms/Utils/EscapeEnumerator.cpp | 1 - llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 1 - llvm/unittests/Analysis/AssumeBundleQueriesTest.cpp | 1 - 18 files changed, 1 insertion(+), 18 deletions(-) diff --git a/llvm/include/llvm/Analysis/PtrUseVisitor.h b/llvm/include/llvm/Analysis/PtrUseVisitor.h index f67bdba5748c..78e9251da627 100644 --- a/llvm/include/llvm/Analysis/PtrUseVisitor.h +++ b/llvm/include/llvm/Analysis/PtrUseVisitor.h @@ -26,7 +26,6 @@ #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/InstVisitor.h" diff --git a/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp b/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp index dc4cbc371ef4..c32aa0340ceb 100644 --- a/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp +++ b/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp @@ -15,7 +15,6 @@ #include "llvm/Analysis/IndirectCallPromotionAnalysis.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/IndirectCallVisitor.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/InstIterator.h" #include "llvm/IR/InstVisitor.h" #include "llvm/IR/Instructions.h" diff --git a/llvm/lib/Analysis/MemDerefPrinter.cpp b/llvm/lib/Analysis/MemDerefPrinter.cpp index 5d824067df53..f8f4f9423f62 100644 --- a/llvm/lib/Analysis/MemDerefPrinter.cpp +++ b/llvm/lib/Analysis/MemDerefPrinter.cpp @@ -8,7 +8,6 @@ #include "llvm/Analysis/Loads.h" #include "llvm/Analysis/Passes.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/InstIterator.h" #include "llvm/IR/LLVMContext.h" diff --git a/llvm/lib/Analysis/ProfileSummaryInfo.cpp b/llvm/lib/Analysis/ProfileSummaryInfo.cpp index 919cda7cf1af..1ef1758d55a4 100644 --- a/llvm/lib/Analysis/ProfileSummaryInfo.cpp +++ b/llvm/lib/Analysis/ProfileSummaryInfo.cpp @@ -14,7 +14,7 @@ #include "llvm/Analysis/ProfileSummaryInfo.h" #include "llvm/Analysis/BlockFrequencyInfo.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/IR/ProfileSummary.h" diff --git a/llvm/lib/Analysis/SyntheticCountsUtils.cpp b/llvm/lib/Analysis/SyntheticCountsUtils.cpp index 22766e5f07f5..a3edce76cd88 100644 --- a/llvm/lib/Analysis/SyntheticCountsUtils.cpp +++ b/llvm/lib/Analysis/SyntheticCountsUtils.cpp @@ -14,7 +14,6 @@ #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/Analysis/CallGraph.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Function.h" #include "llvm/IR/InstIterator.h" #include "llvm/IR/Instructions.h" diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 996b9310f8cd..92862fef5934 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -11,7 +11,6 @@ #include "llvm/Analysis/LoopIterator.h" #include "llvm/Analysis/TargetTransformInfoImpl.h" #include "llvm/IR/CFG.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index a05b375d5279..38195e412623 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -69,7 +69,6 @@ #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/CFG.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Constant.h" #include "llvm/IR/ConstantRange.h" diff --git a/llvm/lib/ExecutionEngine/Interpreter/Interpreter.h b/llvm/lib/ExecutionEngine/Interpreter/Interpreter.h index cb0969d852f7..fd7fa21df196 100644 --- a/llvm/lib/ExecutionEngine/Interpreter/Interpreter.h +++ b/llvm/lib/ExecutionEngine/Interpreter/Interpreter.h @@ -15,7 +15,6 @@ #include "llvm/ExecutionEngine/ExecutionEngine.h" #include "llvm/ExecutionEngine/GenericValue.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Function.h" #include "llvm/IR/InstVisitor.h" diff --git a/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp index 1e991d8f58f2..031b1afefc9d 100644 --- a/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp +++ b/llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp @@ -10,7 +10,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Triple.h" #include "llvm/ExecutionEngine/Orc/OrcABISupport.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/IRBuilder.h" #include "llvm/Support/Format.h" #include "llvm/Transforms/Utils/Cloning.h" diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp b/llvm/lib/Transforms/Coroutines/Coroutines.cpp index 35b0f422be26..87c3a8b0d0cf 100644 --- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp +++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp @@ -19,7 +19,6 @@ #include "llvm/Analysis/CallGraph.h" #include "llvm/Analysis/CallGraphSCCPass.h" #include "llvm/IR/Attributes.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index 94c027cb7e54..0907aa01eddc 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -20,7 +20,6 @@ #include "llvm/Analysis/CallGraphSCCPass.h" #include "llvm/Frontend/OpenMP/OMPConstants.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" -#include "llvm/IR/CallSite.h" #include "llvm/InitializePasses.h" #include "llvm/Support/CommandLine.h" #include "llvm/Transforms/IPO.h" diff --git a/llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp b/llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp index 518b8895e836..853385fbf863 100644 --- a/llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp +++ b/llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp @@ -11,7 +11,6 @@ #include "llvm/Transforms/Instrumentation/InstrOrderFile.h" #include "llvm/ADT/Statistic.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" diff --git a/llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp b/llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp index d0afe2959b39..15f3642ff655 100644 --- a/llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp +++ b/llvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp @@ -23,7 +23,6 @@ #include "llvm/Analysis/GlobalsModRef.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" diff --git a/llvm/lib/Transforms/ObjCARC/ObjCARC.h b/llvm/lib/Transforms/ObjCARC/ObjCARC.h index d465630800b9..57dc7c204e6d 100644 --- a/llvm/lib/Transforms/ObjCARC/ObjCARC.h +++ b/llvm/lib/Transforms/ObjCARC/ObjCARC.h @@ -29,7 +29,6 @@ #include "llvm/Analysis/Passes.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Analysis/ValueTracking.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/InstIterator.h" #include "llvm/IR/Module.h" #include "llvm/Pass.h" diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp index af9118bc0a47..4a4beccb8a62 100644 --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -43,7 +43,6 @@ #include "llvm/Config/llvm-config.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DataLayout.h" diff --git a/llvm/lib/Transforms/Utils/EscapeEnumerator.cpp b/llvm/lib/Transforms/Utils/EscapeEnumerator.cpp index 914babeb6829..a62a28deee21 100644 --- a/llvm/lib/Transforms/Utils/EscapeEnumerator.cpp +++ b/llvm/lib/Transforms/Utils/EscapeEnumerator.cpp @@ -14,7 +14,6 @@ #include "llvm/Transforms/Utils/EscapeEnumerator.h" #include "llvm/Analysis/EHPersonalities.h" #include "llvm/Transforms/Utils/Local.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Module.h" using namespace llvm; diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index d67baf9ae749..2bc5fe90f84c 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -33,7 +33,6 @@ #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/CFG.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/ConstantRange.h" #include "llvm/IR/Constants.h" diff --git a/llvm/unittests/Analysis/AssumeBundleQueriesTest.cpp b/llvm/unittests/Analysis/AssumeBundleQueriesTest.cpp index 62293b997d5d..2260d03ff00f 100644 --- a/llvm/unittests/Analysis/AssumeBundleQueriesTest.cpp +++ b/llvm/unittests/Analysis/AssumeBundleQueriesTest.cpp @@ -9,7 +9,6 @@ #include "llvm/Analysis/AssumptionCache.h" #include "llvm/Analysis/AssumeBundleQueries.h" #include "llvm/AsmParser/Parser.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/Support/Regex.h" -- GitLab From ba4162c1c42e656f85abef11a036f4f0b3ad7453 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 22 Apr 2020 09:07:28 +0200 Subject: [PATCH 045/910] [VE] Add alternative names to registers Summary: VE uses identical names "%s0-63" to all generic registers. Change to use alternative name mechanism among all generic registers instead of hard- coding them. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D78174 --- .../Target/VE/MCTargetDesc/VEInstPrinter.cpp | 4 +- .../Target/VE/MCTargetDesc/VEInstPrinter.h | 4 +- llvm/lib/Target/VE/VERegisterInfo.td | 38 +++++++++++-------- 3 files changed, 29 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp index c833b33de7ea..74305f9f6768 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp @@ -36,7 +36,9 @@ using namespace VE; #include "VEGenAsmWriter.inc" void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { - OS << '%' << StringRef(getRegisterName(RegNo)).lower(); + // Generic registers have identical register name among register classes. + unsigned AltIdx = VE::AsmName; + OS << '%' << getRegisterName(RegNo, AltIdx); } void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address, diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h index bdf1be9a91c7..ae2426d1a4e3 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_VE_INSTPRINTER_VEINSTPRINTER_H #define LLVM_LIB_TARGET_VE_INSTPRINTER_VEINSTPRINTER_H +#include "VEMCTargetDesc.h" #include "llvm/MC/MCInstPrinter.h" namespace llvm { @@ -32,7 +33,8 @@ public: const MCSubtargetInfo &, raw_ostream &); void printInstruction(const MCInst *, uint64_t, const MCSubtargetInfo &, raw_ostream &); - static const char *getRegisterName(unsigned RegNo); + static const char *getRegisterName(unsigned RegNo, + unsigned AltIdx = VE::NoRegAltName); void printOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &OS); diff --git a/llvm/lib/Target/VE/VERegisterInfo.td b/llvm/lib/Target/VE/VERegisterInfo.td index e035049076e9..271853fc0ab3 100644 --- a/llvm/lib/Target/VE/VERegisterInfo.td +++ b/llvm/lib/Target/VE/VERegisterInfo.td @@ -10,10 +10,14 @@ // Declarations that describe the VE register file //===----------------------------------------------------------------------===// -class VEReg Enc, string n> : Register { +class VEReg enc, string n, list subregs = [], + list altNames = [], list aliases = []> + : Register { let HWEncoding{15-7} = 0; - let HWEncoding{6-0} = Enc; + let HWEncoding{6-0} = enc; let Namespace = "VE"; + let SubRegs = subregs; + let Aliases = aliases; } let Namespace = "VE" in { @@ -21,41 +25,45 @@ let Namespace = "VE" in { def sub_i16 : SubRegIndex<16, 48>; // Low 16 bit (48..63) def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) + def AsmName : RegAltNameIndex; } -// Registers are identified with 7-bit ID numbers. -// R - 64-bit integer or floating-point registers -class R Enc, string n, list subregs = [], - list aliases = []>: VEReg { - let SubRegs = subregs; - let Aliases = aliases; -} +//----------------------------------------------------------------------------- +// Gneric Registers +//----------------------------------------------------------------------------- + +let RegAltNameIndices = [AsmName] in { // Generic integer registers - 8 bits wide foreach I = 0-63 in - def SB#I : R, DwarfRegNum<[I]>; + def SB#I : VEReg, DwarfRegNum<[I]>; // Generic integer registers - 16 bits wide let SubRegIndices = [sub_i8] in foreach I = 0-63 in - def SH#I : R("SB"#I)]>, DwarfRegNum<[I]>; + def SH#I : VEReg("SB"#I)], ["s"#I]>, + DwarfRegNum<[I]>; // Generic integer registers - 32 bits wide let SubRegIndices = [sub_i16] in foreach I = 0-63 in - def SW#I : R("SH"#I)]>, DwarfRegNum<[I]>; + def SW#I : VEReg("SH"#I)], ["s"#I]>, + DwarfRegNum<[I]>; // Generic floating point registers - 32 bits wide // NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation // problem. foreach I = 0-63 in - def SF#I : R("SW"#I)]>, DwarfRegNum<[I]>; + def SF#I : VEReg("SW"#I)]>, + DwarfRegNum<[I]>; // Generic integer registers - 64 bits wide let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in foreach I = 0-63 in - def SX#I : R("SW"#I), !cast("SF"#I)]>, - DwarfRegNum<[I]>; + def SX#I : VEReg("SW"#I), !cast("SF"#I)], + ["s"#I]>, DwarfRegNum<[I]>; + +} // RegAltNameIndices = [AsmName] // Register classes. // -- GitLab From a6ef4719198e8bc69c6a704c2d95f6421eeeab4c Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 22 Apr 2020 09:09:16 +0200 Subject: [PATCH 046/910] [VE] Update shift operation instructions Summary: Changing all mnemonic to match assembly instructions to simplify mnemonic naming rules. This time update all shift operation instructions. This also corrects instruction's operation kinds. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D78468 --- llvm/lib/Target/VE/VEInstrInfo.td | 141 ++++++++++++------------------ 1 file changed, 56 insertions(+), 85 deletions(-) diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 2cdb6c15384f..46c5010c5b9b 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -32,6 +32,10 @@ def uimm1 : Operand, PatLeaf<(imm), [{ def uimm6 : Operand, PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>; +// uimm7 - Generic immediate value. +def uimm7 : Operand, PatLeaf<(imm), [{ + return isUInt<7>(N->getZExtValue()); }]>; + // simm7 - Generic immediate value. def LO7 : SDNodeXFormgetTargetConstant(SignExtend32(N->getSExtValue(), 7), @@ -423,69 +427,27 @@ multiclass RRFmopc, RRNDmrm, RRNDmim; -// Multiclass for RR type instructions -// Used by sra, sla, sll, and similar instructions -// The order of operands are "$sx, $sz, $sy" - +// Generic RR multiclass for shift instructions with 2 arguments. +// e.g. SLL, SRL, SLAWSX, and etc. +let hasSideEffects = 0 in multiclass RRImopc, RegisterClass RC, ValueType Ty, - Operand immOp, Operand immOp2, - SDPatternOperator OpNode=null_frag> { - def rr : RR< - opc, (outs RC:$sx), (ins RC:$sz, I32:$sy), - !strconcat(opcStr, " $sx, $sz, $sy"), - [(set Ty:$sx, (OpNode Ty:$sz, i32:$sy))]> { - let cy = 1; - let cz = 1; - let hasSideEffects = 0; - } - def ri : RR< - opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy), - !strconcat(opcStr, " $sx, $sz, $sy"), - [(set Ty:$sx, (OpNode Ty:$sz, (i32 simm7:$sy)))]> { - let cy = 0; - let cz = 1; - let hasSideEffects = 0; - } - def rm0 : RR< - opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy), - !strconcat(opcStr, " $sx, (${sz})0, $sy")> { - let cy = 1; - let cz = 0; - let sz{6} = 1; - let hasSideEffects = 0; - } - def rm1 : RR< - opc, (outs RC:$sx), (ins immOp2:$sz, I32:$sy), - !strconcat(opcStr, " $sx, (${sz})1, $sy")> { - let cy = 1; - let cz = 0; - let hasSideEffects = 0; - } - def im0 : RR< - opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy), - !strconcat(opcStr, " $sx, (${sz})0, $sy")> { - let cy = 0; - let cz = 0; - let sz{6} = 1; - let hasSideEffects = 0; - } - def im1 : RR< - opc, (outs RC:$sx), (ins immOp2:$sz, immOp:$sy), - !strconcat(opcStr, " $sx, (${sz})1, $sy")> { - let cy = 0; - let cz = 0; - let hasSideEffects = 0; - } - def zi : RR< - opc, (outs RC:$sx), (ins immOp:$sy), - !strconcat(opcStr, " $sx, $sy"), - [(set Ty:$sx, (OpNode 0, (i32 simm7:$sy)))]> { - let cy = 0; - let cz = 0; - let sz = 0; - let hasSideEffects = 0; - } + SDPatternOperator OpNode = null_frag> { + def rr : RR; + let cz = 0 in + def mr : RR; + let cy = 0 in + def ri : RR; + let cy = 0, cz = 0 in + def mi : RR; } // Generic RR multiclass with an argument. @@ -898,23 +860,32 @@ let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>; let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>; let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>; -// 5.3.2.4 Shift Instructions +//----------------------------------------------------------------------------- +// Section 8.6 - Shift Operation Instructions +//----------------------------------------------------------------------------- -let cx = 0 in -defm SRAX : RRIm<"sra.l", 0x77, I64, i64, simm7, uimm6, sra>; -let cx = 0 in -defm SRA : RRIm<"sra.w.sx", 0x76, I32, i32, simm7, uimm6, sra>; -let cx = 1 in -defm SRAU : RRIm<"sra.w.zx", 0x76, I32, i32, simm7, uimm6>; +// Section 8.6.1 - SLL (Shift Left Logical) +defm SLL : RRIm<"sll", 0x65, I64, i64, shl>; -let cx = 0 in -defm SLL : RRIm<"sll", 0x65, I64, i64, simm7, uimm6, shl>; -let cx = 0 in -defm SLA : RRIm<"sla.w.sx", 0x66, I32, i32, simm7, uimm6, shl>; -let cx = 1 in -defm SLAU : RRIm<"sla.w.zx", 0x66, I32, i32, simm7, uimm6>; -let cx = 0 in -defm SRL : RRIm<"srl", 0x75, I64, i64, simm7, uimm6, srl>; +// Section 8.6.2 - SLD (Shift Left Double) + +// Section 8.6.3 - SRL (Shift Right Logical) +defm SRL : RRIm<"srl", 0x75, I64, i64, srl>; + +// Section 8.6.4 - SRD (Shift Right Double) + +// Section 8.6.5 - SLA (Shift Left Arithmetic) +defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>; +let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>; + +// Section 8.6.6 - SLAX (Shift Left Arithmetic) + +// Section 8.6.7 - SRA (Shift Right Arithmetic) +defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>; +let cx = 1 in defm SRAWZX : RRIm<"sra.w.zx", 0x76, I32, i32>; + +// Section 8.6.8 - SRAX (Shift Right Arithmetic) +defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>; def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))), (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), @@ -1113,27 +1084,27 @@ def : Pat<(f64 fpimm:$val), // Cast to i1 def : Pat<(sext_inreg I32:$src, i1), - (SRAri (SLAri $src, 31), 31)>; + (SRAWSXri (SLAWSXri $src, 31), 31)>; def : Pat<(sext_inreg I64:$src, i1), - (SRAXri (SLLri $src, 63), 63)>; + (SRALri (SLLri $src, 63), 63)>; // Cast to i8 def : Pat<(sext_inreg I32:$src, i8), - (SRAri (SLAri $src, 24), 24)>; + (SRAWSXri (SLAWSXri $src, 24), 24)>; def : Pat<(sext_inreg I64:$src, i8), - (SRAXri (SLLri $src, 56), 56)>; + (SRALri (SLLri $src, 56), 56)>; def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8), - (EXTRACT_SUBREG (SRAXri (SLLri $src, 56), 56), sub_i32)>; + (EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>; def : Pat<(and (trunc i64:$src), 0xff), (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>; // Cast to i16 def : Pat<(sext_inreg I32:$src, i16), - (SRAri (SLAri $src, 16), 16)>; + (SRAWSXri (SLAWSXri $src, 16), 16)>; def : Pat<(sext_inreg I64:$src, i16), - (SRAXri (SLLri $src, 48), 48)>; + (SRALri (SLLri $src, 48), 48)>; def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16), - (EXTRACT_SUBREG (SRAXri (SLLri $src, 48), 48), sub_i32)>; + (EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>; def : Pat<(and (trunc i64:$src), 0xffff), (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>; @@ -1553,7 +1524,7 @@ def : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>; def : Pat<(i64 (bitconvert f64:$src)), (COPY_TO_REGCLASS $src, I64)>; def : Pat<(i32 (bitconvert f32:$op)), - (EXTRACT_SUBREG (SRAXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (SRALri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $op, sub_f32), 32), sub_i32)>; def : Pat<(f32 (bitconvert i32:$op)), (EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), -- GitLab From a53874b7e4c82416b8eb48bbd45b5cb93f1e09d3 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 22 Apr 2020 09:14:06 +0200 Subject: [PATCH 047/910] [lldb] Fix modules build by adding missing include This header is using FileSpec so we should at least include the forward header. --- lldb/include/lldb/Utility/XcodeSDK.h | 1 + 1 file changed, 1 insertion(+) diff --git a/lldb/include/lldb/Utility/XcodeSDK.h b/lldb/include/lldb/Utility/XcodeSDK.h index b186ab4a7091..552c51c36844 100644 --- a/lldb/include/lldb/Utility/XcodeSDK.h +++ b/lldb/include/lldb/Utility/XcodeSDK.h @@ -9,6 +9,7 @@ #ifndef LLDB_UTILITY_SDK_H #define LLDB_UTILITY_SDK_H +#include "lldb/lldb-forward.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/VersionTuple.h" #include -- GitLab From 5397f290871b2e27265569e3d8197a9565373597 Mon Sep 17 00:00:00 2001 From: aartbik Date: Tue, 21 Apr 2020 20:43:00 -0700 Subject: [PATCH 048/910] [llvm] [X86] Make test more robust against different builds Summary: Rationale: Using the --debug-only flag requires a debug build. Also, the debug output is not always consistent over different builds. This change avoids all problems by just testing the generated assembly for AVX. Reviewers: craig.topper, mehdi_amini, nicolasvasilache Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78609 --- llvm/test/CodeGen/X86/pr45563.ll | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/X86/pr45563.ll b/llvm/test/CodeGen/X86/pr45563.ll index 3fbd991729d5..0c205f665b82 100644 --- a/llvm/test/CodeGen/X86/pr45563.ll +++ b/llvm/test/CodeGen/X86/pr45563.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -debug-only=isel -O3 -mattr=avx 2>&1 | FileCheck %s +; RUN: llc < %s -O3 -mattr=avx | FileCheck %s ; Bug 45563: ; The LowerMLOAD() method AVX masked load branch should @@ -12,7 +12,8 @@ define <16 x double> @bug45563(<16 x double>* %addr, <16 x double> %dst, <16 x i64> %e, <16 x i64> %f) { ; CHECK-LABEL: bug45563: -; CHECK: v4f64 = vselect +; CHECK: vmaskmovpd +; CHECK: vblendvpd %mask = icmp slt <16 x i64> %e, %f %res = call <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %addr, i32 4, <16 x i1>%mask, <16 x double> %dst) ret <16 x double> %res -- GitLab From 28138027460d3a99646bb0c47dda7472e34d2bb5 Mon Sep 17 00:00:00 2001 From: Frederik Gossen Date: Tue, 21 Apr 2020 07:00:37 +0000 Subject: [PATCH 049/910] [MLIR] Fix test case for kernel attribute. Summary: Fix a broken test case in the `invalid.mlir` lit test case. `expect` was missing its `e`. Differential Revision: https://reviews.llvm.org/D78540 --- mlir/test/Dialect/GPU/invalid.mlir | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/test/Dialect/GPU/invalid.mlir b/mlir/test/Dialect/GPU/invalid.mlir index f2a9e1175310..610c1c046e8b 100644 --- a/mlir/test/Dialect/GPU/invalid.mlir +++ b/mlir/test/Dialect/GPU/invalid.mlir @@ -140,13 +140,13 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { gpu.module @kernels { - gpu.func @kernel_1(%arg1 : !llvm<"float*">) kernel { + gpu.func @kernel_1(%arg1 : !llvm<"float*">) { gpu.return } } func @launch_func_missing_kernel_attr(%sz : index, %arg : !llvm<"float*">) { - // xpected-error@+1 {{kernel function is missing the 'gpu.kernel' attribute}} + // expected-error@+1 {{kernel function is missing the 'gpu.kernel' attribute}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz, %arg) {kernel = "kernel_1", kernel_module = @kernels} : (index, index, index, index, index, index, !llvm<"float*">) -> () -- GitLab From 04ef154124e51827c5ed5cb5e6535a2c42bc437a Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Tue, 21 Apr 2020 15:57:28 +0100 Subject: [PATCH 050/910] [NFC] Test changes Add some more targets for the ARM cost model tests and add some tests for icmps and bitcasts. --- llvm/test/Analysis/CostModel/ARM/arith.ll | 615 +++++++++++++ llvm/test/Analysis/CostModel/ARM/cast.ll | 978 +++++++++++++++++++++ llvm/test/Analysis/CostModel/ARM/divrem.ll | 816 +++++++++++++++++ llvm/test/Analysis/CostModel/ARM/icmps.ll | 56 ++ llvm/test/Analysis/CostModel/ARM/select.ll | 32 + 5 files changed, 2497 insertions(+) create mode 100644 llvm/test/Analysis/CostModel/ARM/icmps.ll diff --git a/llvm/test/Analysis/CostModel/ARM/arith.ll b/llvm/test/Analysis/CostModel/ARM/arith.ll index 4e9de7a122ce..ddde98b7433d 100644 --- a/llvm/test/Analysis/CostModel/ARM/arith.ll +++ b/llvm/test/Analysis/CostModel/ARM/arith.ll @@ -2,6 +2,9 @@ ; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,+mve1beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE1 ; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE2 ; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,+mve4beat < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE4 +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE +; RUN: opt -cost-model -analyze -mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R define void @i8() { ; CHECK-LABEL: 'i8' @@ -15,6 +18,42 @@ define void @i8() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i8 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i8 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i8' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i8' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i8' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c = add i8 undef, undef %d = sub i8 undef, undef @@ -40,6 +79,42 @@ define void @i16() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i16 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i16 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c = add i16 undef, undef %d = sub i16 undef, undef @@ -65,6 +140,42 @@ define void @i32() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i32 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i32 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = add i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = sub i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = mul i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = ashr i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = lshr i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %h = shl i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i = and i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j = or i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k = xor i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c = add i32 undef, undef %d = sub i32 undef, undef @@ -90,6 +201,42 @@ define void @i64() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j = or i64 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k = xor i64 undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c = add i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d = sub i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e = mul i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f = ashr i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g = lshr i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h = shl i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i = and i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j = or i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k = xor i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c = add i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d = sub i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e = mul i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f = ashr i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g = lshr i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h = shl i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i = and i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j = or i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k = xor i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c = add i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d = sub i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e = mul i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f = ashr i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g = lshr i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h = shl i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i = and i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j = or i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k = xor i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c = add i64 undef, undef %d = sub i64 undef, undef @@ -221,6 +368,123 @@ define void @vi8() { ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j16 = or <16 x i8> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k16 = xor <16 x i8> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi8' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi8' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi8' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c2 = add <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d2 = sub <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e2 = mul <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i2 = and <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j2 = or <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k2 = xor <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c4 = add <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d4 = sub <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e4 = mul <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f4 = ashr <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g4 = lshr <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h4 = shl <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i4 = and <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j4 = or <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k4 = xor <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = add <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d8 = sub <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e8 = mul <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f8 = ashr <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g8 = lshr <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h8 = shl <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = and <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j8 = or <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k8 = xor <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c16 = add <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d16 = sub <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e16 = mul <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f16 = ashr <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g16 = lshr <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h16 = shl <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i16 = and <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j16 = or <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k16 = xor <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c2 = add <2 x i8> undef, undef %d2 = sub <2 x i8> undef, undef @@ -378,6 +642,123 @@ define void @vi16() { ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j16 = or <16 x i16> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k16 = xor <16 x i16> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c2 = add <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d2 = sub <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e2 = mul <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i2 = and <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j2 = or <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k2 = xor <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c4 = add <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d4 = sub <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e4 = mul <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f4 = ashr <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g4 = lshr <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h4 = shl <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i4 = and <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j4 = or <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k4 = xor <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c8 = add <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d8 = sub <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e8 = mul <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f8 = ashr <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g8 = lshr <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h8 = shl <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i8 = and <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j8 = or <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k8 = xor <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c16 = add <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d16 = sub <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e16 = mul <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f16 = ashr <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g16 = lshr <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h16 = shl <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i16 = and <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j16 = or <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k16 = xor <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c2 = add <2 x i16> undef, undef %d2 = sub <2 x i16> undef, undef @@ -535,6 +916,123 @@ define void @vi32() { ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i32> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i32> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c2 = add <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d2 = sub <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i2 = and <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j2 = or <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k2 = xor <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c4 = add <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d4 = sub <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i4 = and <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j4 = or <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k4 = xor <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c8 = add <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d8 = sub <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i8 = and <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j8 = or <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k8 = xor <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c16 = add <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d16 = sub <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i16 = and <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j16 = or <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k16 = xor <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c2 = add <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d2 = sub <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e2 = mul <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i2 = and <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j2 = or <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k2 = xor <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c4 = add <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d4 = sub <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e4 = mul <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f4 = ashr <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g4 = lshr <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h4 = shl <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i4 = and <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j4 = or <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k4 = xor <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c8 = add <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d8 = sub <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e8 = mul <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f8 = ashr <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g8 = lshr <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h8 = shl <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i8 = and <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j8 = or <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k8 = xor <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c16 = add <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d16 = sub <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e16 = mul <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f16 = ashr <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g16 = lshr <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h16 = shl <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i16 = and <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j16 = or <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k16 = xor <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c2 = add <2 x i32> undef, undef %d2 = sub <2 x i32> undef, undef @@ -692,6 +1190,123 @@ define void @vi64() { ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %j16 = or <16 x i64> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %k16 = xor <16 x i64> undef, undef ; CHECK-MVE4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c2 = add <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d2 = sub <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e2 = mul <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = ashr <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g2 = lshr <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h2 = shl <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i2 = and <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j2 = or <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k2 = xor <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c4 = add <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d4 = sub <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e4 = mul <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = ashr <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g4 = lshr <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h4 = shl <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i4 = and <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j4 = or <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k4 = xor <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c8 = add <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d8 = sub <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e8 = mul <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f8 = ashr <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g8 = lshr <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h8 = shl <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i8 = and <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j8 = or <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k8 = xor <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %c16 = add <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %d16 = sub <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %e16 = mul <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %f16 = ashr <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %g16 = lshr <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %h16 = shl <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %i16 = and <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %j16 = or <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %k16 = xor <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c2 = add <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d2 = sub <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e2 = mul <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = ashr <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g2 = lshr <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h2 = shl <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i2 = and <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j2 = or <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k2 = xor <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c4 = add <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d4 = sub <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e4 = mul <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = ashr <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g4 = lshr <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h4 = shl <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i4 = and <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j4 = or <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k4 = xor <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %c8 = add <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %d8 = sub <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e8 = mul <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f8 = ashr <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g8 = lshr <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h8 = shl <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %i8 = and <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %j8 = or <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %k8 = xor <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %c16 = add <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %d16 = sub <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %e16 = mul <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %f16 = ashr <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %g16 = lshr <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %h16 = shl <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %i16 = and <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %j16 = or <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %k16 = xor <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c2 = add <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d2 = sub <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e2 = mul <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f2 = ashr <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g2 = lshr <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %h2 = shl <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %i2 = and <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %j2 = or <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %k2 = xor <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %c4 = add <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %d4 = sub <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %e4 = mul <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f4 = ashr <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %g4 = lshr <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %h4 = shl <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %i4 = and <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %j4 = or <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %k4 = xor <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %c8 = add <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %d8 = sub <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e8 = mul <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f8 = ashr <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g8 = lshr <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %h8 = shl <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %i8 = and <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %j8 = or <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %k8 = xor <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %c16 = add <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %d16 = sub <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e16 = mul <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f16 = ashr <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %g16 = lshr <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %h16 = shl <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %i16 = and <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %j16 = or <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %k16 = xor <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %c2 = add <2 x i64> undef, undef %d2 = sub <2 x i64> undef, undef diff --git a/llvm/test/Analysis/CostModel/ARM/cast.ll b/llvm/test/Analysis/CostModel/ARM/cast.ll index d7592124f886..5d857bc2e802 100644 --- a/llvm/test/Analysis/CostModel/ARM/cast.ll +++ b/llvm/test/Analysis/CostModel/ARM/cast.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK-NEON ; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE +; RUN: opt -cost-model -analyze -mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R define i32 @casts() { ; CHECK-NEON-LABEL: 'casts' @@ -536,6 +539,807 @@ define i32 @casts() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1045 for instruction: %r248 = uitofp <16 x i64> undef to <16 x double> ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1045 for instruction: %r249 = sitofp <16 x i64> undef to <16 x double> ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-MAIN-LABEL: 'casts' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r0 = sext i1 undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r1 = zext i1 undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r2 = sext i1 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = zext i1 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i1 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i1 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r6 = sext i1 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = zext i1 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = trunc i8 undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = sext i8 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = zext i8 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = sext i8 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = zext i8 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = sext i8 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r14 = zext i8 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r15 = trunc i16 undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r16 = trunc i16 undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r17 = sext i16 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r18 = zext i16 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r19 = sext i16 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r20 = zext i16 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r21 = trunc i32 undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r22 = trunc i32 undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r23 = trunc i32 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r24 = sext i32 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r25 = zext i32 undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r26 = trunc i64 undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r27 = trunc i64 undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r28 = trunc i64 undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r29 = trunc i64 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r30 = fptoui float undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r31 = fptosi float undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r32 = fptoui float undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r33 = fptosi float undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r34 = fptoui float undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r35 = fptosi float undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r36 = fptoui float undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r37 = fptosi float undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r38 = fptoui float undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r39 = fptosi float undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r40 = fptoui double undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r41 = fptosi double undef to i1 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r42 = fptoui double undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r43 = fptosi double undef to i8 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r44 = fptoui double undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r45 = fptosi double undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r46 = fptoui double undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r47 = fptosi double undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r48 = fptoui double undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r49 = fptosi double undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r50 = sitofp i1 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r51 = uitofp i1 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r52 = sitofp i1 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r53 = uitofp i1 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r54 = sitofp i8 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r55 = uitofp i8 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r56 = sitofp i8 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r57 = uitofp i8 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r58 = sitofp i16 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r59 = uitofp i16 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r60 = sitofp i16 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r61 = uitofp i16 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r62 = sitofp i32 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r63 = uitofp i32 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r64 = sitofp i32 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r65 = uitofp i32 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r66 = sitofp i64 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r67 = uitofp i64 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r68 = sitofp i64 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r69 = uitofp i64 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q71 = sext <8 x i8> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r70 = sext <8 x i8> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r71 = sext <16 x i8> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q73 = zext <8 x i8> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r72 = zext <8 x i8> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r73 = zext <16 x i8> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_0 = sext <8 x i8> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_1 = zext <8 x i8> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %rext_2 = sext <8 x i16> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_3 = zext <8 x i16> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %rext_4 = sext <4 x i16> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %rext_5 = zext <4 x i16> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_6 = sext <2 x i8> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_7 = zext <2 x i8> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %rext_8 = sext <2 x i16> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_9 = zext <2 x i16> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_a = sext <2 x i32> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_b = zext <2 x i32> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r74 = trunc <8 x i32> undef to <8 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r75 = trunc <16 x i32> undef to <16 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r80 = fptrunc double undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r81 = fptrunc <2 x double> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r82 = fptrunc <4 x double> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r83 = fptrunc <8 x double> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r84 = fptrunc <16 x double> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r85 = fpext float undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r86 = fpext <2 x float> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r87 = fpext <4 x float> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r88 = fpext <8 x float> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r89 = fpext <16 x float> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r90 = fptoui <2 x float> undef to <2 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r91 = fptosi <2 x float> undef to <2 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r92 = fptoui <2 x float> undef to <2 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r93 = fptosi <2 x float> undef to <2 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r94 = fptoui <2 x float> undef to <2 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r95 = fptosi <2 x float> undef to <2 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r96 = fptoui <2 x float> undef to <2 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r97 = fptosi <2 x float> undef to <2 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r98 = fptoui <2 x float> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r99 = fptosi <2 x float> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r100 = fptoui <2 x double> undef to <2 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r101 = fptosi <2 x double> undef to <2 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r102 = fptoui <2 x double> undef to <2 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r103 = fptosi <2 x double> undef to <2 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r104 = fptoui <2 x double> undef to <2 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r105 = fptosi <2 x double> undef to <2 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r106 = fptoui <2 x double> undef to <2 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r107 = fptosi <2 x double> undef to <2 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r108 = fptoui <2 x double> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r109 = fptosi <2 x double> undef to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r110 = fptoui <4 x float> undef to <4 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r111 = fptosi <4 x float> undef to <4 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r112 = fptoui <4 x float> undef to <4 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r113 = fptosi <4 x float> undef to <4 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r114 = fptoui <4 x float> undef to <4 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r115 = fptosi <4 x float> undef to <4 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r116 = fptoui <4 x float> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r117 = fptosi <4 x float> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r118 = fptoui <4 x float> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r119 = fptosi <4 x float> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r120 = fptoui <4 x double> undef to <4 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r121 = fptosi <4 x double> undef to <4 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r122 = fptoui <4 x double> undef to <4 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r123 = fptosi <4 x double> undef to <4 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r124 = fptoui <4 x double> undef to <4 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r125 = fptosi <4 x double> undef to <4 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r126 = fptoui <4 x double> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r127 = fptosi <4 x double> undef to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r128 = fptoui <4 x double> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r129 = fptosi <4 x double> undef to <4 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r130 = fptoui <8 x float> undef to <8 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r131 = fptosi <8 x float> undef to <8 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r132 = fptoui <8 x float> undef to <8 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r133 = fptosi <8 x float> undef to <8 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r134 = fptoui <8 x float> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r135 = fptosi <8 x float> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r136 = fptoui <8 x float> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r137 = fptosi <8 x float> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r138 = fptoui <8 x float> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r139 = fptosi <8 x float> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r140 = fptoui <8 x double> undef to <8 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r141 = fptosi <8 x double> undef to <8 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r142 = fptoui <8 x double> undef to <8 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r143 = fptosi <8 x double> undef to <8 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r144 = fptoui <8 x double> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r145 = fptosi <8 x double> undef to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r146 = fptoui <8 x double> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r147 = fptosi <8 x double> undef to <8 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r148 = fptoui <8 x double> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r149 = fptosi <8 x double> undef to <8 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r150 = fptoui <16 x float> undef to <16 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r151 = fptosi <16 x float> undef to <16 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r152 = fptoui <16 x float> undef to <16 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r153 = fptosi <16 x float> undef to <16 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r154 = fptoui <16 x float> undef to <16 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r155 = fptosi <16 x float> undef to <16 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r156 = fptoui <16 x float> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r157 = fptosi <16 x float> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r158 = fptoui <16 x float> undef to <16 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r159 = fptosi <16 x float> undef to <16 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r160 = fptoui <16 x double> undef to <16 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r161 = fptosi <16 x double> undef to <16 x i1> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r162 = fptoui <16 x double> undef to <16 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r163 = fptosi <16 x double> undef to <16 x i8> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r164 = fptoui <16 x double> undef to <16 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r165 = fptosi <16 x double> undef to <16 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r166 = fptoui <16 x double> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r167 = fptosi <16 x double> undef to <16 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r168 = fptoui <16 x double> undef to <16 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r169 = fptosi <16 x double> undef to <16 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r170 = uitofp <2 x i1> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r171 = sitofp <2 x i1> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r172 = uitofp <2 x i8> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r173 = sitofp <2 x i8> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r174 = uitofp <2 x i16> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r175 = sitofp <2 x i16> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r176 = uitofp <2 x i32> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r177 = sitofp <2 x i32> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r178 = uitofp <2 x i64> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r179 = sitofp <2 x i64> undef to <2 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r180 = uitofp <2 x i1> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r181 = sitofp <2 x i1> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r182 = uitofp <2 x i8> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r183 = sitofp <2 x i8> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r184 = uitofp <2 x i16> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r185 = sitofp <2 x i16> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r186 = uitofp <2 x i32> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r187 = sitofp <2 x i32> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r188 = uitofp <2 x i64> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r189 = sitofp <2 x i64> undef to <2 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r190 = uitofp <4 x i1> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r191 = sitofp <4 x i1> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r192 = uitofp <4 x i8> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r193 = sitofp <4 x i8> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r194 = uitofp <4 x i16> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r195 = sitofp <4 x i16> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r196 = uitofp <4 x i32> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r197 = sitofp <4 x i32> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r198 = uitofp <4 x i64> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r199 = sitofp <4 x i64> undef to <4 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r200 = uitofp <4 x i1> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r201 = sitofp <4 x i1> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r202 = uitofp <4 x i8> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r203 = sitofp <4 x i8> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r204 = uitofp <4 x i16> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r205 = sitofp <4 x i16> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r206 = uitofp <4 x i32> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r207 = sitofp <4 x i32> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r208 = uitofp <4 x i64> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r209 = sitofp <4 x i64> undef to <4 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r210 = uitofp <8 x i1> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r211 = sitofp <8 x i1> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r212 = uitofp <8 x i8> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r213 = sitofp <8 x i8> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r214 = uitofp <8 x i16> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r215 = sitofp <8 x i16> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r216 = uitofp <8 x i32> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r217 = sitofp <8 x i32> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r218 = uitofp <8 x i64> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r219 = sitofp <8 x i64> undef to <8 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r220 = uitofp <8 x i1> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r221 = sitofp <8 x i1> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r222 = uitofp <8 x i8> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r223 = sitofp <8 x i8> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r224 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r225 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r226 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r227 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r228 = uitofp <8 x i64> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r229 = sitofp <8 x i64> undef to <8 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r230 = uitofp <16 x i1> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r231 = sitofp <16 x i1> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r232 = uitofp <16 x i8> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r233 = sitofp <16 x i8> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r234 = uitofp <16 x i16> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r235 = sitofp <16 x i16> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r236 = uitofp <16 x i32> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r237 = sitofp <16 x i32> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r238 = uitofp <16 x i64> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r239 = sitofp <16 x i64> undef to <16 x float> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r240 = uitofp <16 x i1> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r241 = sitofp <16 x i1> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r242 = uitofp <16 x i8> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r243 = sitofp <16 x i8> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r244 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r245 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r246 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r247 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r248 = uitofp <16 x i64> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r249 = sitofp <16 x i64> undef to <16 x double> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-BASE-LABEL: 'casts' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r0 = sext i1 undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r1 = zext i1 undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r2 = sext i1 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = zext i1 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i1 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i1 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r6 = sext i1 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = zext i1 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = trunc i8 undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = sext i8 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = zext i8 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = sext i8 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = zext i8 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = sext i8 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r14 = zext i8 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r15 = trunc i16 undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r16 = trunc i16 undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r17 = sext i16 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r18 = zext i16 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r19 = sext i16 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r20 = zext i16 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r21 = trunc i32 undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r22 = trunc i32 undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r23 = trunc i32 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r24 = sext i32 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r25 = zext i32 undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r26 = trunc i64 undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r27 = trunc i64 undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r28 = trunc i64 undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r29 = trunc i64 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r30 = fptoui float undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r31 = fptosi float undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r32 = fptoui float undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r33 = fptosi float undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r34 = fptoui float undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r35 = fptosi float undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r36 = fptoui float undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r37 = fptosi float undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r38 = fptoui float undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r39 = fptosi float undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r40 = fptoui double undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r41 = fptosi double undef to i1 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r42 = fptoui double undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r43 = fptosi double undef to i8 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r44 = fptoui double undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r45 = fptosi double undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r46 = fptoui double undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r47 = fptosi double undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r48 = fptoui double undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r49 = fptosi double undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r50 = sitofp i1 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r51 = uitofp i1 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r52 = sitofp i1 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r53 = uitofp i1 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r54 = sitofp i8 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r55 = uitofp i8 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r56 = sitofp i8 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r57 = uitofp i8 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r58 = sitofp i16 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r59 = uitofp i16 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r60 = sitofp i16 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r61 = uitofp i16 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r62 = sitofp i32 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r63 = uitofp i32 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r64 = sitofp i32 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r65 = uitofp i32 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r66 = sitofp i64 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r67 = uitofp i64 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r68 = sitofp i64 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r69 = uitofp i64 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q71 = sext <8 x i8> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r70 = sext <8 x i8> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r71 = sext <16 x i8> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q73 = zext <8 x i8> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r72 = zext <8 x i8> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r73 = zext <16 x i8> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_0 = sext <8 x i8> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_1 = zext <8 x i8> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %rext_2 = sext <8 x i16> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %rext_3 = zext <8 x i16> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %rext_4 = sext <4 x i16> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %rext_5 = zext <4 x i16> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_6 = sext <2 x i8> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_7 = zext <2 x i8> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %rext_8 = sext <2 x i16> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_9 = zext <2 x i16> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_a = sext <2 x i32> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %rext_b = zext <2 x i32> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r74 = trunc <8 x i32> undef to <8 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r75 = trunc <16 x i32> undef to <16 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r80 = fptrunc double undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r81 = fptrunc <2 x double> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r82 = fptrunc <4 x double> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r83 = fptrunc <8 x double> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r84 = fptrunc <16 x double> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r85 = fpext float undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r86 = fpext <2 x float> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r87 = fpext <4 x float> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r88 = fpext <8 x float> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r89 = fpext <16 x float> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r90 = fptoui <2 x float> undef to <2 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r91 = fptosi <2 x float> undef to <2 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r92 = fptoui <2 x float> undef to <2 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r93 = fptosi <2 x float> undef to <2 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r94 = fptoui <2 x float> undef to <2 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r95 = fptosi <2 x float> undef to <2 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r96 = fptoui <2 x float> undef to <2 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r97 = fptosi <2 x float> undef to <2 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r98 = fptoui <2 x float> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r99 = fptosi <2 x float> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r100 = fptoui <2 x double> undef to <2 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r101 = fptosi <2 x double> undef to <2 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r102 = fptoui <2 x double> undef to <2 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r103 = fptosi <2 x double> undef to <2 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r104 = fptoui <2 x double> undef to <2 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r105 = fptosi <2 x double> undef to <2 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r106 = fptoui <2 x double> undef to <2 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r107 = fptosi <2 x double> undef to <2 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r108 = fptoui <2 x double> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r109 = fptosi <2 x double> undef to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r110 = fptoui <4 x float> undef to <4 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r111 = fptosi <4 x float> undef to <4 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r112 = fptoui <4 x float> undef to <4 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r113 = fptosi <4 x float> undef to <4 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r114 = fptoui <4 x float> undef to <4 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r115 = fptosi <4 x float> undef to <4 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r116 = fptoui <4 x float> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r117 = fptosi <4 x float> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r118 = fptoui <4 x float> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r119 = fptosi <4 x float> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r120 = fptoui <4 x double> undef to <4 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r121 = fptosi <4 x double> undef to <4 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r122 = fptoui <4 x double> undef to <4 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r123 = fptosi <4 x double> undef to <4 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r124 = fptoui <4 x double> undef to <4 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r125 = fptosi <4 x double> undef to <4 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r126 = fptoui <4 x double> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r127 = fptosi <4 x double> undef to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r128 = fptoui <4 x double> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r129 = fptosi <4 x double> undef to <4 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r130 = fptoui <8 x float> undef to <8 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r131 = fptosi <8 x float> undef to <8 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r132 = fptoui <8 x float> undef to <8 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r133 = fptosi <8 x float> undef to <8 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r134 = fptoui <8 x float> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r135 = fptosi <8 x float> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r136 = fptoui <8 x float> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r137 = fptosi <8 x float> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r138 = fptoui <8 x float> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r139 = fptosi <8 x float> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r140 = fptoui <8 x double> undef to <8 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r141 = fptosi <8 x double> undef to <8 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r142 = fptoui <8 x double> undef to <8 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r143 = fptosi <8 x double> undef to <8 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r144 = fptoui <8 x double> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r145 = fptosi <8 x double> undef to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r146 = fptoui <8 x double> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r147 = fptosi <8 x double> undef to <8 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r148 = fptoui <8 x double> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r149 = fptosi <8 x double> undef to <8 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r150 = fptoui <16 x float> undef to <16 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r151 = fptosi <16 x float> undef to <16 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r152 = fptoui <16 x float> undef to <16 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r153 = fptosi <16 x float> undef to <16 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r154 = fptoui <16 x float> undef to <16 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r155 = fptosi <16 x float> undef to <16 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r156 = fptoui <16 x float> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r157 = fptosi <16 x float> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r158 = fptoui <16 x float> undef to <16 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r159 = fptosi <16 x float> undef to <16 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r160 = fptoui <16 x double> undef to <16 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r161 = fptosi <16 x double> undef to <16 x i1> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r162 = fptoui <16 x double> undef to <16 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r163 = fptosi <16 x double> undef to <16 x i8> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r164 = fptoui <16 x double> undef to <16 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r165 = fptosi <16 x double> undef to <16 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r166 = fptoui <16 x double> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r167 = fptosi <16 x double> undef to <16 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r168 = fptoui <16 x double> undef to <16 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r169 = fptosi <16 x double> undef to <16 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r170 = uitofp <2 x i1> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r171 = sitofp <2 x i1> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r172 = uitofp <2 x i8> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r173 = sitofp <2 x i8> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r174 = uitofp <2 x i16> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r175 = sitofp <2 x i16> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r176 = uitofp <2 x i32> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r177 = sitofp <2 x i32> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r178 = uitofp <2 x i64> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r179 = sitofp <2 x i64> undef to <2 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r180 = uitofp <2 x i1> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r181 = sitofp <2 x i1> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r182 = uitofp <2 x i8> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r183 = sitofp <2 x i8> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r184 = uitofp <2 x i16> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r185 = sitofp <2 x i16> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r186 = uitofp <2 x i32> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r187 = sitofp <2 x i32> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r188 = uitofp <2 x i64> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r189 = sitofp <2 x i64> undef to <2 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r190 = uitofp <4 x i1> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r191 = sitofp <4 x i1> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r192 = uitofp <4 x i8> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r193 = sitofp <4 x i8> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r194 = uitofp <4 x i16> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r195 = sitofp <4 x i16> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r196 = uitofp <4 x i32> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r197 = sitofp <4 x i32> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r198 = uitofp <4 x i64> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r199 = sitofp <4 x i64> undef to <4 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r200 = uitofp <4 x i1> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r201 = sitofp <4 x i1> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r202 = uitofp <4 x i8> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r203 = sitofp <4 x i8> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r204 = uitofp <4 x i16> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r205 = sitofp <4 x i16> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r206 = uitofp <4 x i32> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r207 = sitofp <4 x i32> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r208 = uitofp <4 x i64> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r209 = sitofp <4 x i64> undef to <4 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r210 = uitofp <8 x i1> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r211 = sitofp <8 x i1> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r212 = uitofp <8 x i8> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r213 = sitofp <8 x i8> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r214 = uitofp <8 x i16> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r215 = sitofp <8 x i16> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r216 = uitofp <8 x i32> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r217 = sitofp <8 x i32> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r218 = uitofp <8 x i64> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r219 = sitofp <8 x i64> undef to <8 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r220 = uitofp <8 x i1> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r221 = sitofp <8 x i1> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r222 = uitofp <8 x i8> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r223 = sitofp <8 x i8> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r224 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r225 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r226 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r227 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r228 = uitofp <8 x i64> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r229 = sitofp <8 x i64> undef to <8 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r230 = uitofp <16 x i1> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r231 = sitofp <16 x i1> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r232 = uitofp <16 x i8> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r233 = sitofp <16 x i8> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r234 = uitofp <16 x i16> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r235 = sitofp <16 x i16> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r236 = uitofp <16 x i32> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r237 = sitofp <16 x i32> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r238 = uitofp <16 x i64> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %r239 = sitofp <16 x i64> undef to <16 x float> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r240 = uitofp <16 x i1> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r241 = sitofp <16 x i1> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r242 = uitofp <16 x i8> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r243 = sitofp <16 x i8> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r244 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r245 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r246 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %r247 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r248 = uitofp <16 x i64> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r249 = sitofp <16 x i64> undef to <16 x double> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8R-LABEL: 'casts' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r0 = sext i1 undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r1 = zext i1 undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r2 = sext i1 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r3 = zext i1 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i1 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i1 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r6 = sext i1 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r7 = zext i1 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r8 = trunc i8 undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = sext i8 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = zext i8 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = sext i8 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r12 = zext i8 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r13 = sext i8 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r14 = zext i8 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r15 = trunc i16 undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r16 = trunc i16 undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r17 = sext i16 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r18 = zext i16 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r19 = sext i16 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r20 = zext i16 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r21 = trunc i32 undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r22 = trunc i32 undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r23 = trunc i32 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r24 = sext i32 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r25 = zext i32 undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r26 = trunc i64 undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r27 = trunc i64 undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r28 = trunc i64 undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r29 = trunc i64 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r30 = fptoui float undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r31 = fptosi float undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r32 = fptoui float undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r33 = fptosi float undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r34 = fptoui float undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r35 = fptosi float undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r36 = fptoui float undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r37 = fptosi float undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r38 = fptoui float undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r39 = fptosi float undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r40 = fptoui double undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r41 = fptosi double undef to i1 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r42 = fptoui double undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r43 = fptosi double undef to i8 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r44 = fptoui double undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r45 = fptosi double undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r46 = fptoui double undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r47 = fptosi double undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r48 = fptoui double undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r49 = fptosi double undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r50 = sitofp i1 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r51 = uitofp i1 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r52 = sitofp i1 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r53 = uitofp i1 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r54 = sitofp i8 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r55 = uitofp i8 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r56 = sitofp i8 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r57 = uitofp i8 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r58 = sitofp i16 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r59 = uitofp i16 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r60 = sitofp i16 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r61 = uitofp i16 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r62 = sitofp i32 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r63 = uitofp i32 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r64 = sitofp i32 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r65 = uitofp i32 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r66 = sitofp i64 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r67 = uitofp i64 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r68 = sitofp i64 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %r69 = uitofp i64 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q71 = sext <8 x i8> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s70 = sext <4 x i8> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r70 = sext <8 x i8> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %r71 = sext <16 x i8> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %q73 = zext <8 x i8> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s72 = zext <4 x i8> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r72 = zext <8 x i8> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %r73 = zext <16 x i8> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %rext_0 = sext <8 x i8> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %rext_1 = zext <8 x i8> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %rext_2 = sext <8 x i16> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %rext_3 = zext <8 x i16> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %rext_4 = sext <4 x i16> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %rext_5 = zext <4 x i16> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_6 = sext <2 x i8> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_7 = zext <2 x i8> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_8 = sext <2 x i16> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_9 = zext <2 x i16> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_a = sext <2 x i32> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %rext_b = zext <2 x i32> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r74 = trunc <8 x i32> undef to <8 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %r75 = trunc <16 x i32> undef to <16 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r80 = fptrunc double undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r81 = fptrunc <2 x double> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r82 = fptrunc <4 x double> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r83 = fptrunc <8 x double> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r84 = fptrunc <16 x double> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r85 = fpext float undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r86 = fpext <2 x float> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r87 = fpext <4 x float> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r88 = fpext <8 x float> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r89 = fpext <16 x float> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r90 = fptoui <2 x float> undef to <2 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r91 = fptosi <2 x float> undef to <2 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r92 = fptoui <2 x float> undef to <2 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r93 = fptosi <2 x float> undef to <2 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r94 = fptoui <2 x float> undef to <2 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r95 = fptosi <2 x float> undef to <2 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r96 = fptoui <2 x float> undef to <2 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r97 = fptosi <2 x float> undef to <2 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r98 = fptoui <2 x float> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r99 = fptosi <2 x float> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r100 = fptoui <2 x double> undef to <2 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r101 = fptosi <2 x double> undef to <2 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r102 = fptoui <2 x double> undef to <2 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r103 = fptosi <2 x double> undef to <2 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r104 = fptoui <2 x double> undef to <2 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r105 = fptosi <2 x double> undef to <2 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r106 = fptoui <2 x double> undef to <2 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r107 = fptosi <2 x double> undef to <2 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r108 = fptoui <2 x double> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r109 = fptosi <2 x double> undef to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r110 = fptoui <4 x float> undef to <4 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %r111 = fptosi <4 x float> undef to <4 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r112 = fptoui <4 x float> undef to <4 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r113 = fptosi <4 x float> undef to <4 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r114 = fptoui <4 x float> undef to <4 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r115 = fptosi <4 x float> undef to <4 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r116 = fptoui <4 x float> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r117 = fptosi <4 x float> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r118 = fptoui <4 x float> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r119 = fptosi <4 x float> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r120 = fptoui <4 x double> undef to <4 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r121 = fptosi <4 x double> undef to <4 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r122 = fptoui <4 x double> undef to <4 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r123 = fptosi <4 x double> undef to <4 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r124 = fptoui <4 x double> undef to <4 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %r125 = fptosi <4 x double> undef to <4 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %r126 = fptoui <4 x double> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %r127 = fptosi <4 x double> undef to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r128 = fptoui <4 x double> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r129 = fptosi <4 x double> undef to <4 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r130 = fptoui <8 x float> undef to <8 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %r131 = fptosi <8 x float> undef to <8 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r132 = fptoui <8 x float> undef to <8 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r133 = fptosi <8 x float> undef to <8 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r134 = fptoui <8 x float> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r135 = fptosi <8 x float> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r136 = fptoui <8 x float> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r137 = fptosi <8 x float> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r138 = fptoui <8 x float> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r139 = fptosi <8 x float> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r140 = fptoui <8 x double> undef to <8 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r141 = fptosi <8 x double> undef to <8 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r142 = fptoui <8 x double> undef to <8 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r143 = fptosi <8 x double> undef to <8 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r144 = fptoui <8 x double> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %r145 = fptosi <8 x double> undef to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r146 = fptoui <8 x double> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %r147 = fptosi <8 x double> undef to <8 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r148 = fptoui <8 x double> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r149 = fptosi <8 x double> undef to <8 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r150 = fptoui <16 x float> undef to <16 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %r151 = fptosi <16 x float> undef to <16 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r152 = fptoui <16 x float> undef to <16 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r153 = fptosi <16 x float> undef to <16 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r154 = fptoui <16 x float> undef to <16 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r155 = fptosi <16 x float> undef to <16 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r156 = fptoui <16 x float> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r157 = fptosi <16 x float> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 263 for instruction: %r158 = fptoui <16 x float> undef to <16 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 263 for instruction: %r159 = fptosi <16 x float> undef to <16 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r160 = fptoui <16 x double> undef to <16 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r161 = fptosi <16 x double> undef to <16 x i1> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r162 = fptoui <16 x double> undef to <16 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r163 = fptosi <16 x double> undef to <16 x i8> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r164 = fptoui <16 x double> undef to <16 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 135 for instruction: %r165 = fptosi <16 x double> undef to <16 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r166 = fptoui <16 x double> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %r167 = fptosi <16 x double> undef to <16 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 263 for instruction: %r168 = fptoui <16 x double> undef to <16 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 263 for instruction: %r169 = fptosi <16 x double> undef to <16 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %r170 = uitofp <2 x i1> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %r171 = sitofp <2 x i1> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r172 = uitofp <2 x i8> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r173 = sitofp <2 x i8> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r174 = uitofp <2 x i16> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r175 = sitofp <2 x i16> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r176 = uitofp <2 x i32> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r177 = sitofp <2 x i32> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %r178 = uitofp <2 x i64> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %r179 = sitofp <2 x i64> undef to <2 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r180 = uitofp <2 x i1> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r181 = sitofp <2 x i1> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r182 = uitofp <2 x i8> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r183 = sitofp <2 x i8> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r184 = uitofp <2 x i16> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r185 = sitofp <2 x i16> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r186 = uitofp <2 x i32> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r187 = sitofp <2 x i32> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %r188 = uitofp <2 x i64> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %r189 = sitofp <2 x i64> undef to <2 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r190 = uitofp <4 x i1> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r191 = sitofp <4 x i1> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r192 = uitofp <4 x i8> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r193 = sitofp <4 x i8> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r194 = uitofp <4 x i16> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r195 = sitofp <4 x i16> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r196 = uitofp <4 x i32> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r197 = sitofp <4 x i32> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %r198 = uitofp <4 x i64> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %r199 = sitofp <4 x i64> undef to <4 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %r200 = uitofp <4 x i1> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %r201 = sitofp <4 x i1> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %r202 = uitofp <4 x i8> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %r203 = sitofp <4 x i8> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r204 = uitofp <4 x i16> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r205 = sitofp <4 x i16> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %r206 = uitofp <4 x i32> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %r207 = sitofp <4 x i32> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %r208 = uitofp <4 x i64> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %r209 = sitofp <4 x i64> undef to <4 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r210 = uitofp <8 x i1> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r211 = sitofp <8 x i1> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r212 = uitofp <8 x i8> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %r213 = sitofp <8 x i8> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r214 = uitofp <8 x i16> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r215 = sitofp <8 x i16> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r216 = uitofp <8 x i32> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r217 = sitofp <8 x i32> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 115 for instruction: %r218 = uitofp <8 x i64> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 115 for instruction: %r219 = sitofp <8 x i64> undef to <8 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %r220 = uitofp <8 x i1> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %r221 = sitofp <8 x i1> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %r222 = uitofp <8 x i8> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %r223 = sitofp <8 x i8> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r224 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r225 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r226 = uitofp <8 x i16> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r227 = sitofp <8 x i16> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %r228 = uitofp <8 x i64> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %r229 = sitofp <8 x i64> undef to <8 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r230 = uitofp <16 x i1> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r231 = sitofp <16 x i1> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r232 = uitofp <16 x i8> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %r233 = sitofp <16 x i8> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r234 = uitofp <16 x i16> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %r235 = sitofp <16 x i16> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r236 = uitofp <16 x i32> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r237 = sitofp <16 x i32> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 231 for instruction: %r238 = uitofp <16 x i64> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 231 for instruction: %r239 = sitofp <16 x i64> undef to <16 x float> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %r240 = uitofp <16 x i1> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %r241 = sitofp <16 x i1> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %r242 = uitofp <16 x i8> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %r243 = sitofp <16 x i8> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r244 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r245 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r246 = uitofp <16 x i16> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %r247 = sitofp <16 x i16> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 199 for instruction: %r248 = uitofp <16 x i64> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 199 for instruction: %r249 = sitofp <16 x i64> undef to <16 x double> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; -- scalars -- %r0 = sext i1 undef to i8 @@ -911,6 +1715,114 @@ define i32 @load_extends() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v10 = sext <2 x i32> %loadv2i32 to <2 x i64> ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v11 = zext <2 x i32> %loadv2i32 to <2 x i64> ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-MAIN-LABEL: 'load_extends' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi8 = load i8, i8* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi16 = load i16, i16* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi32 = load i32, i32* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i8 = load <2 x i8>, <2 x i8>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv4i8 = load <4 x i8>, <4 x i8>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %loadv8i8 = load <8 x i8>, <8 x i8>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i16 = load <2 x i16>, <2 x i16>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv4i16 = load <4 x i16>, <4 x i16>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i32 = load <2 x i32>, <2 x i32>* undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r0 = sext i8 %loadi8 to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext i8 %loadi8 to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext i8 %loadi8 to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r3 = zext i8 %loadi8 to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i8 %loadi8 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i8 %loadi8 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r6 = sext i16 %loadi16 to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = zext i16 %loadi16 to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = sext i16 %loadi16 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = zext i16 %loadi16 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = sext i32 %loadi32 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = zext i32 %loadi32 to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = sext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = zext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = sext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = zext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v4 = sext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v5 = zext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v6 = sext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = zext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %v8 = sext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v9 = zext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v10 = sext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v11 = zext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-BASE-LABEL: 'load_extends' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi8 = load i8, i8* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi16 = load i16, i16* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi32 = load i32, i32* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i8 = load <2 x i8>, <2 x i8>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv4i8 = load <4 x i8>, <4 x i8>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %loadv8i8 = load <8 x i8>, <8 x i8>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i16 = load <2 x i16>, <2 x i16>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %loadv4i16 = load <4 x i16>, <4 x i16>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %loadv2i32 = load <2 x i32>, <2 x i32>* undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r0 = sext i8 %loadi8 to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext i8 %loadi8 to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext i8 %loadi8 to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r3 = zext i8 %loadi8 to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i8 %loadi8 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i8 %loadi8 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r6 = sext i16 %loadi16 to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = zext i16 %loadi16 to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = sext i16 %loadi16 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = zext i16 %loadi16 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = sext i32 %loadi32 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = zext i32 %loadi32 to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = sext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = zext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = sext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = zext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v4 = sext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v5 = zext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v6 = sext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v7 = zext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %v8 = sext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v9 = zext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v10 = sext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %v11 = zext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8R-LABEL: 'load_extends' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi8 = load i8, i8* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi16 = load i16, i16* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadi32 = load i32, i32* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv2i8 = load <2 x i8>, <2 x i8>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv4i8 = load <4 x i8>, <4 x i8>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv8i8 = load <8 x i8>, <8 x i8>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv2i16 = load <2 x i16>, <2 x i16>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv4i16 = load <4 x i16>, <4 x i16>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %loadv2i32 = load <2 x i32>, <2 x i32>* undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r0 = sext i8 %loadi8 to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r1 = zext i8 %loadi8 to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r2 = sext i8 %loadi8 to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r3 = zext i8 %loadi8 to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r4 = sext i8 %loadi8 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r5 = zext i8 %loadi8 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r6 = sext i16 %loadi16 to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %r7 = zext i16 %loadi16 to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r8 = sext i16 %loadi16 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r9 = zext i16 %loadi16 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r10 = sext i32 %loadi32 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %r11 = zext i32 %loadi32 to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = sext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = zext <8 x i8> %loadv8i8 to <8 x i16> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = sext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = zext <4 x i8> %loadv4i8 to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4 = sext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = zext <2 x i8> %loadv2i8 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v6 = sext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v7 = zext <4 x i16> %loadv4i16 to <4 x i32> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8 = sext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v9 = zext <2 x i16> %loadv2i16 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v10 = sext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v11 = zext <2 x i32> %loadv2i32 to <2 x i64> +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %loadi8 = load i8, i8* undef @@ -952,3 +1864,69 @@ define i32 @load_extends() { ret i32 undef } +define i32 @bitcasts() { +; CHECK-NEON-LABEL: 'bitcasts' +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a = bitcast i32 undef to i32 +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b = bitcast float undef to float +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %c = bitcast i32 undef to float +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d = bitcast float undef to i32 +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %e = bitcast i64 undef to double +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = bitcast double undef to i64 +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %g = bitcast half undef to i16 +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %h = bitcast i16 undef to half +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-MVE-LABEL: 'bitcasts' +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a = bitcast i32 undef to i32 +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b = bitcast float undef to float +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %c = bitcast i32 undef to float +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d = bitcast float undef to i32 +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %e = bitcast i64 undef to double +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = bitcast double undef to i64 +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = bitcast half undef to i16 +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %h = bitcast i16 undef to half +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-MAIN-LABEL: 'bitcasts' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a = bitcast i32 undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b = bitcast float undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %c = bitcast i32 undef to float +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d = bitcast float undef to i32 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %e = bitcast i64 undef to double +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = bitcast double undef to i64 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %g = bitcast half undef to i16 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %h = bitcast i16 undef to half +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-BASE-LABEL: 'bitcasts' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a = bitcast i32 undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b = bitcast float undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %c = bitcast i32 undef to float +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d = bitcast float undef to i32 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %e = bitcast i64 undef to double +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = bitcast double undef to i64 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %g = bitcast half undef to i16 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %h = bitcast i16 undef to half +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8R-LABEL: 'bitcasts' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %a = bitcast i32 undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %b = bitcast float undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %c = bitcast i32 undef to float +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %d = bitcast float undef to i32 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %e = bitcast i64 undef to double +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = bitcast double undef to i64 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %g = bitcast half undef to i16 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %h = bitcast i16 undef to half +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; + %a = bitcast i32 undef to i32 + %b = bitcast float undef to float + %c = bitcast i32 undef to float + %d = bitcast float undef to i32 + %e = bitcast i64 undef to double + %f = bitcast double undef to i64 + %g = bitcast half undef to i16 + %h = bitcast i16 undef to half + ret i32 undef +} diff --git a/llvm/test/Analysis/CostModel/ARM/divrem.ll b/llvm/test/Analysis/CostModel/ARM/divrem.ll index 259981a7dfee..7471a8b495dd 100644 --- a/llvm/test/Analysis/CostModel/ARM/divrem.ll +++ b/llvm/test/Analysis/CostModel/ARM/divrem.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK-NEON ; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE +; RUN: opt -cost-model -analyze -mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R define void @i8() { ; CHECK-NEON-LABEL: 'i8' @@ -24,6 +27,39 @@ define void @i8() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i8 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i8 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i8' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i8 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i8 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i8 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i8 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i8' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i8 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i8 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i8 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i8 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i8' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i8 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i8 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i8 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i8 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = sdiv i8 undef, undef %2 = udiv i8 undef, undef @@ -58,6 +94,39 @@ define void @i16() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i16 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i16 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i16 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i16 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i16 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i16 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i16 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i16 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i16 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i16 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i16 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i16 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i16 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i16 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = sdiv i16 undef, undef %2 = udiv i16 undef, undef @@ -92,6 +161,39 @@ define void @i32() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i32 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i32 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i32 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i32 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i32 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i32 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i32 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i32 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i32 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i32 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = sdiv i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = udiv i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = sdiv i32 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = udiv i32 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i32 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i32 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = sdiv i32 undef, undef %2 = udiv i32 undef, undef @@ -126,6 +228,39 @@ define void @i64() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i64 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i64 undef, 2 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'i64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = sdiv i64 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = udiv i64 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i64 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i64 undef, 2 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'i64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = sdiv i64 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = udiv i64 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i64 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i64 undef, 2 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'i64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = sdiv i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = udiv i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = srem i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = urem i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = sdiv i64 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = udiv i64 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = srem i64 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = urem i64 undef, 2 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = sdiv i64 undef, undef %2 = udiv i64 undef, undef @@ -152,6 +287,27 @@ define void @f16() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv half undef, 0xH4000 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem half undef, 0xH4000 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'f16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = fdiv half undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = frem half undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv half undef, 0xH4000 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem half undef, 0xH4000 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'f16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = fdiv half undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = frem half undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv half undef, 0xH4000 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem half undef, 0xH4000 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'f16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv half undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = frem half undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = fdiv half undef, 0xH4000 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = frem half undef, 0xH4000 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv half undef, undef %2 = frem half undef, undef @@ -174,6 +330,27 @@ define void @f32() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv float undef, 2.000000e+00 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem float undef, 2.000000e+00 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'f32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = fdiv float undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = frem float undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv float undef, 2.000000e+00 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem float undef, 2.000000e+00 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'f32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = fdiv float undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = frem float undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv float undef, 2.000000e+00 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem float undef, 2.000000e+00 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'f32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv float undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = frem float undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = fdiv float undef, 2.000000e+00 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = frem float undef, 2.000000e+00 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv float undef, undef %2 = frem float undef, undef @@ -196,6 +373,27 @@ define void @f64() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = fdiv double undef, 2.000000e+00 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = frem double undef, 2.000000e+00 ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'f64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv double undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = frem double undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = fdiv double undef, 2.000000e+00 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = frem double undef, 2.000000e+00 +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'f64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv double undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = frem double undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = fdiv double undef, 2.000000e+00 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = frem double undef, 2.000000e+00 +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'f64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv double undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = frem double undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = fdiv double undef, 2.000000e+00 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = frem double undef, 2.000000e+00 +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv double undef, undef %2 = frem double undef, undef @@ -242,6 +440,63 @@ define void @vi8() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i8> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i8> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi8' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi8' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi8' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f1 = sdiv <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f2 = udiv <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %e1 = sdiv <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %e2 = udiv <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i8> undef, undef %t2 = udiv <2 x i8> undef, undef @@ -300,6 +555,63 @@ define void @vi16() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i16> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i16> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f1 = sdiv <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f2 = udiv <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i16> undef, undef %t2 = udiv <2 x i16> undef, undef @@ -358,6 +670,63 @@ define void @vi32() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i32> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i32> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f1 = sdiv <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f2 = udiv <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i32> undef, undef %t2 = udiv <2 x i32> undef, undef @@ -416,6 +785,63 @@ define void @vi64() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i64> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i64> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t1 = sdiv <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t2 = udiv <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f1 = sdiv <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f2 = udiv <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f3 = srem <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f4 = urem <4 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e1 = sdiv <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e2 = udiv <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e3 = srem <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e4 = urem <8 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s1 = sdiv <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s2 = udiv <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s3 = srem <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s4 = urem <16 x i64> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t1 = sdiv <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t2 = udiv <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f1 = sdiv <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f2 = udiv <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f3 = srem <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f4 = urem <4 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e1 = sdiv <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e2 = udiv <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e3 = srem <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e4 = urem <8 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s1 = sdiv <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s2 = udiv <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s3 = srem <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s4 = urem <16 x i64> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f1 = sdiv <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f2 = udiv <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i64> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i64> undef, undef %t2 = udiv <2 x i64> undef, undef @@ -454,6 +880,33 @@ define void @vf16() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x half> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x half> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf16' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x half> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf16' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x half> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf16' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x half> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x half> undef, undef %2 = fdiv <2 x half> undef, undef @@ -482,6 +935,33 @@ define void @vf32() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x float> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x float> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf32' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x float> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf32' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x float> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf32' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %1 = fdiv <2 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %2 = fdiv <2 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %3 = fdiv <4 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %4 = fdiv <4 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %5 = fdiv <8 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %6 = fdiv <8 x float> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x float> undef, undef %2 = fdiv <2 x float> undef, undef @@ -510,6 +990,33 @@ define void @vf64() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x double> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x double> undef, undef ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf64' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x double> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf64' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x double> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf64' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = fdiv <2 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %2 = fdiv <2 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = fdiv <4 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = fdiv <4 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = fdiv <8 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %6 = fdiv <8 x double> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x double> undef, undef %2 = fdiv <2 x double> undef, undef @@ -558,6 +1065,63 @@ define void @vi8_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i8> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i8> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi8_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i8> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi8_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i8> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi8_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f1 = sdiv <4 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f2 = udiv <4 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %e1 = sdiv <8 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %e2 = udiv <8 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i8> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i8> undef, %t2 = udiv <2 x i8> undef, @@ -616,6 +1180,63 @@ define void @vi16_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i16> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i16> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi16_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i16> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi16_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i16> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi16_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f1 = sdiv <4 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %f2 = udiv <4 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i16> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i16> undef, %t2 = udiv <2 x i16> undef, @@ -674,6 +1295,63 @@ define void @vi32_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i32> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i32> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi32_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i32> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi32_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t1 = sdiv <2 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %t2 = udiv <2 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t3 = srem <2 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t4 = urem <2 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f1 = sdiv <4 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f2 = udiv <4 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f3 = srem <4 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f4 = urem <4 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e1 = sdiv <8 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %e2 = udiv <8 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e3 = srem <8 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e4 = urem <8 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s1 = sdiv <16 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %s2 = udiv <16 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s3 = srem <16 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s4 = urem <16 x i32> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi32_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f1 = sdiv <4 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f2 = udiv <4 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i32> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i32> undef, %t2 = udiv <2 x i32> undef, @@ -732,6 +1410,63 @@ define void @vi64_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s3 = srem <16 x i64> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 272 for instruction: %s4 = urem <16 x i64> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vi64_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t1 = sdiv <2 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t2 = udiv <2 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f1 = sdiv <4 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f2 = udiv <4 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f3 = srem <4 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f4 = urem <4 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e1 = sdiv <8 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e2 = udiv <8 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e3 = srem <8 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e4 = urem <8 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s1 = sdiv <16 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s2 = udiv <16 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s3 = srem <16 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s4 = urem <16 x i64> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vi64_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t1 = sdiv <2 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t2 = udiv <2 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t3 = srem <2 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %t4 = urem <2 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f1 = sdiv <4 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %f2 = udiv <4 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f3 = srem <4 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %f4 = urem <4 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e1 = sdiv <8 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %e2 = udiv <8 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e3 = srem <8 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %e4 = urem <8 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s1 = sdiv <16 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %s2 = udiv <16 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s3 = srem <16 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %s4 = urem <16 x i64> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vi64_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t1 = sdiv <2 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t2 = udiv <2 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t3 = srem <2 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t4 = urem <2 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f1 = sdiv <4 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f2 = udiv <4 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f3 = srem <4 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %f4 = urem <4 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e1 = sdiv <8 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e2 = udiv <8 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e3 = srem <8 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %e4 = urem <8 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s1 = sdiv <16 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s2 = udiv <16 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s3 = srem <16 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %s4 = urem <16 x i64> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %t1 = sdiv <2 x i64> undef, %t2 = udiv <2 x i64> undef, @@ -770,6 +1505,33 @@ define void @vf16_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x half> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x half> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf16_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x half> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf16_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x half> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf16_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x half> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x half> undef, %2 = fdiv <2 x half> undef, @@ -798,6 +1560,33 @@ define void @vf32_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x float> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x float> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf32_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x float> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf32_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fdiv <2 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = fdiv <2 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = fdiv <4 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = fdiv <4 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %5 = fdiv <8 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = fdiv <8 x float> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf32_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %1 = fdiv <2 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %2 = fdiv <2 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %3 = fdiv <4 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %4 = fdiv <4 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %5 = fdiv <8 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %6 = fdiv <8 x float> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x float> undef, %2 = fdiv <2 x float> undef, @@ -826,6 +1615,33 @@ define void @vf64_2() { ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %5 = fdiv <8 x double> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %6 = fdiv <8 x double> undef, ; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-MAIN-LABEL: 'vf64_2' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x double> undef, +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8M-BASE-LABEL: 'vf64_2' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fdiv <2 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = fdiv <2 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %3 = fdiv <4 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %4 = fdiv <4 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = fdiv <8 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = fdiv <8 x double> undef, +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-V8R-LABEL: 'vf64_2' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = fdiv <2 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %2 = fdiv <2 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = fdiv <4 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = fdiv <4 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %5 = fdiv <8 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %6 = fdiv <8 x double> undef, +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %1 = fdiv <2 x double> undef, %2 = fdiv <2 x double> undef, diff --git a/llvm/test/Analysis/CostModel/ARM/icmps.ll b/llvm/test/Analysis/CostModel/ARM/icmps.ll new file mode 100644 index 000000000000..962ddb499347 --- /dev/null +++ b/llvm/test/Analysis/CostModel/ARM/icmps.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK-MVE +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.main-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN +; RUN: opt -cost-model -analyze -mtriple=thumbv8m.base-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE +; RUN: opt -cost-model -analyze -mtriple=armv8r-none-eabi < %s | FileCheck %s --check-prefix=CHECK-V8R + +define i32 @icmps() { +; CHECK-MVE-LABEL: 'icmps' +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = icmp slt i8 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = icmp ult i16 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = icmp sge i32 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = icmp ne i64 undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %e = icmp slt <16 x i8> undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %f = icmp ult <8 x i16> undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %g = icmp sge <4 x i32> undef, undef +; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-MAIN-LABEL: 'icmps' +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = icmp slt i8 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = icmp ult i16 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = icmp sge i32 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = icmp ne i64 undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %e = icmp slt <16 x i8> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f = icmp ult <8 x i16> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g = icmp sge <4 x i32> undef, undef +; CHECK-V8M-MAIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8M-BASE-LABEL: 'icmps' +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = icmp slt i8 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = icmp ult i16 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = icmp sge i32 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = icmp ne i64 undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %e = icmp slt <16 x i8> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %f = icmp ult <8 x i16> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %g = icmp sge <4 x i32> undef, undef +; CHECK-V8M-BASE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; CHECK-V8R-LABEL: 'icmps' +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %a = icmp slt i8 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %b = icmp ult i16 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %c = icmp sge i32 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %d = icmp ne i64 undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %e = icmp slt <16 x i8> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f = icmp ult <8 x i16> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %g = icmp sge <4 x i32> undef, undef +; CHECK-V8R-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; + %a = icmp slt i8 undef, undef + %b = icmp ult i16 undef, undef + %c = icmp sge i32 undef, undef + %d = icmp ne i64 undef, undef + %e = icmp slt <16 x i8> undef, undef + %f = icmp ult <8 x i16> undef, undef + %g = icmp sge <4 x i32> undef, undef + ret i32 undef +} diff --git a/llvm/test/Analysis/CostModel/ARM/select.ll b/llvm/test/Analysis/CostModel/ARM/select.ll index 7851bdf2e485..df62ff0f09ae 100644 --- a/llvm/test/Analysis/CostModel/ARM/select.ll +++ b/llvm/test/Analysis/CostModel/ARM/select.ll @@ -2,6 +2,7 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-MVE ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=swift | FileCheck %s --check-prefix=CHECK-NEON ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8m.base | FileCheck %s --check-prefix=CHECK-THUMB1 +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv8m.main | FileCheck %s --check-prefix=CHECK-THUMB2 define void @selects() { ; CHECK-MVE-LABEL: 'selects' @@ -96,6 +97,37 @@ define void @selects() { ; CHECK-THUMB1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef ; CHECK-THUMB1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef ; CHECK-THUMB1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-THUMB2-LABEL: 'selects' +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v1 = select i1 undef, i8 undef, i8 undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = select i1 undef, i16 undef, i16 undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v3 = select i1 undef, i32 undef, i32 undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4 = select i1 undef, i64 undef, i64 undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v5 = select i1 undef, float undef, float undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v6 = select i1 undef, double undef, double undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v7 = select <2 x i1> undef, <2 x i8> undef, <2 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8 = select <4 x i1> undef, <4 x i8> undef, <4 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v9 = select <8 x i1> undef, <8 x i8> undef, <8 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v10 = select <16 x i1> undef, <16 x i8> undef, <16 x i8> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v11 = select <2 x i1> undef, <2 x i16> undef, <2 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v12 = select <4 x i1> undef, <4 x i16> undef, <4 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v13 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v13b = select <16 x i1> undef, <16 x i16> undef, <16 x i16> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v14 = select <2 x i1> undef, <2 x i32> undef, <2 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v15 = select <4 x i1> undef, <4 x i32> undef, <4 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v15b = select <8 x i1> undef, <8 x i32> undef, <8 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v15c = select <16 x i1> undef, <16 x i32> undef, <16 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16 = select <2 x i1> undef, <2 x i64> undef, <2 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v17 = select <2 x i1> undef, <2 x float> undef, <2 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v18 = select <4 x i1> undef, <4 x float> undef, <4 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v19 = select <2 x i1> undef, <2 x double> undef, <2 x double> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v20 = select <1 x i1> undef, <1 x i32> undef, <1 x i32> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v21 = select <3 x i1> undef, <3 x float> undef, <3 x float> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %v22 = select <5 x i1> undef, <5 x double> undef, <5 x double> undef +; CHECK-THUMB2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; Scalar values %v1 = select i1 undef, i8 undef, i8 undef -- GitLab From 648fc950833422f863847d9dfd45a4625084319d Mon Sep 17 00:00:00 2001 From: Frederik Gossen Date: Tue, 21 Apr 2020 07:11:10 +0000 Subject: [PATCH 051/910] [MLIR] Use `kernel` as a short hand for `gpu.kernel` attribute. Summary: Use the shortcu `kernel` for the `gpu.kernel` attribute of `gpu.func`. The parser supports this and test cases are easier to read. Differential Revision: https://reviews.llvm.org/D78542 --- mlir/test/Conversion/GPUToSPIRV/builtins.mlir | 32 +++++++++---------- mlir/test/Conversion/GPUToSPIRV/if.mlir | 8 ++--- .../Conversion/GPUToSPIRV/load-store.mlir | 4 +-- mlir/test/Conversion/GPUToSPIRV/loop.mlir | 4 +-- mlir/test/Conversion/GPUToSPIRV/simple.mlir | 6 ++-- mlir/test/Dialect/GPU/all-reduce-max.mlir | 2 +- mlir/test/Dialect/GPU/all-reduce.mlir | 2 +- mlir/test/Dialect/GPU/invalid.mlir | 4 +-- mlir/test/Dialect/GPU/ops.mlir | 4 +-- mlir/test/mlir-vulkan-runner/addf.mlir | 2 +- mlir/test/mlir-vulkan-runner/mulf.mlir | 2 +- mlir/test/mlir-vulkan-runner/subf.mlir | 2 +- mlir/test/mlir-vulkan-runner/time.mlir | 2 +- 13 files changed, 37 insertions(+), 37 deletions(-) diff --git a/mlir/test/Conversion/GPUToSPIRV/builtins.mlir b/mlir/test/Conversion/GPUToSPIRV/builtins.mlir index e41002a71a0a..2a73884c8696 100644 --- a/mlir/test/Conversion/GPUToSPIRV/builtins.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/builtins.mlir @@ -10,8 +10,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 // CHECK: spv.globalVariable [[WORKGROUPID:@.*]] built_in("WorkgroupId") gpu.module @kernels { - gpu.func @builtin_workgroup_id_x() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_id_x() kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESS:%.*]] = spv._address_of [[WORKGROUPID]] // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]] // CHECK-NEXT: {{%.*}} = spv.CompositeExtract [[VEC]]{{\[}}0 : i32{{\]}} @@ -33,8 +33,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 // CHECK: spv.globalVariable [[WORKGROUPID:@.*]] built_in("WorkgroupId") gpu.module @kernels { - gpu.func @builtin_workgroup_id_y() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_id_y() kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESS:%.*]] = spv._address_of [[WORKGROUPID]] // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]] // CHECK-NEXT: {{%.*}} = spv.CompositeExtract [[VEC]]{{\[}}1 : i32{{\]}} @@ -56,8 +56,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 // CHECK: spv.globalVariable [[WORKGROUPID:@.*]] built_in("WorkgroupId") gpu.module @kernels { - gpu.func @builtin_workgroup_id_z() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_id_z() kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESS:%.*]] = spv._address_of [[WORKGROUPID]] // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]] // CHECK-NEXT: {{%.*}} = spv.CompositeExtract [[VEC]]{{\[}}2 : i32{{\]}} @@ -78,8 +78,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 gpu.module @kernels { - gpu.func @builtin_workgroup_size_x() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[32, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_size_x() kernel + attributes {spv.entry_point_abi = {local_size = dense<[32, 1, 1]>: vector<3xi32>}} { // The constant value is obtained from the spv.entry_point_abi. // Note that this ignores the workgroup size specification in gpu.launch. // We may want to define gpu.workgroup_size and convert it to the entry @@ -102,8 +102,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 gpu.module @kernels { - gpu.func @builtin_workgroup_size_y() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_size_y() kernel + attributes {spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { // The constant value is obtained from the spv.entry_point_abi. // CHECK: spv.constant 4 : i32 %0 = "gpu.block_dim"() {dimension = "y"} : () -> index @@ -123,8 +123,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 gpu.module @kernels { - gpu.func @builtin_workgroup_size_z() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { + gpu.func @builtin_workgroup_size_z() kernel + attributes {spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { // The constant value is obtained from the spv.entry_point_abi. // CHECK: spv.constant 1 : i32 %0 = "gpu.block_dim"() {dimension = "z"} : () -> index @@ -145,8 +145,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 // CHECK: spv.globalVariable [[LOCALINVOCATIONID:@.*]] built_in("LocalInvocationId") gpu.module @kernels { - gpu.func @builtin_local_id_x() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_local_id_x() kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESS:%.*]] = spv._address_of [[LOCALINVOCATIONID]] // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]] // CHECK-NEXT: {{%.*}} = spv.CompositeExtract [[VEC]]{{\[}}0 : i32{{\]}} @@ -168,8 +168,8 @@ module attributes {gpu.container_module} { // CHECK-LABEL: spv.module Logical GLSL450 // CHECK: spv.globalVariable [[NUMWORKGROUPS:@.*]] built_in("NumWorkgroups") gpu.module @kernels { - gpu.func @builtin_num_workgroups_x() - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @builtin_num_workgroups_x() kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESS:%.*]] = spv._address_of [[NUMWORKGROUPS]] // CHECK-NEXT: [[VEC:%.*]] = spv.Load "Input" [[ADDRESS]] // CHECK-NEXT: {{%.*}} = spv.CompositeExtract [[VEC]]{{\[}}0 : i32{{\]}} diff --git a/mlir/test/Conversion/GPUToSPIRV/if.mlir b/mlir/test/Conversion/GPUToSPIRV/if.mlir index 8a8aa1c88813..3fefc04fad1a 100644 --- a/mlir/test/Conversion/GPUToSPIRV/if.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/if.mlir @@ -15,8 +15,8 @@ module attributes { gpu.module @kernels { // CHECK-LABEL: @kernel_simple_selection - gpu.func @kernel_simple_selection(%arg2 : memref<10xf32>, %arg3 : i1) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @kernel_simple_selection(%arg2 : memref<10xf32>, %arg3 : i1) kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { %value = constant 0.0 : f32 %i = constant 0 : index @@ -36,8 +36,8 @@ module attributes { } // CHECK-LABEL: @kernel_nested_selection - gpu.func @kernel_nested_selection(%arg3 : memref<10xf32>, %arg4 : memref<10xf32>, %arg5 : i1, %arg6 : i1) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @kernel_nested_selection(%arg3 : memref<10xf32>, %arg4 : memref<10xf32>, %arg5 : i1, %arg6 : i1) kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { %i = constant 0 : index %j = constant 9 : index diff --git a/mlir/test/Conversion/GPUToSPIRV/load-store.mlir b/mlir/test/Conversion/GPUToSPIRV/load-store.mlir index 94f7c650fa0d..acb18e7b16e1 100644 --- a/mlir/test/Conversion/GPUToSPIRV/load-store.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/load-store.mlir @@ -34,8 +34,8 @@ module attributes { // CHECK-SAME: [[ARG4:%.*]]: i32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 4), StorageBuffer>} // CHECK-SAME: [[ARG5:%.*]]: i32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 5), StorageBuffer>} // CHECK-SAME: [[ARG6:%.*]]: i32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 6), StorageBuffer>} - gpu.func @load_store_kernel(%arg0: memref<12x4xf32>, %arg1: memref<12x4xf32>, %arg2: memref<12x4xf32>, %arg3: index, %arg4: index, %arg5: index, %arg6: index) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @load_store_kernel(%arg0: memref<12x4xf32>, %arg1: memref<12x4xf32>, %arg2: memref<12x4xf32>, %arg3: index, %arg4: index, %arg5: index, %arg6: index) kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[ADDRESSWORKGROUPID:%.*]] = spv._address_of [[WORKGROUPIDVAR]] // CHECK: [[WORKGROUPID:%.*]] = spv.Load "Input" [[ADDRESSWORKGROUPID]] // CHECK: [[WORKGROUPIDX:%.*]] = spv.CompositeExtract [[WORKGROUPID]]{{\[}}0 : i32{{\]}} diff --git a/mlir/test/Conversion/GPUToSPIRV/loop.mlir b/mlir/test/Conversion/GPUToSPIRV/loop.mlir index 8adc5e355f08..6f0b209c8ea0 100644 --- a/mlir/test/Conversion/GPUToSPIRV/loop.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/loop.mlir @@ -14,8 +14,8 @@ module attributes { } gpu.module @kernels { - gpu.func @loop_kernel(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { + gpu.func @loop_kernel(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) kernel + attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} { // CHECK: [[LB:%.*]] = spv.constant 4 : i32 %lb = constant 4 : index // CHECK: [[UB:%.*]] = spv.constant 42 : i32 diff --git a/mlir/test/Conversion/GPUToSPIRV/simple.mlir b/mlir/test/Conversion/GPUToSPIRV/simple.mlir index 81b842a11c96..c657d5f68fab 100644 --- a/mlir/test/Conversion/GPUToSPIRV/simple.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/simple.mlir @@ -7,8 +7,8 @@ module attributes {gpu.container_module} { // CHECK-SAME: {{%.*}}: f32 {spv.interface_var_abi = #spv.interface_var_abi<(0, 0), StorageBuffer>} // CHECK-SAME: {{%.*}}: !spv.ptr [0]>, StorageBuffer> {spv.interface_var_abi = #spv.interface_var_abi<(0, 1)>} // CHECK-SAME: spv.entry_point_abi = {local_size = dense<[32, 4, 1]> : vector<3xi32>} - gpu.func @basic_module_structure(%arg0 : f32, %arg1 : memref<12xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { + gpu.func @basic_module_structure(%arg0 : f32, %arg1 : memref<12xf32>) kernel + attributes {spv.entry_point_abi = {local_size = dense<[32, 4, 1]>: vector<3xi32>}} { // CHECK: spv.Return gpu.return } @@ -30,7 +30,7 @@ module attributes {gpu.container_module} { gpu.module @kernels { // expected-error @below {{failed to legalize operation 'gpu.func'}} // expected-remark @below {{match failure: missing 'spv.entry_point_abi' attribute}} - gpu.func @missing_entry_point_abi(%arg0 : f32, %arg1 : memref<12xf32>) attributes {gpu.kernel} { + gpu.func @missing_entry_point_abi(%arg0 : f32, %arg1 : memref<12xf32>) kernel { gpu.return } } diff --git a/mlir/test/Dialect/GPU/all-reduce-max.mlir b/mlir/test/Dialect/GPU/all-reduce-max.mlir index ffd244742b71..9c227a8abfe6 100644 --- a/mlir/test/Dialect/GPU/all-reduce-max.mlir +++ b/mlir/test/Dialect/GPU/all-reduce-max.mlir @@ -6,7 +6,7 @@ module @kernels attributes {gpu.kernel_module} { // CHECK-LABEL: gpu.func @kernel( // CHECK-SAME: [[VAL_0:%.*]]: f32) workgroup([[VAL_1:%.*]] : memref<32xf32, 3>) kernel { - gpu.func @kernel(%arg0 : f32) attributes { gpu.kernel } { + gpu.func @kernel(%arg0 : f32) kernel { // CHECK: [[VAL_2:%.*]] = constant 31 : i32 // CHECK: [[VAL_3:%.*]] = constant 0 : i32 // CHECK: [[VAL_4:%.*]] = constant 0 : index diff --git a/mlir/test/Dialect/GPU/all-reduce.mlir b/mlir/test/Dialect/GPU/all-reduce.mlir index 7af995f9a4a0..94ddf8ceea5a 100644 --- a/mlir/test/Dialect/GPU/all-reduce.mlir +++ b/mlir/test/Dialect/GPU/all-reduce.mlir @@ -6,7 +6,7 @@ module @kernels attributes {gpu.kernel_module} { // CHECK-LABEL: gpu.func @kernel( // CHECK-SAME: [[VAL_0:%.*]]: f32) workgroup([[VAL_1:%.*]] : memref<32xf32, 3>) kernel { - gpu.func @kernel(%arg0 : f32) attributes { gpu.kernel } { + gpu.func @kernel(%arg0 : f32) kernel { // CHECK: [[VAL_2:%.*]] = constant 31 : i32 // CHECK: [[VAL_3:%.*]] = constant 0 : i32 // CHECK: [[VAL_4:%.*]] = constant 0 : index diff --git a/mlir/test/Dialect/GPU/invalid.mlir b/mlir/test/Dialect/GPU/invalid.mlir index 610c1c046e8b..885ad3273d63 100644 --- a/mlir/test/Dialect/GPU/invalid.mlir +++ b/mlir/test/Dialect/GPU/invalid.mlir @@ -158,7 +158,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { gpu.module @kernels { - gpu.func @kernel_1(%arg1 : !llvm<"float*">) attributes { gpu.kernel } { + gpu.func @kernel_1(%arg1 : !llvm<"float*">) kernel { gpu.return } } @@ -177,7 +177,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { gpu.module @kernels { - gpu.func @kernel_1(%arg1 : f32) attributes { gpu.kernel } { + gpu.func @kernel_1(%arg1 : f32) kernel { gpu.return } } diff --git a/mlir/test/Dialect/GPU/ops.mlir b/mlir/test/Dialect/GPU/ops.mlir index 196513b90c62..1cb1b53e077c 100644 --- a/mlir/test/Dialect/GPU/ops.mlir +++ b/mlir/test/Dialect/GPU/ops.mlir @@ -27,7 +27,7 @@ module attributes {gpu.container_module} { } gpu.module @kernels { - gpu.func @kernel_1(%arg0 : f32, %arg1 : memref) attributes {gpu.kernel} { + gpu.func @kernel_1(%arg0 : f32, %arg1 : memref) kernel { %tIdX = "gpu.thread_id"() {dimension = "x"} : () -> (index) %tIdY = "gpu.thread_id"() {dimension = "y"} : () -> (index) %tIdZ = "gpu.thread_id"() {dimension = "z"} : () -> (index) @@ -59,7 +59,7 @@ module attributes {gpu.container_module} { gpu.return } - gpu.func @kernel_2(%arg0: f32, %arg1: memref) attributes {gpu.kernel} { + gpu.func @kernel_2(%arg0: f32, %arg1: memref) kernel { gpu.return } } diff --git a/mlir/test/mlir-vulkan-runner/addf.mlir b/mlir/test/mlir-vulkan-runner/addf.mlir index 4ae375d63c55..2fb3a94a190b 100644 --- a/mlir/test/mlir-vulkan-runner/addf.mlir +++ b/mlir/test/mlir-vulkan-runner/addf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_add(%arg0 : memref<8xf32>, %arg1 : memref<8xf32>, %arg2 : memref<8xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>}} { + attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { %0 = "gpu.block_id"() {dimension = "x"} : () -> index %1 = load %arg0[%0] : memref<8xf32> %2 = load %arg1[%0] : memref<8xf32> diff --git a/mlir/test/mlir-vulkan-runner/mulf.mlir b/mlir/test/mlir-vulkan-runner/mulf.mlir index dc962108cbc3..0da888b6876c 100644 --- a/mlir/test/mlir-vulkan-runner/mulf.mlir +++ b/mlir/test/mlir-vulkan-runner/mulf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_mul(%arg0 : memref<4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<4x4xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>}} { + attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { %x = "gpu.block_id"() {dimension = "x"} : () -> index %y = "gpu.block_id"() {dimension = "y"} : () -> index %1 = load %arg0[%x, %y] : memref<4x4xf32> diff --git a/mlir/test/mlir-vulkan-runner/subf.mlir b/mlir/test/mlir-vulkan-runner/subf.mlir index 82dec1243740..c77a14b2ccf5 100644 --- a/mlir/test/mlir-vulkan-runner/subf.mlir +++ b/mlir/test/mlir-vulkan-runner/subf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_sub(%arg0 : memref<8x4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<8x4x4xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>}} { + attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { %x = "gpu.block_id"() {dimension = "x"} : () -> index %y = "gpu.block_id"() {dimension = "y"} : () -> index %z = "gpu.block_id"() {dimension = "z"} : () -> index diff --git a/mlir/test/mlir-vulkan-runner/time.mlir b/mlir/test/mlir-vulkan-runner/time.mlir index f69b4feec37f..b95452e19f96 100644 --- a/mlir/test/mlir-vulkan-runner/time.mlir +++ b/mlir/test/mlir-vulkan-runner/time.mlir @@ -13,7 +13,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_add(%arg0 : memref<16384xf32>, %arg1 : memref<16384xf32>, %arg2 : memref<16384xf32>) - attributes {gpu.kernel, spv.entry_point_abi = {local_size = dense<[128, 1, 1]>: vector<3xi32>}} { + attributes { spv.entry_point_abi = {local_size = dense<[128, 1, 1]>: vector<3xi32>} } kernel { %bid = "gpu.block_id"() {dimension = "x"} : () -> index %tid = "gpu.thread_id"() {dimension = "x"} : () -> index %cst = constant 128 : index -- GitLab From 0372db05bb1552c2b39fc735f949977e0a863a25 Mon Sep 17 00:00:00 2001 From: Frederik Gossen Date: Tue, 21 Apr 2020 10:16:41 +0000 Subject: [PATCH 052/910] [MLIR] Use nested symbol to identify kernel in `LaunchFuncOp`. Summary: Use a nested symbol to identify the kernel to be invoked by a `LaunchFuncOp` in the GPU dialect. This replaces the two attributes that were used to identify the kernel module and the kernel within seperately. Differential Revision: https://reviews.llvm.org/D78551 --- mlir/include/mlir/Dialect/GPU/GPUOps.td | 14 ++--- mlir/include/mlir/IR/SymbolTable.h | 16 +++++ .../ConvertLaunchFuncToCudaCalls.cpp | 14 ++--- ...ConvertGPULaunchFuncToVulkanLaunchFunc.cpp | 2 +- mlir/lib/Dialect/GPU/IR/GPUDialect.cpp | 40 ++++++------- .../GPUToCUDA/lower-launch-func-to-cuda.mlir | 2 +- mlir/test/Conversion/GPUToSPIRV/builtins.mlir | 16 ++--- mlir/test/Conversion/GPUToSPIRV/if.mlir | 2 +- .../Conversion/GPUToSPIRV/load-store.mlir | 2 +- mlir/test/Conversion/GPUToSPIRV/loop.mlir | 2 +- mlir/test/Conversion/GPUToSPIRV/simple.mlir | 4 +- .../lower-gpu-launch-vulkan-launch.mlir | 2 +- mlir/test/Dialect/GPU/invalid.mlir | 59 +++++++++---------- mlir/test/Dialect/GPU/ops.mlir | 8 +-- mlir/test/Dialect/GPU/outlining.mlir | 8 +-- mlir/test/mlir-vulkan-runner/addf.mlir | 2 +- mlir/test/mlir-vulkan-runner/mulf.mlir | 2 +- mlir/test/mlir-vulkan-runner/subf.mlir | 2 +- mlir/test/mlir-vulkan-runner/time.mlir | 2 +- 19 files changed, 98 insertions(+), 101 deletions(-) diff --git a/mlir/include/mlir/Dialect/GPU/GPUOps.td b/mlir/include/mlir/Dialect/GPU/GPUOps.td index 5d91ff6ac545..342b36badd30 100644 --- a/mlir/include/mlir/Dialect/GPU/GPUOps.td +++ b/mlir/include/mlir/Dialect/GPU/GPUOps.td @@ -334,15 +334,17 @@ def GPU_LaunchFuncOp : GPU_Op<"launch_func">, let extraClassDeclaration = [{ /// The kernel function specified by the operation's `kernel` attribute. - StringRef kernel(); + SymbolRefAttr kernel(); /// The number of operands passed to the kernel function. unsigned getNumKernelOperands(); - /// The name of the kernel module specified by the operation's - /// `kernel_module` attribute. + /// The name of the kernel's containing module. StringRef getKernelModuleName(); + /// The name of the kernel. + StringRef getKernelName(); + /// The i-th operand passed to the kernel function. Value getKernelOperand(unsigned i); @@ -361,12 +363,8 @@ def GPU_LaunchFuncOp : GPU_Op<"launch_func">, friend LogicalResult GPUDialect::verifyOperationAttribute(Operation *, NamedAttribute); - /// The name of the symbolRef attribute specifying the kernel to launch. + /// The name of the symbol reference attribute specifying the kernel to launch. static StringRef getKernelAttrName() { return "kernel"; } - - /// The name of the symbolRef attribute specifying the name of the module - /// containing the kernel to launch. - static StringRef getKernelModuleAttrName() { return "kernel_module"; } }]; let verifier = [{ return ::verify(*this); }]; diff --git a/mlir/include/mlir/IR/SymbolTable.h b/mlir/include/mlir/IR/SymbolTable.h index 6f5c07ef3a41..c61efb066e39 100644 --- a/mlir/include/mlir/IR/SymbolTable.h +++ b/mlir/include/mlir/IR/SymbolTable.h @@ -9,6 +9,7 @@ #ifndef MLIR_IR_SYMBOLTABLE_H #define MLIR_IR_SYMBOLTABLE_H +#include "mlir/IR/Attributes.h" #include "mlir/IR/OpDefinition.h" #include "llvm/ADT/StringMap.h" @@ -106,6 +107,14 @@ public: static Operation *lookupNearestSymbolFrom(Operation *from, StringRef symbol); static Operation *lookupNearestSymbolFrom(Operation *from, SymbolRefAttr symbol); + template + static T lookupNearestSymbolFrom(Operation *from, StringRef symbol) { + return dyn_cast_or_null(lookupNearestSymbolFrom(from, symbol)); + } + template + static T lookupNearestSymbolFrom(Operation *from, SymbolRefAttr symbol) { + return dyn_cast_or_null(lookupNearestSymbolFrom(from, symbol)); + } /// This class represents a specific symbol use. class SymbolUse { @@ -227,6 +236,13 @@ public: template T lookupSymbol(StringRef name) { return dyn_cast_or_null(lookupSymbol(name)); } + Operation *lookupSymbol(SymbolRefAttr symbol) { + return mlir::SymbolTable::lookupSymbolIn(this->getOperation(), symbol); + } + template + T lookupSymbol(SymbolRefAttr symbol) { + return dyn_cast_or_null(lookupSymbol(symbol)); + } }; /// A trait used to define a symbol that can be used on operations within a diff --git a/mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp b/mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp index bdd9bb66f617..cfdcb0f98ade 100644 --- a/mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp +++ b/mlir/lib/Conversion/GPUToCUDA/ConvertLaunchFuncToCudaCalls.cpp @@ -273,14 +273,8 @@ Value GpuLaunchFuncToCudaCallsPass::setupParamsArray(gpu::LaunchFuncOp launchOp, OpBuilder &builder) { // Get the launch target. - auto containingModule = launchOp.getParentOfType(); - if (!containingModule) - return {}; - auto gpuModule = containingModule.lookupSymbol( - launchOp.getKernelModuleName()); - if (!gpuModule) - return {}; - auto gpuFunc = gpuModule.lookupSymbol(launchOp.kernel()); + auto gpuFunc = SymbolTable::lookupNearestSymbolFrom( + launchOp, launchOp.kernel()); if (!gpuFunc) return {}; @@ -416,8 +410,8 @@ void GpuLaunchFuncToCudaCallsPass::translateGpuLaunchCalls( // the kernel function. auto cuOwningModuleRef = builder.create(loc, getPointerType(), cuModule); - auto kernelName = generateKernelNameConstant(launchOp.getKernelModuleName(), - launchOp.kernel(), loc, builder); + auto kernelName = generateKernelNameConstant( + launchOp.getKernelModuleName(), launchOp.getKernelName(), loc, builder); auto cuFunction = allocatePointer(builder, loc); auto cuModuleGetFunction = getOperation().lookupSymbol(cuModuleGetFunctionName); diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp index b33edb92605c..26588049b939 100644 --- a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp +++ b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp @@ -182,7 +182,7 @@ void ConvertGpuLaunchFuncToVulkanLaunchFunc::convertGpuLaunchFunc( // Set entry point name as an attribute. vulkanLaunchCallOp.setAttr( kSPIRVEntryPointAttrName, - StringAttr::get(launchOp.kernel(), loc->getContext())); + StringAttr::get(launchOp.getKernelName(), loc->getContext())); launchOp.erase(); } diff --git a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp index 1474be76c57e..e751107820bc 100644 --- a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp +++ b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp @@ -11,8 +11,10 @@ //===----------------------------------------------------------------------===// #include "mlir/Dialect/GPU/GPUDialect.h" + #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/Dialect/StandardOps/IR/Ops.h" +#include "mlir/IR/Attributes.h" #include "mlir/IR/Builders.h" #include "mlir/IR/Function.h" #include "mlir/IR/FunctionImplementation.h" @@ -62,10 +64,8 @@ LogicalResult GPUDialect::verifyOperationAttribute(Operation *op, // Ignore launch ops with missing attributes here. The errors will be // reported by the verifiers of those ops. - if (!launchOp.getAttrOfType( - LaunchFuncOp::getKernelAttrName()) || - !launchOp.getAttrOfType( - LaunchFuncOp::getKernelModuleAttrName())) + if (!launchOp.getAttrOfType( + LaunchFuncOp::getKernelAttrName())) return success(); // Check that `launch_func` refers to a well-formed GPU kernel module. @@ -76,13 +76,12 @@ LogicalResult GPUDialect::verifyOperationAttribute(Operation *op, << "kernel module '" << kernelModuleName << "' is undefined"; // Check that `launch_func` refers to a well-formed kernel function. - StringRef kernelName = launchOp.kernel(); - Operation *kernelFunc = kernelModule.lookupSymbol(kernelName); + Operation *kernelFunc = module.lookupSymbol(launchOp.kernel()); auto kernelGPUFunction = dyn_cast_or_null(kernelFunc); auto kernelLLVMFunction = dyn_cast_or_null(kernelFunc); if (!kernelGPUFunction && !kernelLLVMFunction) return launchOp.emitOpError("kernel function '") - << kernelName << "' is undefined"; + << launchOp.kernel() << "' is undefined"; if (!kernelFunc->getAttrOfType( GPUDialect::getKernelFuncAttrName())) return launchOp.emitOpError("kernel function is missing the '") @@ -397,11 +396,11 @@ void LaunchFuncOp::build(Builder *builder, OperationState &result, result.addOperands( {gridSizeX, gridSizeY, gridSizeZ, blockSizeX, blockSizeY, blockSizeZ}); result.addOperands(kernelOperands); - result.addAttribute(getKernelAttrName(), - builder->getStringAttr(kernelFunc.getName())); auto kernelModule = kernelFunc.getParentOfType(); - result.addAttribute(getKernelModuleAttrName(), - builder->getSymbolRefAttr(kernelModule.getName())); + auto kernelSymbol = builder->getSymbolRefAttr( + kernelModule.getName(), + {builder->getSymbolRefAttr(kernelFunc.getName())}); + result.addAttribute(getKernelAttrName(), kernelSymbol); } void LaunchFuncOp::build(Builder *builder, OperationState &result, @@ -411,8 +410,8 @@ void LaunchFuncOp::build(Builder *builder, OperationState &result, blockSize.x, blockSize.y, blockSize.z, kernelOperands); } -StringRef LaunchFuncOp::kernel() { - return getAttrOfType(getKernelAttrName()).getValue(); +SymbolRefAttr LaunchFuncOp::kernel() { + return getAttrOfType(getKernelAttrName()); } unsigned LaunchFuncOp::getNumKernelOperands() { @@ -420,10 +419,11 @@ unsigned LaunchFuncOp::getNumKernelOperands() { } StringRef LaunchFuncOp::getKernelModuleName() { - return getAttrOfType(getKernelModuleAttrName()) - .getRootReference(); + return kernel().getRootReference(); } +StringRef LaunchFuncOp::getKernelName() { return kernel().getLeafReference(); } + Value LaunchFuncOp::getKernelOperand(unsigned i) { return getOperation()->getOperand(i + kNumConfigOperands); } @@ -446,16 +446,10 @@ static LogicalResult verify(LaunchFuncOp op) { "expected the closest surrounding module to have the '" + GPUDialect::getContainerModuleAttrName() + "' attribute"); - auto kernelAttr = op.getAttrOfType(op.getKernelAttrName()); + auto kernelAttr = op.getAttrOfType(op.getKernelAttrName()); if (!kernelAttr) - return op.emitOpError("string attribute '" + op.getKernelAttrName() + - "' must be specified"); - - auto kernelModuleAttr = - op.getAttrOfType(op.getKernelModuleAttrName()); - if (!kernelModuleAttr) return op.emitOpError("symbol reference attribute '" + - op.getKernelModuleAttrName() + "' must be specified"); + op.getKernelAttrName() + "' must be specified"); return success(); } diff --git a/mlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir b/mlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir index 17244ce9f066..20b76a2e3a29 100644 --- a/mlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir +++ b/mlir/test/Conversion/GPUToCUDA/lower-launch-func-to-cuda.mlir @@ -27,7 +27,7 @@ module attributes {gpu.container_module} { // CHECK: llvm.call @mcuGetStreamHelper // CHECK: llvm.call @mcuLaunchKernel // CHECK: llvm.call @mcuStreamSynchronize - "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = "kernel", kernel_module = @kernel_module } + "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = @kernel_module::@kernel } : (!llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.i64, !llvm.float, !llvm<"float*">) -> () llvm.return diff --git a/mlir/test/Conversion/GPUToSPIRV/builtins.mlir b/mlir/test/Conversion/GPUToSPIRV/builtins.mlir index 2a73884c8696..84afa22ecae3 100644 --- a/mlir/test/Conversion/GPUToSPIRV/builtins.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/builtins.mlir @@ -3,7 +3,7 @@ module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_id_x", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_id_x} : (index, index, index, index, index, index) -> () return } @@ -26,7 +26,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_id_y", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_id_y} : (index, index, index, index, index, index) -> () return } @@ -49,7 +49,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_id_z", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_id_z} : (index, index, index, index, index, index) -> () return } @@ -72,7 +72,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_size_x", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_size_x} : (index, index, index, index, index, index) -> () return } @@ -96,7 +96,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_size_y", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_size_y} : (index, index, index, index, index, index) -> () return } @@ -117,7 +117,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_workgroup_size_z", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_workgroup_size_z} : (index, index, index, index, index, index) -> () return } @@ -138,7 +138,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_local_id_x", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_local_id_x} : (index, index, index, index, index, index) -> () return } @@ -161,7 +161,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { func @builtin() { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = "builtin_num_workgroups_x", kernel_module = @kernels} : (index, index, index, index, index, index) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0) {kernel = @kernels::@builtin_num_workgroups_x} : (index, index, index, index, index, index) -> () return } diff --git a/mlir/test/Conversion/GPUToSPIRV/if.mlir b/mlir/test/Conversion/GPUToSPIRV/if.mlir index 3fefc04fad1a..8a637457884e 100644 --- a/mlir/test/Conversion/GPUToSPIRV/if.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/if.mlir @@ -9,7 +9,7 @@ module attributes { } { func @main(%arg0 : memref<10xf32>, %arg1 : i1) { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0, %arg0, %arg1) { kernel = "kernel_simple_selection", kernel_module = @kernels} : (index, index, index, index, index, index, memref<10xf32>, i1) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0, %arg0, %arg1) { kernel = @kernels::@kernel_simple_selection} : (index, index, index, index, index, index, memref<10xf32>, i1) -> () return } diff --git a/mlir/test/Conversion/GPUToSPIRV/load-store.mlir b/mlir/test/Conversion/GPUToSPIRV/load-store.mlir index acb18e7b16e1..077a1c0c7879 100644 --- a/mlir/test/Conversion/GPUToSPIRV/load-store.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/load-store.mlir @@ -17,7 +17,7 @@ module attributes { %1 = subi %c4, %c0_0 : index %c1_1 = constant 1 : index %c1_2 = constant 1 : index - "gpu.launch_func"(%0, %c1_2, %c1_2, %1, %c1_2, %c1_2, %arg0, %arg1, %arg2, %c0, %c0_0, %c1, %c1_1) {kernel = "load_store_kernel", kernel_module = @kernels} : (index, index, index, index, index, index, memref<12x4xf32>, memref<12x4xf32>, memref<12x4xf32>, index, index, index, index) -> () + "gpu.launch_func"(%0, %c1_2, %c1_2, %1, %c1_2, %c1_2, %arg0, %arg1, %arg2, %c0, %c0_0, %c1, %c1_1) {kernel = @kernels::@load_store_kernel} : (index, index, index, index, index, index, memref<12x4xf32>, memref<12x4xf32>, memref<12x4xf32>, index, index, index, index) -> () return } diff --git a/mlir/test/Conversion/GPUToSPIRV/loop.mlir b/mlir/test/Conversion/GPUToSPIRV/loop.mlir index 6f0b209c8ea0..56bff8a3985b 100644 --- a/mlir/test/Conversion/GPUToSPIRV/loop.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/loop.mlir @@ -9,7 +9,7 @@ module attributes { } { func @loop(%arg0 : memref<10xf32>, %arg1 : memref<10xf32>) { %c0 = constant 1 : index - "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0, %arg0, %arg1) { kernel = "loop_kernel", kernel_module = @kernels} : (index, index, index, index, index, index, memref<10xf32>, memref<10xf32>) -> () + "gpu.launch_func"(%c0, %c0, %c0, %c0, %c0, %c0, %arg0, %arg1) { kernel = @kernels::@loop_kernel} : (index, index, index, index, index, index, memref<10xf32>, memref<10xf32>) -> () return } diff --git a/mlir/test/Conversion/GPUToSPIRV/simple.mlir b/mlir/test/Conversion/GPUToSPIRV/simple.mlir index c657d5f68fab..f68823321568 100644 --- a/mlir/test/Conversion/GPUToSPIRV/simple.mlir +++ b/mlir/test/Conversion/GPUToSPIRV/simple.mlir @@ -18,7 +18,7 @@ module attributes {gpu.container_module} { %0 = "op"() : () -> (f32) %1 = "op"() : () -> (memref<12xf32>) %cst = constant 1 : index - "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = "basic_module_structure", kernel_module = @kernels } + "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = @kernels::@basic_module_structure } : (index, index, index, index, index, index, f32, memref<12xf32>) -> () return } @@ -39,7 +39,7 @@ module attributes {gpu.container_module} { %0 = "op"() : () -> (f32) %1 = "op"() : () -> (memref<12xf32>) %cst = constant 1 : index - "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = "missing_entry_point_abi", kernel_module = @kernels } + "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) { kernel = @kernels::@missing_entry_point_abi } : (index, index, index, index, index, index, f32, memref<12xf32>) -> () return } diff --git a/mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir b/mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir index 30dc3a478036..726b276010ef 100644 --- a/mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir +++ b/mlir/test/Conversion/GPUToVulkan/lower-gpu-launch-vulkan-launch.mlir @@ -26,7 +26,7 @@ module attributes {gpu.container_module} { func @foo() { %0 = alloc() : memref<12xf32> %c1 = constant 1 : index - "gpu.launch_func"(%c1, %c1, %c1, %c1, %c1, %c1, %0) {kernel = "kernel", kernel_module = @kernels} : (index, index, index, index, index, index, memref<12xf32>) -> () + "gpu.launch_func"(%c1, %c1, %c1, %c1, %c1, %c1, %0) {kernel = @kernels::@kernel} : (index, index, index, index, index, index, memref<12xf32>) -> () return } } diff --git a/mlir/test/Dialect/GPU/invalid.mlir b/mlir/test/Dialect/GPU/invalid.mlir index 885ad3273d63..be02dec83913 100644 --- a/mlir/test/Dialect/GPU/invalid.mlir +++ b/mlir/test/Dialect/GPU/invalid.mlir @@ -54,7 +54,7 @@ func @launch_func_missing_parent_module_attribute(%sz : index) { module attributes {gpu.container_module} { func @launch_func_missing_callee_attribute(%sz : index) { - // expected-error@+1 {{string attribute 'kernel' must be specified}} + // expected-error@+1 {{symbol reference attribute 'kernel' must be specified}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) {foo = "bar"} : (index, index, index, index, index, index) -> () return @@ -63,20 +63,9 @@ module attributes {gpu.container_module} { // ----- -module attributes {gpu.container_module} { - func @launch_func_missing_module_attribute(%sz : index) { - // expected-error@+1 {{attribute 'kernel_module' must be specified}} - "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) {kernel = "launch_func_missing_kernel_attr"} - : (index, index, index, index, index, index) -> () - return - } -} - -// ----- - module attributes {gpu.container_module} { func @launch_func_no_function_attribute(%sz : index) { - // expected-error@+1 {{string attribute 'kernel' must be specified}} + // expected-error@+1 {{symbol reference attribute 'kernel' must be specified}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) {kernel = 10} : (index, index, index, index, index, index) -> () return @@ -85,23 +74,11 @@ module attributes {gpu.container_module} { // ----- -module attributes {gpu.container_module} { - func @launch_func_module_attribute_wrong_type(%sz : index) { - // expected-error@+1 {{symbol reference attribute 'kernel_module' must be specified}} - "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) - {kernel = "launch_func_module_attribute_wrong_type", kernel_module = 10} - : (index, index, index, index, index, index) -> () - return - } -} - -// ----- - module attributes {gpu.container_module} { func @launch_func_undefined_module(%sz : index) { // expected-error@+1 {{kernel module 'kernels' is undefined}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) - { kernel = "kernel_1", kernel_module = @kernels } + { kernel = @kernels::@kernel_1 } : (index, index, index, index, index, index) -> () return } @@ -116,7 +93,7 @@ module attributes {gpu.container_module} { func @launch_func_missing_module_attribute(%sz : index) { // expected-error@+1 {{kernel module 'kernels' is undefined}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) - { kernel = "kernel_1", kernel_module = @kernels } + { kernel = @kernels::@kernel_1 } : (index, index, index, index, index, index) -> () return } @@ -128,9 +105,9 @@ module attributes {gpu.container_module} { gpu.module @kernels { } func @launch_func_undefined_function(%sz : index) { - // expected-error@+1 {{kernel function 'kernel_1' is undefined}} + // expected-error@+1 {{kernel function '@kernels::@kernel_1' is undefined}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz) - { kernel = "kernel_1", kernel_module = @kernels } + { kernel = @kernels::@kernel_1 } : (index, index, index, index, index, index) -> () return } @@ -138,6 +115,24 @@ module attributes {gpu.container_module} { // ----- +module attributes {gpu.container_module} { + module @kernels { + gpu.func @kernel_1(%arg1 : !llvm<"float*">) kernel { + gpu.return + } + } + + func @launch_func_missing_kernel_attr(%sz : index, %arg : !llvm<"float*">) { + // expected-error@+1 {{kernel module 'kernels' is undefined}} + "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz, %arg) + {kernel = @kernels::@kernel_1} + : (index, index, index, index, index, index, !llvm<"float*">) -> () + return + } +} + +// ----- + module attributes {gpu.container_module} { gpu.module @kernels { gpu.func @kernel_1(%arg1 : !llvm<"float*">) { @@ -148,7 +143,7 @@ module attributes {gpu.container_module} { func @launch_func_missing_kernel_attr(%sz : index, %arg : !llvm<"float*">) { // expected-error@+1 {{kernel function is missing the 'gpu.kernel' attribute}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz, %arg) - {kernel = "kernel_1", kernel_module = @kernels} + {kernel = @kernels::@kernel_1} : (index, index, index, index, index, index, !llvm<"float*">) -> () return } @@ -166,7 +161,7 @@ module attributes {gpu.container_module} { func @launch_func_kernel_operand_size(%sz : index, %arg : !llvm<"float*">) { // expected-error@+1 {{got 2 kernel operands but expected 1}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz, %arg, %arg) - {kernel = "kernel_1", kernel_module = @kernels} + {kernel = @kernels::@kernel_1} : (index, index, index, index, index, index, !llvm<"float*">, !llvm<"float*">) -> () return @@ -185,7 +180,7 @@ module attributes {gpu.container_module} { func @launch_func_kernel_operand_types(%sz : index, %arg : f32) { // expected-err@+1 {{type of function argument 0 does not match}} "gpu.launch_func"(%sz, %sz, %sz, %sz, %sz, %sz, %arg) - {kernel = "kernel_1", kernel_module = @kernels} + {kernel = @kernels::@kernel_1} : (index, index, index, index, index, index, f32) -> () return } diff --git a/mlir/test/Dialect/GPU/ops.mlir b/mlir/test/Dialect/GPU/ops.mlir index 1cb1b53e077c..f500d7173f71 100644 --- a/mlir/test/Dialect/GPU/ops.mlir +++ b/mlir/test/Dialect/GPU/ops.mlir @@ -70,14 +70,14 @@ module attributes {gpu.container_module} { // CHECK: %{{.*}} = constant 8 %cst = constant 8 : index - // CHECK: "gpu.launch_func"(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {kernel = "kernel_1", kernel_module = @kernels} : (index, index, index, index, index, index, f32, memref) -> () + // CHECK: "gpu.launch_func"(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {kernel = @kernels::@kernel_1} : (index, index, index, index, index, index, f32, memref) -> () "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) - { kernel = "kernel_1", kernel_module = @kernels } + { kernel = @kernels::@kernel_1} : (index, index, index, index, index, index, f32, memref) -> () - // CHECK: "gpu.launch_func"(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {kernel = "kernel_2", kernel_module = @kernels} : (index, index, index, index, index, index, f32, memref) -> () + // CHECK: "gpu.launch_func"(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}) {kernel = @kernels::@kernel_2} : (index, index, index, index, index, index, f32, memref) -> () "gpu.launch_func"(%cst, %cst, %cst, %cst, %cst, %cst, %0, %1) - { kernel = "kernel_2", kernel_module = @kernels } + { kernel = @kernels::@kernel_2} : (index, index, index, index, index, index, f32, memref) -> () return diff --git a/mlir/test/Dialect/GPU/outlining.mlir b/mlir/test/Dialect/GPU/outlining.mlir index 0d8734716a47..d15f10fd75ec 100644 --- a/mlir/test/Dialect/GPU/outlining.mlir +++ b/mlir/test/Dialect/GPU/outlining.mlir @@ -21,7 +21,7 @@ func @launch() { // CHECK: %[[BDIMZ:.*]] = constant 28 %bDimZ = constant 28 : index - // CHECK: "gpu.launch_func"(%[[GDIMX]], %[[GDIMY]], %[[GDIMZ]], %[[BDIMX]], %[[BDIMY]], %[[BDIMZ]], %[[ARG0]], %[[ARG1]]) {kernel = "launch_kernel", kernel_module = @launch_kernel} : (index, index, index, index, index, index, f32, memref) -> () + // CHECK: "gpu.launch_func"(%[[GDIMX]], %[[GDIMY]], %[[GDIMZ]], %[[BDIMX]], %[[BDIMY]], %[[BDIMZ]], %[[ARG0]], %[[ARG1]]) {kernel = @launch_kernel::@launch_kernel} : (index, index, index, index, index, index, f32, memref) -> () // CHECK-NOT: gpu.launch blocks gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %gDimX, %grid_y = %gDimY, %grid_z = %gDimZ) @@ -64,14 +64,14 @@ func @launch() { func @multiple_launches() { // CHECK: %[[CST:.*]] = constant 8 : index %cst = constant 8 : index - // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]]) {kernel = "multiple_launches_kernel", kernel_module = @multiple_launches_kernel} : (index, index, index, index, index, index) -> () + // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]]) {kernel = @multiple_launches_kernel::@multiple_launches_kernel} : (index, index, index, index, index, index) -> () gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %cst, %grid_y = %cst, %grid_z = %cst) threads(%tx, %ty, %tz) in (%block_x = %cst, %block_y = %cst, %block_z = %cst) { gpu.terminator } - // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]]) {kernel = "multiple_launches_kernel", kernel_module = @multiple_launches_kernel_0} : (index, index, index, index, index, index) -> () + // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]]) {kernel = @multiple_launches_kernel_0::@multiple_launches_kernel} : (index, index, index, index, index, index) -> () gpu.launch blocks(%bx2, %by2, %bz2) in (%grid_x2 = %cst, %grid_y2 = %cst, %grid_z2 = %cst) threads(%tx2, %ty2, %tz2) in (%block_x2 = %cst, %block_y2 = %cst, @@ -93,7 +93,7 @@ func @extra_constants(%arg0 : memref) { %cst = constant 8 : index %cst2 = constant 2 : index %cst3 = dim %arg0, 0 : memref - // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %{{.*}}) {kernel = "extra_constants_kernel", kernel_module = @extra_constants_kernel} : (index, index, index, index, index, index, memref) -> () + // CHECK: "gpu.launch_func"(%[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %[[CST]], %{{.*}}) {kernel = @extra_constants_kernel::@extra_constants_kernel} : (index, index, index, index, index, index, memref) -> () gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %cst, %grid_y = %cst, %grid_z = %cst) threads(%tx, %ty, %tz) in (%block_x = %cst, %block_y = %cst, diff --git a/mlir/test/mlir-vulkan-runner/addf.mlir b/mlir/test/mlir-vulkan-runner/addf.mlir index 2fb3a94a190b..3ba86ef89119 100644 --- a/mlir/test/mlir-vulkan-runner/addf.mlir +++ b/mlir/test/mlir-vulkan-runner/addf.mlir @@ -39,7 +39,7 @@ module attributes { %cst1 = constant 1 : index %cst8 = constant 8 : index - "gpu.launch_func"(%cst8, %cst1, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = "kernel_add", kernel_module = @kernels } + gpu.launch_func"(%cst8, %cst1, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_add } : (index, index, index, index, index, index, memref<8xf32>, memref<8xf32>, memref<8xf32>) -> () %arg6 = memref_cast %arg5 : memref to memref<*xf32> call @print_memref_f32(%arg6) : (memref<*xf32>) -> () diff --git a/mlir/test/mlir-vulkan-runner/mulf.mlir b/mlir/test/mlir-vulkan-runner/mulf.mlir index 0da888b6876c..89175e803d98 100644 --- a/mlir/test/mlir-vulkan-runner/mulf.mlir +++ b/mlir/test/mlir-vulkan-runner/mulf.mlir @@ -40,7 +40,7 @@ module attributes { %cst1 = constant 1 : index %cst4 = constant 4 : index - "gpu.launch_func"(%cst4, %cst4, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = "kernel_mul", kernel_module = @kernels } + "gpu.launch_func"(%cst4, %cst4, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_mul } : (index, index, index, index, index, index, memref<4x4xf32>, memref<4x4xf32>, memref<4x4xf32>) -> () %arg6 = memref_cast %arg5 : memref to memref<*xf32> call @print_memref_f32(%arg6) : (memref<*xf32>) -> () diff --git a/mlir/test/mlir-vulkan-runner/subf.mlir b/mlir/test/mlir-vulkan-runner/subf.mlir index c77a14b2ccf5..b41094653d97 100644 --- a/mlir/test/mlir-vulkan-runner/subf.mlir +++ b/mlir/test/mlir-vulkan-runner/subf.mlir @@ -42,7 +42,7 @@ module attributes { %cst1 = constant 1 : index %cst4 = constant 4 : index %cst8 = constant 8 : index - "gpu.launch_func"(%cst8, %cst4, %cst4, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = "kernel_sub", kernel_module = @kernels } + "gpu.launch_func"(%cst8, %cst4, %cst4, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_sub } : (index, index, index, index, index, index, memref<8x4x4xf32>, memref<4x4xf32>, memref<8x4x4xf32>) -> () %arg6 = memref_cast %arg5 : memref to memref<*xf32> call @print_memref_f32(%arg6) : (memref<*xf32>) -> () diff --git a/mlir/test/mlir-vulkan-runner/time.mlir b/mlir/test/mlir-vulkan-runner/time.mlir index b95452e19f96..ffa8985d488f 100644 --- a/mlir/test/mlir-vulkan-runner/time.mlir +++ b/mlir/test/mlir-vulkan-runner/time.mlir @@ -46,7 +46,7 @@ module attributes { %cst1 = constant 1 : index %cst128 = constant 128 : index - "gpu.launch_func"(%cst128, %cst1, %cst1, %cst128, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = "kernel_add", kernel_module = @kernels } + "gpu.launch_func"(%cst128, %cst1, %cst1, %cst128, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_add } : (index, index, index, index, index, index, memref<16384xf32>, memref<16384xf32>, memref<16384xf32>) -> () %arg6 = memref_cast %arg5 : memref to memref<*xf32> return -- GitLab From 2fa17cdd7ad04fe17f97a726e57e79bd0a1d4852 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 21 Apr 2020 11:50:49 +0100 Subject: [PATCH 053/910] [AMDGPU] Simplify definition of VReg and AReg classes. NFC. Differential Revision: https://reviews.llvm.org/D78553 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 110 +++++------------------ 1 file changed, 24 insertions(+), 86 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 92d0cd7363e5..32a4cd60f0ae 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -725,99 +725,37 @@ def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, } // Register class for all vector registers (VGPRs + Interploation Registers) -def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 32, - (add VGPR_64)> { - let Size = 64; +class VRegClass regTypes, dag regList> : + RegisterClass<"AMDGPU", regTypes, 32, regList> { + let Size = !mul(numRegs, 32); - // Requires 2 v_mov_b32 to copy - let CopyCost = 2; - let AllocationPriority = 2; - let Weight = 2; + // Requires n v_mov_b32 to copy + let CopyCost = numRegs; + let AllocationPriority = numRegs; + let Weight = numRegs; } -def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96)> { - let Size = 96; +def VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], + (add VGPR_64)>; +def VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; +def VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, i128], (add VGPR_128)>; +def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; +def VReg_256 : VRegClass<8, [v8i32, v8f32], (add VGPR_256)>; +def VReg_512 : VRegClass<16, [v16i32, v16f32], (add VGPR_512)>; +def VReg_1024 : VRegClass<32, [v32i32, v32f32], (add VGPR_1024)>; - // Requires 3 v_mov_b32 to copy - let CopyCost = 3; - let AllocationPriority = 3; - let Weight = 3; +class ARegClass regTypes, dag regList> : + VRegClass { + // Requires n v_accvgpr_write and n v_accvgpr_read to copy + burn 1 vgpr + let CopyCost = !add(numRegs, numRegs, 1); } -def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64, i128], 32, - (add VGPR_128)> { - let Size = 128; +def AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], + (add AGPR_64)>; +def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>; +def AReg_512 : ARegClass<16, [v16i32, v16f32], (add AGPR_512)>; +def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>; - // Requires 4 v_mov_b32 to copy - let CopyCost = 4; - let AllocationPriority = 4; - let Weight = 4; -} - -def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, - (add VGPR_160)> { - let Size = 160; - - // Requires 5 v_mov_b32 to copy - let CopyCost = 5; - let AllocationPriority = 5; - let Weight = 5; -} - -def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, - (add VGPR_256)> { - let Size = 256; - let CopyCost = 8; - let AllocationPriority = 6; - let Weight = 8; -} - -def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, - (add VGPR_512)> { - let Size = 512; - let CopyCost = 16; - let AllocationPriority = 7; - let Weight = 16; -} - -def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, - (add VGPR_1024)> { - let Size = 1024; - let CopyCost = 32; - let AllocationPriority = 8; - let Weight = 32; -} - -def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, - (add AGPR_64)> { - let Size = 64; - - let CopyCost = 5; - let AllocationPriority = 2; -} - -def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, - (add AGPR_128)> { - let Size = 128; - - // Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr - let CopyCost = 9; - let AllocationPriority = 4; -} - -def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, - (add AGPR_512)> { - let Size = 512; - let CopyCost = 33; - let AllocationPriority = 7; -} - -def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, - (add AGPR_1024)> { - let Size = 1024; - let CopyCost = 65; - let AllocationPriority = 8; -} } // End GeneratePressureSet = 0 // This is not a real register. This is just to have a register to add -- GitLab From 7318625674b7a293fd5645e463e3a4abe81150c0 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 22 Apr 2020 09:05:24 +0100 Subject: [PATCH 054/910] [AMDGPU] Remove obsolete special case for 1024-bit vector types. NFC. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 1bdd2ed8111c..e4fe2e527c3e 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10665,8 +10665,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, break; case 1024: RC = &AMDGPU::AReg_1024RegClass; - // v32 types are not legal but we support them here. - return std::make_pair(0U, RC); + break; } break; } -- GitLab From 35cf2f42dda4d708741e06570b2dbe91cec4dc41 Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Wed, 22 Apr 2020 08:49:02 +0100 Subject: [PATCH 055/910] [Driver][docs] Document option -mtune as a no-op. This documents that option -mtune is accepted for compatibility with GCC, currently it has no effect, and thus does not currently perform any CPU type specific tuning. Corresponding discussion on the cfe dev list: http://lists.llvm.org/pipermail/cfe-dev/2020-April/065169.html Differential Revision: https://reviews.llvm.org/D78511 --- clang/docs/ClangCommandLineReference.rst | 2 ++ clang/include/clang/Driver/Options.td | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst index c7afcf7cf605..a10e747153e2 100644 --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -2735,6 +2735,8 @@ Specify bit size of immediate TLS offsets (AArch64 ELF only): 12 (for 4KB) \| 24 .. option:: -mtune= .. program:: clang +Accepted for compatibility with GCC. Currently has no effect. + .. option:: -mtvos-version-min=, -mappletvos-version-min= .. option:: -municode diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 2ec7269372b1..f9850c60f62d 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2721,7 +2721,8 @@ def muclibc : Flag<["-"], "muclibc">, Group, Flags<[HelpHidden]>; def module_file_info : Flag<["-"], "module-file-info">, Flags<[DriverOption,CC1Option]>, Group, HelpText<"Provide information about a particular module file">; def mthumb : Flag<["-"], "mthumb">, Group; -def mtune_EQ : Joined<["-"], "mtune=">, Group; +def mtune_EQ : Joined<["-"], "mtune=">, Group, + HelpText<"Accepted for compatibility with GCC. Currently has no effect.">; def multi__module : Flag<["-"], "multi_module">; def multiply__defined__unused : Separate<["-"], "multiply_defined_unused">; def multiply__defined : Separate<["-"], "multiply_defined">; -- GitLab From 161afc01064bd5bef42d1655f1b81b3030596527 Mon Sep 17 00:00:00 2001 From: Sam McCall Date: Wed, 22 Apr 2020 01:28:49 +0200 Subject: [PATCH 056/910] [clangd] Remove vscode plugin: now https://github.com/clangd/vscode-clangd Summary: Moving this out of the monorepo for consistency with other editor plugins. There's no version lock with clangd itself, and we never ran tests with lit. The first version from the new repo has been published. Reviewers: hokein Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D78598 --- .../clangd/clients/clangd-vscode/.gitignore | 3 - .../clients/clangd-vscode/.vscode/launch.json | 28 -- .../clangd-vscode/.vscode/settings.json | 9 - .../clients/clangd-vscode/.vscode/tasks.json | 32 -- .../clients/clangd-vscode/.vscodeignore | 9 - .../clients/clangd-vscode/DEVELOPING.md | 53 --- .../clangd/clients/clangd-vscode/LICENSE | 21 - .../clangd/clients/clangd-vscode/README.md | 103 ----- .../clangd-vscode/doc-assets/complete.png | Bin 45024 -> 0 bytes .../clangd-vscode/doc-assets/diagnostics.png | Bin 29566 -> 0 bytes .../clangd-vscode/doc-assets/extract.png | Bin 21101 -> 0 bytes .../clangd-vscode/doc-assets/format.png | Bin 23948 -> 0 bytes .../clangd-vscode/doc-assets/include.png | Bin 21077 -> 0 bytes .../clangd-vscode/doc-assets/symbolsearch.png | Bin 29427 -> 0 bytes .../clangd-vscode/doc-assets/xrefs.png | Bin 114451 -> 0 bytes .../clangd/clients/clangd-vscode/icon.png | Bin 20569 -> 0 bytes .../clients/clangd-vscode/package-lock.json | 419 ------------------ .../clangd/clients/clangd-vscode/package.json | 133 ------ .../clients/clangd-vscode/src/extension.ts | 190 -------- .../src/semantic-highlighting.ts | 399 ----------------- .../test/assets/includeTheme.jsonc | 28 -- .../test/assets/simpleTheme.jsonc | 17 - .../clangd-vscode/test/extension.test.ts | 14 - .../clients/clangd-vscode/test/index.ts | 35 -- .../clients/clangd-vscode/test/runTest.ts | 23 - .../test/semantic-highlighting.test.ts | 174 -------- .../clients/clangd-vscode/tsconfig.json | 29 -- 27 files changed, 1719 deletions(-) delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/.gitignore delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/.vscode/launch.json delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/.vscode/settings.json delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/.vscode/tasks.json delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/.vscodeignore delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/DEVELOPING.md delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/LICENSE delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/README.md delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/complete.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/diagnostics.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/extract.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/format.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/include.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/symbolsearch.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/xrefs.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/icon.png delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/package-lock.json delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/package.json delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/src/extension.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/src/semantic-highlighting.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/assets/includeTheme.jsonc delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/assets/simpleTheme.jsonc delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/extension.test.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/index.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/runTest.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/test/semantic-highlighting.test.ts delete mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/tsconfig.json diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/.gitignore b/clang-tools-extra/clangd/clients/clangd-vscode/.gitignore deleted file mode 100644 index a73617e32b4b..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -out -node_modules -.vscode-test diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/launch.json b/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/launch.json deleted file mode 100644 index 7d414bc00f32..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/launch.json +++ /dev/null @@ -1,28 +0,0 @@ -// A launch configuration that compiles extension and opens it inside a new window. -{ - "version": "0.1.0", - "configurations": [ - { - "name": "Launch Extension", - "type": "extensionHost", - "request": "launch", - "runtimeExecutable": "${execPath}", - "args": ["--extensionDevelopmentPath=${workspaceRoot}" ], - "stopOnEntry": false, - "sourceMaps": true, - "outFiles": [ "${workspaceRoot}/out/src/**/*.js" ], - "preLaunchTask": "npm" - }, - { - "name": "Launch Tests", - "type": "extensionHost", - "request": "launch", - "runtimeExecutable": "${execPath}", - "args": ["--extensionDevelopmentPath=${workspaceRoot}", "--extensionTestsPath=${workspaceRoot}/out/test" ], - "stopOnEntry": false, - "sourceMaps": true, - "outFiles": [ "${workspaceRoot}/out/test/**/*.js" ], - "preLaunchTask": "npm" - } - ] -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/settings.json b/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/settings.json deleted file mode 100644 index d13713339847..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/settings.json +++ /dev/null @@ -1,9 +0,0 @@ -// Place your settings in this file to overwrite default and user settings. -{ - "files.exclude": { - "out": false // set this to true to hide the "out" folder with the compiled JS files - }, - "search.exclude": { - "out": true // set this to false to include "out" folder in search results - } -} \ No newline at end of file diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/tasks.json b/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/tasks.json deleted file mode 100644 index 65b1c9598c0e..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/.vscode/tasks.json +++ /dev/null @@ -1,32 +0,0 @@ -// Available variables which can be used inside of strings. -// ${workspaceRoot}: the root folder of the team -// ${file}: the current opened file -// ${fileBasename}: the current opened file's basename -// ${fileDirname}: the current opened file's dirname -// ${fileExtname}: the current opened file's extension -// ${cwd}: the current working directory of the spawned process - -// Task runner calls custom npm script to compile the extension. -{ - "version": "2.0.0", - - // Run NPM. - "command": "npm", - - // This command is a shell script. - "type": "shell", - - // show the output window only if unrecognized errors occur. - "presentation": { - "reveal": "silent", - }, - - // Run custom "compile" script as defined in package.json - "args": ["run", "compile", "--loglevel", "silent"], - - // tsc compiler is kept alive and runs in the background. - "isBackground": true, - - // Find compilation problems in the output through tsc in watch mode. - "problemMatcher": "$tsc-watch" -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/.vscodeignore b/clang-tools-extra/clangd/clients/clangd-vscode/.vscodeignore deleted file mode 100644 index 5ff3c19320f6..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/.vscodeignore +++ /dev/null @@ -1,9 +0,0 @@ -.vscode/** -.vscode-test/** -out/test/** -test/** -src/** -**/*.map -.gitignore -tsconfig.json -vsc-extension-quickstart.md diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/DEVELOPING.md b/clang-tools-extra/clangd/clients/clangd-vscode/DEVELOPING.md deleted file mode 100644 index 15f2b930329e..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/DEVELOPING.md +++ /dev/null @@ -1,53 +0,0 @@ -# Development - -A guide of developing `vscode-clangd` extension. - -## Requirements - -* VS Code -* node.js and npm - -## Steps - -1. Make sure you disable the installed `vscode-clangd` extension in VS Code. -2. Make sure you have clangd in `/usr/bin/clangd` or edit `src/extension.ts` to -point to the binary. -3. To start a development instance of VS code extended with this, run: - -```bash - $ cd /path/to/clang-tools-extra/clangd/clients/clangd-vscode/ - $ npm install - $ code . - # When VSCode starts, press . -``` - -# Contributing - -Please follow the existing code style when contributing to the extension, we -recommend to run `npm run format` before sending a patch. - -# Publish to VS Code Marketplace - -New changes to `clangd-vscode` are not released until a new version is published -to the marketplace. - -## Requirements - -* Make sure install the `vsce` command (`npm install -g vsce`) -* `llvm-vs-code-extensions` account -* Bump the version in `package.json`, and commit the change to upstream - -The extension is published under `llvm-vs-code-extensions` account, which is -maintained by clangd developers. If you want to make a new release, please -contact clangd-dev@lists.llvm.org. - -## Steps - -```bash - $ cd /path/to/clang-tools-extra/clangd/clients/clangd-vscode/ - # For the first time, you need to login into the account. vsce will ask you - for the Personal Access Token and will remember it for future commands. - $ vsce login llvm-vs-code-extensions - # Publish the extension to the VSCode marketplace. - $ npm run publish -``` diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/LICENSE b/clang-tools-extra/clangd/clients/clangd-vscode/LICENSE deleted file mode 100644 index 6a18483d5b38..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/LICENSE +++ /dev/null @@ -1,21 +0,0 @@ -The MIT License (MIT) - -Copyright (c) 2019 The LLVM Developers - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/README.md b/clang-tools-extra/clangd/clients/clangd-vscode/README.md deleted file mode 100644 index 44b7f9697e78..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/README.md +++ /dev/null @@ -1,103 +0,0 @@ -# vscode-clangd - -Provides C/C++ language IDE features for VS Code using [clangd](https://clang.llvm.org/extra/clangd.html): - - - code completion - - compile errors and warnings - - go-to-definition and cross references - - include management - - code formatting - - simple refactorings - -## Setup - -### `clangd` server - -`clangd` is a language server that must be installed separately, see -[getting started](https://clang.llvm.org/extra/clangd/Installation.html#installing-clangd). -The vscode-clangd extension will look for `clangd` on your PATH (you can change -this in the settings). - -### Project setup - -clangd is based on the clang C++ compiler, and understands even complex C++ -code. However, you must tell clangd how your project is built (compile flags). -[A `compile_commands.json` file](http://clang.llvm.org/docs/JSONCompilationDatabase.html) -can usually be generated by your build system -(e.g. by setting `-DCMAKE_EXPORT_COMPILE_COMMANDS=1` when building with CMake, -or with -[many other tools](https://sarcasm.github.io/notes/dev/compilation-database.html)). - -It should live at the top of your source tree: symlink or copy it there. - -## Features - -### Code completion - -Suggestions will appear as you type names, or after `.` or `->`. -Because clangd uses a full C++ parser, code completion has access to precise -type information. - -![Code completion](doc-assets/complete.png) - -### Errors, warnings, and clang-tidy - -Code errors are shown as you type (both as red squiggle underlines, and in the -"Problems" panel). These are the same as produced by the clang compiler, and -suggested fixes can automatically be applied. - -![Error with fix](doc-assets/diagnostics.png) - -Most clang-tidy checks are supported (these can be enabled using a [.clang-tidy -file](https://clang.llvm.org/extra/clang-tidy/)). - -### Cross-references - -Go-to-definition and find-references work across your code, using a project-wide -index. - -![Cross-reference list](doc-assets/xrefs.png) - -Press `Ctrl-P #` to quickly navigate to a symbol by name. - -### Include management - -Code completion works across your codebase and adds `#include` directives where -needed. The `•` shows includes that will be inserted. - -clangd can also suggest inserting missing #includes, where they cause errors. - -![Fix inserts include](doc-assets/include.png) - -### Formatting - -clangd uses the `clang-format` engine. You can format a file or the selection. -When "Format on Type" is enabled in the settings, pressing enter will cause -clangd to format the old line and semantically reindent. - -![Format-on-type](doc-assets/format.png) - -The style used for formatting (and certain other operations) is controlled by -the .clang-format file is controlled by the project's -[.clang-format file](https://clang.llvm.org/docs/ClangFormatStyleOptions.html). - -### Refactoring - -clangd supports some local refactorings. When you select an expression or -declaration, the lightbulb menu appears and you can choose a code action. - -![Extract variable code action](doc-assets/extract.png) - -Current refactorings include: - - extract variable/function - - expand `auto` types and macros - - use raw strings - - rename (bound to ``, rather than a contextual code action) - -## Bugs/contributing - -clangd and vscode-clangd are part of the [LLVM project](https://llvm.org). - -If you'd like to help out, reach out to clangd-dev@lists.llvm.org. - -If you've found a bug, please file at https://github.com/clangd/clangd/issues. diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/complete.png b/clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/complete.png deleted file mode 100644 index 1ce9e82c64c36e2d782f9d636c4594566b3f9843..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 45024 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"vscode-clangd", - "description": "Clang Language Server", - "version": "0.0.22", - "publisher": "llvm-vs-code-extensions", - "homepage": "https://clangd.llvm.org/", - "icon": "icon.png", - "engines": { - "vscode": "^1.41.0" - }, - "categories": [ - "Programming Languages", - "Linters", - "Snippets" - ], - "keywords": [ - "C", - "C++", - "LSP", - "Clangd", - "LLVM" - ], - "activationEvents": [ - "onLanguage:c", - "onLanguage:cpp", - "onLanguage:cuda", - "onLanguage:objective-c", - "onLanguage:objective-cpp", - "onCommand:clangd-vscode.activate" - ], - "main": "./out/src/extension", - "scripts": { - "vscode:prepublish": "tsc -p ./", - "compile": "tsc -watch -p ./", - "format": "clang-format --style=LLVM -i --glob=\"{src,test}/*.ts\"", - "test": "tsc -p ./ && node ./out/test/runTest.js", - "package": "vsce package --baseImagesUrl https://raw.githubusercontent.com/llvm/llvm-project/master/clang-tools-extra/clangd/clients/clangd-vscode/", - "publish": "vsce publish --baseImagesUrl https://raw.githubusercontent.com/llvm/llvm-project/master/clang-tools-extra/clangd/clients/clangd-vscode/" - }, - "dependencies": { - "jsonc-parser": "^2.1.0", - "vscode-languageclient": "^6.1.0", - "vscode-languageserver": "^6.1.0", - "vscode-languageserver-types": "^3.15.1" - }, - "devDependencies": { - "@types/glob": "^7.1.1", - "@types/mocha": "^2.2.32", - "@types/node": "^6.0.40", - "@types/vscode": "^1.41.0", - "glob": "^7.1.4", - "clang-format": "1.2.4", - "mocha": "^5.2.0", - "typescript": "^3.5.1", - "vscode-test": "^1.3.0" - }, - "repository": { - "type": "git", - "url": "https://github.com/llvm/llvm-project.git", - "directory": "clang-tools/extra/clangd/clients/clangd-vscode" - }, - "contributes": { - "languages": [ - { - "id": "cpp", - "filenamePatterns": [ - "**/include/c++/**", - "**/MSVC/*/include/**" - ], - "firstLine": "^/[/*].*-\\*-\\s*C\\+\\+\\s*-\\*-.*" - }, - { - "id": "cuda", - "extensions": [ - ".cu", - ".cuh" - ] - } - ], - "configuration": { - "type": "object", - "title": "clangd configuration", - "properties": { - "clangd.path": { - "type": "string", - "default": "clangd", - "description": "The path to clangd executable, e.g.: /usr/bin/clangd" - }, - "clangd.arguments": { - "type": "array", - "default": [], - "items": { - "type": "string" - }, - "description": "Arguments for clangd server" - }, - "clangd.syncFileEvents": { - "type": "boolean", - "default": true, - "description": "Whether or not to send file events to clangd (File created, changed or deleted). This can be disabled for performance consideration." - }, - "clangd.trace": { - "type": "string", - "description": "Names a file that clangd should log a performance trace to, in chrome trace-viewer JSON format." - }, - "clangd.semanticHighlighting": { - "type": "boolean", - "default": "true", - "description": "Enable semantic highlighting in clangd" - } - } - }, - "commands": [ - { - "command": "clangd-vscode.switchheadersource", - "title": "Switch between Source/Header" - }, - { - "command": "clangd-vscode.activate", - "title": "Manually activate clangd extension" - } - ], - "keybindings": [ - { - "command": "clangd-vscode.switchheadersource", - "key": "Alt+o", - "mac": "Alt+cmd+o", - "when": "editorTextFocus" - } - ] - } -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/src/extension.ts b/clang-tools-extra/clangd/clients/clangd-vscode/src/extension.ts deleted file mode 100644 index a7570b63e552..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/src/extension.ts +++ /dev/null @@ -1,190 +0,0 @@ -import * as vscode from 'vscode'; -import * as vscodelc from 'vscode-languageclient'; -import * as semanticHighlighting from './semantic-highlighting'; - -/** - * Get an option from workspace configuration. - * @param option name of the option (e.g. for clangd.path should be path) - * @param defaultValue default value to return if option is not set - */ -function getConfig(option: string, defaultValue?: any): T { - const config = vscode.workspace.getConfiguration('clangd'); - return config.get(option, defaultValue); -} - -namespace SwitchSourceHeaderRequest { -export const type = - new vscodelc.RequestType('textDocument/switchSourceHeader'); -} - -class FileStatus { - private statuses = new Map(); - private readonly statusBarItem = - vscode.window.createStatusBarItem(vscode.StatusBarAlignment.Left, 10); - - onFileUpdated(fileStatus: any) { - const filePath = vscode.Uri.parse(fileStatus.uri); - this.statuses.set(filePath.fsPath, fileStatus); - this.updateStatus(); - } - - updateStatus() { - const path = vscode.window.activeTextEditor.document.fileName; - const status = this.statuses.get(path); - if (!status) { - this.statusBarItem.hide(); - return; - } - this.statusBarItem.text = `clangd: ` + status.state; - this.statusBarItem.show(); - } - - clear() { - this.statuses.clear(); - this.statusBarItem.hide(); - } - - dispose() { this.statusBarItem.dispose(); } -} - -class ClangdLanguageClient extends vscodelc.LanguageClient { - // Override the default implementation for failed requests. The default - // behavior is just to log failures in the output panel, however output panel - // is designed for extension debugging purpose, normal users will not open it, - // thus when the failure occurs, normal users doesn't know that. - // - // For user-interactive operations (e.g. applyFixIt, applyTweaks), we will - // prompt up the failure to users. - logFailedRequest(rpcReply: vscodelc.RPCMessageType, error: any) { - if (error instanceof vscodelc.ResponseError && - rpcReply.method === "workspace/executeCommand") - vscode.window.showErrorMessage(error.message); - // Call default implementation. - super.logFailedRequest(rpcReply, error); - } -} - -class EnableEditsNearCursorFeature implements vscodelc.StaticFeature { - initialize() {} - fillClientCapabilities(capabilities: vscodelc.ClientCapabilities): void { - const extendedCompletionCapabilities: any = - capabilities.textDocument.completion; - extendedCompletionCapabilities.editsNearCursor = true; - } -} - -/** - * This method is called when the extension is activated. The extension is - * activated the very first time a command is executed. - */ -export function activate(context: vscode.ExtensionContext) { - const syncFileEvents = getConfig('syncFileEvents', true); - - const clangd: vscodelc.Executable = { - command : getConfig('path'), - args : getConfig('arguments') - }; - const traceFile = getConfig('trace'); - if (!!traceFile) { - const trace = {CLANGD_TRACE : traceFile}; - clangd.options = {env : {...process.env, ...trace}}; - } - const serverOptions: vscodelc.ServerOptions = clangd; - - const clientOptions: vscodelc.LanguageClientOptions = { - // Register the server for c-family and cuda files. - documentSelector: [ - { scheme: 'file', language: 'c' }, - { scheme: 'file', language: 'cpp' }, - // CUDA is not supported by vscode, but our extension does supports it. - { scheme: 'file', language: 'cuda' }, - { scheme: 'file', language: 'objective-c'}, - { scheme: 'file', language: 'objective-cpp'} - ], - synchronize: !syncFileEvents ? undefined : { - // FIXME: send sync file events when clangd provides implementations. - }, - initializationOptions: { clangdFileStatus: true }, - // Do not switch to output window when clangd returns output. - revealOutputChannelOn: vscodelc.RevealOutputChannelOn.Never, - - // We hack up the completion items a bit to prevent VSCode from re-ranking them - // and throwing away all our delicious signals like type information. - // - // VSCode sorts by (fuzzymatch(prefix, item.filterText), item.sortText) - // By adding the prefix to the beginning of the filterText, we get a perfect - // fuzzymatch score for every item. - // The sortText (which reflects clangd ranking) breaks the tie. - // This also prevents VSCode from filtering out any results due to the - // differences in how fuzzy filtering is applies, e.g. enable dot-to-arrow - // fixes in completion. - // - // We also have to mark the list as incomplete to force retrieving new rankings. - // See https://github.com/microsoft/language-server-protocol/issues/898 - middleware: { - provideCompletionItem: async (document, position, context, token, next) => { - let list = await next(document, position, context, token); - let items = (Array.isArray(list) ? list : list.items).map(item => { - // Gets the prefix used by VSCode when doing fuzzymatch. - let prefix = document.getText(new vscode.Range(item.range.start, position)) - if (prefix) - item.filterText = prefix + "_" + item.filterText; - return item; - }) - return new vscode.CompletionList(items, /*isIncomplete=*/true); - } - }, - }; - - const clangdClient = new ClangdLanguageClient('Clang Language Server', - serverOptions, clientOptions); - if (getConfig('semanticHighlighting')) { - const semanticHighlightingFeature = - new semanticHighlighting.SemanticHighlightingFeature(clangdClient, - context); - context.subscriptions.push( - vscode.Disposable.from(semanticHighlightingFeature)); - clangdClient.registerFeature(semanticHighlightingFeature); - } - clangdClient.registerFeature(new EnableEditsNearCursorFeature); - console.log('Clang Language Server is now active!'); - context.subscriptions.push(clangdClient.start()); - context.subscriptions.push(vscode.commands.registerCommand( - 'clangd-vscode.switchheadersource', async () => { - const uri = - vscode.Uri.file(vscode.window.activeTextEditor.document.fileName); - if (!uri) { - return; - } - const docIdentifier = - vscodelc.TextDocumentIdentifier.create(uri.toString()); - const sourceUri = await clangdClient.sendRequest( - SwitchSourceHeaderRequest.type, docIdentifier); - if (!sourceUri) { - return; - } - const doc = await vscode.workspace.openTextDocument( - vscode.Uri.parse(sourceUri)); - vscode.window.showTextDocument(doc); - })); - const status = new FileStatus(); - context.subscriptions.push(vscode.Disposable.from(status)); - context.subscriptions.push(vscode.window.onDidChangeActiveTextEditor( - () => { status.updateStatus(); })); - context.subscriptions.push(clangdClient.onDidChangeState(({newState}) => { - if (newState == vscodelc.State.Running) { - // clangd starts or restarts after crash. - clangdClient.onNotification( - 'textDocument/clangd.fileStatus', - (fileStatus) => { status.onFileUpdated(fileStatus); }); - } else if (newState == vscodelc.State.Stopped) { - // Clear all cached statuses when clangd crashes. - status.clear(); - } - })); - // An empty place holder for the activate command, otherwise we'll get an - // "command is not registered" error. - context.subscriptions.push(vscode.commands.registerCommand( - 'clangd-vscode.activate', async () => {})); -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/src/semantic-highlighting.ts b/clang-tools-extra/clangd/clients/clangd-vscode/src/semantic-highlighting.ts deleted file mode 100644 index 17517441bab9..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/src/semantic-highlighting.ts +++ /dev/null @@ -1,399 +0,0 @@ -import * as fs from 'fs'; -import * as jsonc from "jsonc-parser"; -import * as path from 'path'; -import * as vscode from 'vscode'; -import * as vscodelc from 'vscode-languageclient'; -import * as vscodelct from 'vscode-languageserver-types'; - -// Parameters for the semantic highlighting (server-side) push notification. -// Mirrors the structure in the semantic highlighting proposal for LSP. -interface SemanticHighlightingParams { - // The text document that has to be decorated with the semantic highlighting - // information. - textDocument: vscodelct.VersionedTextDocumentIdentifier; - // An array of semantic highlighting information. - lines: SemanticHighlightingInformation[]; -} -// Contains the highlighting information for a specified line. Mirrors the -// structure in the semantic highlighting proposal for LSP. -interface SemanticHighlightingInformation { - // The zero-based line position in the text document. - line: number; - // A base64 encoded string representing every single highlighted characters - // with its start position, length and the "lookup table" index of of the - // semantic highlighting Text Mate scopes. - tokens?: string; -} - -// A SemanticHighlightingToken decoded from the base64 data sent by clangd. -interface SemanticHighlightingToken { - // Start column for this token. - character: number; - // Length of the token. - length: number; - // The TextMate scope index to the clangd scope lookup table. - scopeIndex: number; -} -// A line of decoded highlightings from the data clangd sent. -export interface SemanticHighlightingLine { - // The zero-based line position in the text document. - line: number; - // All SemanticHighlightingTokens on the line. - tokens: SemanticHighlightingToken[]; -} - -// Language server push notification providing the semantic highlighting -// information for a text document. -const NotificationType = - new vscodelc.NotificationType( - 'textDocument/semanticHighlighting'); - -// The feature that should be registered in the vscode lsp for enabling -// experimental semantic highlighting. -export class SemanticHighlightingFeature implements vscodelc.StaticFeature { - // The TextMate scope lookup table. A token with scope index i has the scopes - // on index i in the lookup table. - scopeLookupTable: string[][]; - // The object that applies the highlightings clangd sends. - highlighter: Highlighter; - // Any disposables that should be cleaned up when clangd crashes. - private subscriptions: vscode.Disposable[] = []; - constructor(client: vscodelc.BaseLanguageClient, - context: vscode.ExtensionContext) { - context.subscriptions.push(client.onDidChangeState(({newState}) => { - if (newState == vscodelc.State.Running) { - // Register handler for semantic highlighting notification. - client.onNotification(NotificationType, - this.handleNotification.bind(this)); - } else if (newState == vscodelc.State.Stopped) { - // Dispose resources when clangd crashes. - this.dispose(); - } - })); - } - fillClientCapabilities(capabilities: vscodelc.ClientCapabilities) { - // Extend the ClientCapabilities type and add semantic highlighting - // capability to the object. - const textDocumentCapabilities: vscodelc.TextDocumentClientCapabilities& - {semanticHighlightingCapabilities?: {semanticHighlighting : boolean}} = - capabilities.textDocument; - textDocumentCapabilities.semanticHighlightingCapabilities = { - semanticHighlighting : true, - }; - } - - async loadCurrentTheme() { - const themeRuleMatcher = new ThemeRuleMatcher( - await loadTheme(vscode.workspace.getConfiguration('workbench') - .get('colorTheme'))); - this.highlighter.initialize(themeRuleMatcher); - } - - initialize(capabilities: vscodelc.ServerCapabilities, - documentSelector: vscodelc.DocumentSelector|undefined) { - // The semantic highlighting capability information is in the capabilities - // object but to access the data we must first extend the ServerCapabilities - // type. - const serverCapabilities: vscodelc.ServerCapabilities& - {semanticHighlighting?: {scopes : string[][]}} = capabilities; - if (!serverCapabilities.semanticHighlighting) - return; - this.scopeLookupTable = serverCapabilities.semanticHighlighting.scopes; - // Important that highlighter is created before the theme is loading as - // otherwise it could try to update the themeRuleMatcher without the - // highlighter being created. - this.highlighter = new Highlighter(this.scopeLookupTable); - this.subscriptions.push(vscode.Disposable.from(this.highlighter)); - // Adds a listener to reload the theme when it changes. - this.subscriptions.push( - vscode.workspace.onDidChangeConfiguration((conf) => { - if (!conf.affectsConfiguration('workbench.colorTheme')) - return; - this.loadCurrentTheme(); - })); - this.loadCurrentTheme(); - // Event handling for handling with TextDocuments/Editors lifetimes. - this.subscriptions.push(vscode.window.onDidChangeVisibleTextEditors( - (editors: vscode.TextEditor[]) => editors.forEach( - (e) => this.highlighter.applyHighlights(e.document.uri)))); - this.subscriptions.push(vscode.workspace.onDidCloseTextDocument( - (doc) => this.highlighter.removeFileHighlightings(doc.uri))); - } - - handleNotification(params: SemanticHighlightingParams) { - const lines: SemanticHighlightingLine[] = params.lines.map( - (line) => ({line : line.line, tokens : decodeTokens(line.tokens)})); - this.highlighter.highlight(vscode.Uri.parse(params.textDocument.uri), - lines); - } - // Disposes of all disposable resources used by this object. - public dispose() { - this.subscriptions.forEach((d) => d.dispose()); - this.subscriptions = []; - } -} - -// Converts a string of base64 encoded tokens into the corresponding array of -// HighlightingTokens. -export function decodeTokens(tokens: string): SemanticHighlightingToken[] { - const scopeMask = 0xFFFF; - const lenShift = 0x10; - const uint32Size = 4; - const buf = Buffer.from(tokens, 'base64'); - const retTokens = []; - for (let i = 0, end = buf.length / uint32Size; i < end; i += 2) { - const start = buf.readUInt32BE(i * uint32Size); - const lenKind = buf.readUInt32BE((i + 1) * uint32Size); - const scopeIndex = lenKind & scopeMask; - const len = lenKind >>> lenShift; - retTokens.push({character : start, scopeIndex : scopeIndex, length : len}); - } - - return retTokens; -} - -// The main class responsible for processing of highlightings that clangd -// sends. -export class Highlighter { - // Maps uris with currently open TextDocuments to the current highlightings. - private files: Map> = new Map(); - // DecorationTypes for the current theme that are used when highlighting. A - // SemanticHighlightingToken with scopeIndex i should have the decoration at - // index i in this list. - private decorationTypes: vscode.TextEditorDecorationType[] = []; - // The clangd TextMate scope lookup table. - private scopeLookupTable: string[][]; - constructor(scopeLookupTable: string[][]) { - this.scopeLookupTable = scopeLookupTable; - } - public dispose() { - this.files.clear(); - this.decorationTypes.forEach((t) => t.dispose()); - // Dispose must not be not called multiple times if initialize is - // called again. - this.decorationTypes = []; - } - // This function must be called at least once or no highlightings will be - // done. Sets the theme that is used when highlighting. Also triggers a - // recolorization for all current highlighters. Should be called whenever the - // theme changes and has been loaded. Should also be called when the first - // theme is loaded. - public initialize(themeRuleMatcher: ThemeRuleMatcher) { - this.decorationTypes.forEach((t) => t.dispose()); - this.decorationTypes = this.scopeLookupTable.map((scopes) => { - const options: vscode.DecorationRenderOptions = { - // If there exists no rule for this scope the matcher returns an empty - // color. That's ok because vscode does not do anything when applying - // empty decorations. - color : themeRuleMatcher.getBestThemeRule(scopes[0]).foreground, - // If the rangeBehavior is set to Open in any direction the - // highlighting becomes weird in certain cases. - rangeBehavior : vscode.DecorationRangeBehavior.ClosedClosed, - }; - return vscode.window.createTextEditorDecorationType(options); - }); - this.getVisibleTextEditorUris().forEach((fileUri) => - this.applyHighlights(fileUri)); - } - - // Adds incremental highlightings to the current highlightings for the file - // with fileUri. Also applies the highlightings to any associated - // TextEditor(s). - public highlight(fileUri: vscode.Uri, - highlightingLines: SemanticHighlightingLine[]) { - const fileUriStr = fileUri.toString(); - if (!this.files.has(fileUriStr)) { - this.files.set(fileUriStr, new Map()); - } - const fileHighlightings = this.files.get(fileUriStr); - highlightingLines.forEach((line) => fileHighlightings.set(line.line, line)); - this.applyHighlights(fileUri); - } - - // Applies all the highlightings currently stored for a file with fileUri. - public applyHighlights(fileUri: vscode.Uri) { - const fileUriStr = fileUri.toString(); - if (!this.files.has(fileUriStr)) - // There are no highlightings for this file, must return early or will get - // out of bounds when applying the decorations below. - return; - if (!this.decorationTypes.length) - // Can't apply any decorations when there is no theme loaded. - return; - // This must always do a full re-highlighting due to the fact that - // TextEditorDecorationType are very expensive to create (which makes - // incremental updates infeasible). For this reason one - // TextEditorDecorationType is used per scope. - const ranges = this.getDecorationRanges(fileUri); - vscode.window.visibleTextEditors.forEach((e) => { - if (e.document.uri.toString() !== fileUriStr) - return; - this.decorationTypes.forEach((d, i) => e.setDecorations(d, ranges[i])); - }); - } - - // Called when a text document is closed. Removes any highlighting entries for - // the text document that was closed. - public removeFileHighlightings(fileUri: vscode.Uri) { - // If there exists no entry the call to delete just returns false. - this.files.delete(fileUri.toString()); - } - - // Gets the uris as strings for the currently visible text editors. - protected getVisibleTextEditorUris(): vscode.Uri[] { - return vscode.window.visibleTextEditors.map((e) => e.document.uri); - } - - // Returns the ranges that should be used when decorating. Index i in the - // range array has the decoration type at index i of this.decorationTypes. - protected getDecorationRanges(fileUri: vscode.Uri): vscode.Range[][] { - const fileUriStr = fileUri.toString(); - if (!this.files.has(fileUriStr)) - // this.files should always have an entry for fileUri if we are here. But - // if there isn't one we don't want to crash the extension. This is also - // useful for tests. - return []; - const lines: SemanticHighlightingLine[] = - Array.from(this.files.get(fileUriStr).values()); - const decorations: vscode.Range[][] = this.decorationTypes.map(() => []); - lines.forEach((line) => { - line.tokens.forEach((token) => { - decorations[token.scopeIndex].push(new vscode.Range( - new vscode.Position(line.line, token.character), - new vscode.Position(line.line, token.character + token.length))); - }); - }); - return decorations; - } -} - -// A rule for how to color TextMate scopes. -interface TokenColorRule { - // A TextMate scope that specifies the context of the token, e.g. - // "entity.name.function.cpp". - scope: string; - // foreground is the color tokens of this scope should have. - foreground: string; -} - -export class ThemeRuleMatcher { - // The rules for the theme. - private themeRules: TokenColorRule[]; - // A cache for the getBestThemeRule function. - private bestRuleCache: Map = new Map(); - constructor(rules: TokenColorRule[]) { this.themeRules = rules; } - // Returns the best rule for a scope. - getBestThemeRule(scope: string): TokenColorRule { - if (this.bestRuleCache.has(scope)) - return this.bestRuleCache.get(scope); - let bestRule: TokenColorRule = {scope : '', foreground : ''}; - this.themeRules.forEach((rule) => { - // The best rule for a scope is the rule that is the longest prefix of the - // scope (unless a perfect match exists in which case the perfect match is - // the best). If a rule is not a prefix and we tried to match with longest - // common prefix instead variables would be highlighted as `less` - // variables when using Light+ (as variable.other would be matched against - // variable.other.less in this case). Doing common prefix matching also - // means we could match variable.cpp to variable.css if variable.css - // occurs before variable in themeRules. - // FIXME: This is not defined in the TextMate standard (it is explicitly - // undefined, https://macromates.com/manual/en/scope_selectors). Might - // want to rank some other way. - if (scope.startsWith(rule.scope) && - rule.scope.length > bestRule.scope.length) - // This rule matches and is more specific than the old rule. - bestRule = rule; - }); - this.bestRuleCache.set(scope, bestRule); - return bestRule; - } -} - -// Get all token color rules provided by the theme. -function loadTheme(themeName: string): Promise { - const extension = - vscode.extensions.all.find((extension: vscode.Extension) => { - const contribs = extension.packageJSON.contributes; - if (!contribs || !contribs.themes) - return false; - return contribs.themes.some((theme: any) => theme.id === themeName || - theme.label === themeName); - }); - - if (!extension) { - return Promise.reject('Could not find a theme with name: ' + themeName); - } - - const themeInfo = extension.packageJSON.contributes.themes.find( - (theme: any) => theme.id === themeName || theme.label === themeName); - return parseThemeFile(path.join(extension.extensionPath, themeInfo.path)); -} - -/** - * Parse the TextMate theme at fullPath. If there are multiple TextMate scopes - * of the same name in the include chain only the earliest entry of the scope is - * saved. - * @param fullPath The absolute path to the theme. - * @param seenScopes A set containing the name of the scopes that have already - * been set. - */ -export async function parseThemeFile( - fullPath: string, seenScopes?: Set): Promise { - if (!seenScopes) - seenScopes = new Set(); - // FIXME: Add support for themes written as .tmTheme. - if (path.extname(fullPath) === '.tmTheme') - return []; - try { - const contents = await readFileText(fullPath); - const parsed = jsonc.parse(contents); - const rules: TokenColorRule[] = []; - // To make sure it does not crash if tokenColors is undefined. - if (!parsed.tokenColors) - parsed.tokenColors = []; - parsed.tokenColors.forEach((rule: any) => { - if (!rule.scope || !rule.settings || !rule.settings.foreground) - return; - const textColor = rule.settings.foreground; - // Scopes that were found further up the TextMate chain should not be - // overwritten. - const addColor = (scope: string) => { - if (seenScopes.has(scope)) - return; - rules.push({scope, foreground : textColor}); - seenScopes.add(scope); - }; - if (rule.scope instanceof Array) { - return rule.scope.forEach((s: string) => addColor(s)); - } - addColor(rule.scope); - }); - - if (parsed.include) - // Get all includes and merge into a flat list of parsed json. - return [ - ...(await parseThemeFile( - path.join(path.dirname(fullPath), parsed.include), seenScopes)), - ...rules - ]; - return rules; - } catch (err) { - // If there is an error opening a file, the TextMate files that were - // correctly found and parsed further up the chain should be returned. - // Otherwise there will be no highlightings at all. - console.warn('Could not open file: ' + fullPath + ', error: ', err); - } - - return []; -} - -function readFileText(path: string): Promise { - return new Promise((resolve, reject) => { - fs.readFile(path, 'utf8', (err, data) => { - if (err) { - return reject(err); - } - return resolve(data); - }); - }); -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/includeTheme.jsonc b/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/includeTheme.jsonc deleted file mode 100644 index 6f0032c64a76..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/includeTheme.jsonc +++ /dev/null @@ -1,28 +0,0 @@ -{ - // Some comment - "include": "simpleTheme.jsonc", - "name": "TestTheme", - "type": "dark", - "colors": { - "dropdown.background": "#fff" - }, - "tokenColors": [ - { - "settings": { - "foreground": "#fff" - } - }, - { - "scope": "a", - "settings": { - "foreground": "#fff" - } - }, - { - "scope": ["a", "b"], - "settings": { - "foreground": "#000" - } - } - ] -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/simpleTheme.jsonc b/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/simpleTheme.jsonc deleted file mode 100644 index 59a3ad61177b..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/assets/simpleTheme.jsonc +++ /dev/null @@ -1,17 +0,0 @@ -{ - // Some comment - "tokenColors": [ - { - "scope": "a", - "settings": { - "foreground": "#ff0000" - } - }, - { - "scope": "c", - "settings": { - "foreground": "#bcd" - } - } - ] -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/extension.test.ts b/clang-tools-extra/clangd/clients/clangd-vscode/test/extension.test.ts deleted file mode 100644 index 19691d69e49e..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/extension.test.ts +++ /dev/null @@ -1,14 +0,0 @@ -/** The module 'assert' provides assertion methods from node */ -import * as assert from 'assert'; - -import * as vscode from 'vscode'; -import * as myExtension from '../src/extension'; - -// TODO: add tests -suite("Extension Tests", () => { - // Defines a Mocha unit test - test("Something 1", () => { - assert.equal(-1, [ 1, 2, 3 ].indexOf(5)); - assert.equal(-1, [ 1, 2, 3 ].indexOf(0)); - }); -}); \ No newline at end of file diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/index.ts b/clang-tools-extra/clangd/clients/clangd-vscode/test/index.ts deleted file mode 100644 index 6e8047acbcec..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/index.ts +++ /dev/null @@ -1,35 +0,0 @@ -import * as glob from 'glob'; -import * as Mocha from 'mocha'; -import * as path from 'path'; - -export function run(): Promise { - // Create the mocha test - const mocha = new Mocha({ui : 'tdd'}); - mocha.useColors(true); - - const testsRoot = path.resolve(__dirname, '..'); - - return new Promise((c, e) => { - glob('**/**.test.js', {cwd : testsRoot}, (err, files) => { - if (err) { - return e(err); - } - - // Add files to the test suite - files.forEach(f => mocha.addFile(path.resolve(testsRoot, f))); - - try { - // Run the mocha test - mocha.run(failures => { - if (failures > 0) { - e(new Error(`${failures} tests failed.`)); - } else { - c(); - } - }); - } catch (err) { - e(err); - } - }); - }); -} diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/runTest.ts b/clang-tools-extra/clangd/clients/clangd-vscode/test/runTest.ts deleted file mode 100644 index 72ff0481a0c8..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/runTest.ts +++ /dev/null @@ -1,23 +0,0 @@ -import * as path from 'path'; - -import {runTests} from 'vscode-test'; - -async function main() { - try { - // The folder containing the Extension Manifest package.json - // Passed to `--extensionDevelopmentPath` - const extensionDevelopmentPath = path.resolve(__dirname, '../'); - - // The path to the extension test script - // Passed to --extensionTestsPath - const extensionTestsPath = path.resolve(__dirname, './index'); - - // Download VS Code, unzip it and run the integration test - await runTests({extensionDevelopmentPath, extensionTestsPath}); - } catch (err) { - console.error('Failed to run tests'); - process.exit(1); - } -} - -main(); diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/test/semantic-highlighting.test.ts b/clang-tools-extra/clangd/clients/clangd-vscode/test/semantic-highlighting.test.ts deleted file mode 100644 index 9f3e8bd9371f..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/test/semantic-highlighting.test.ts +++ /dev/null @@ -1,174 +0,0 @@ -import * as assert from 'assert'; -import * as path from 'path'; -import * as vscode from 'vscode'; - -import * as semanticHighlighting from '../src/semantic-highlighting'; - -suite('SemanticHighlighting Tests', () => { - test('Parses arrays of textmate themes.', async () => { - const themePath = - path.join(__dirname, '../../test/assets/includeTheme.jsonc'); - const scopeColorRules = - await semanticHighlighting.parseThemeFile(themePath); - const getScopeRule = (scope: string) => - scopeColorRules.find((v) => v.scope === scope); - assert.equal(scopeColorRules.length, 3); - assert.deepEqual(getScopeRule('a'), {scope : 'a', foreground : '#fff'}); - assert.deepEqual(getScopeRule('b'), {scope : 'b', foreground : '#000'}); - assert.deepEqual(getScopeRule('c'), {scope : 'c', foreground : '#bcd'}); - }); - test('Decodes tokens correctly', () => { - const testCases: string[] = [ - 'AAAAAAABAAA=', 'AAAAAAADAAkAAAAEAAEAAA==', - 'AAAAAAADAAkAAAAEAAEAAAAAAAoAAQAA' - ]; - const expected = [ - [ {character : 0, scopeIndex : 0, length : 1} ], - [ - {character : 0, scopeIndex : 9, length : 3}, - {character : 4, scopeIndex : 0, length : 1} - ], - [ - {character : 0, scopeIndex : 9, length : 3}, - {character : 4, scopeIndex : 0, length : 1}, - {character : 10, scopeIndex : 0, length : 1} - ] - ]; - testCases.forEach( - (testCase, i) => assert.deepEqual( - semanticHighlighting.decodeTokens(testCase), expected[i])); - }); - test('ScopeRules overrides for more specific themes', () => { - const rules = [ - {scope : 'variable.other.css', foreground : '1'}, - {scope : 'variable.other', foreground : '2'}, - {scope : 'storage', foreground : '3'}, - {scope : 'storage.static', foreground : '4'}, - {scope : 'storage', foreground : '5'}, - {scope : 'variable.other.parameter', foreground : '6'}, - ]; - const tm = new semanticHighlighting.ThemeRuleMatcher(rules); - assert.deepEqual(tm.getBestThemeRule('variable.other.cpp').scope, - 'variable.other'); - assert.deepEqual(tm.getBestThemeRule('storage.static').scope, - 'storage.static'); - assert.deepEqual( - tm.getBestThemeRule('storage'), - rules[2]); // Match the first element if there are duplicates. - assert.deepEqual(tm.getBestThemeRule('variable.other.parameter').scope, - 'variable.other.parameter'); - assert.deepEqual(tm.getBestThemeRule('variable.other.parameter.cpp').scope, - 'variable.other.parameter'); - }); - test('Colorizer groups decorations correctly', async () => { - const scopeTable = [ - [ 'variable' ], [ 'entity.type.function' ], - [ 'entity.type.function.method' ] - ]; - // Create the scope source ranges the highlightings should be highlighted - // at. Assumes the scopes used are the ones in the "scopeTable" variable. - const createHighlightingScopeRanges = - (highlightingLines: - semanticHighlighting.SemanticHighlightingLine[]) => { - // Initialize the scope ranges list to the correct size. Otherwise - // scopes that don't have any highlightings are missed. - let scopeRanges: vscode.Range[][] = scopeTable.map(() => []); - highlightingLines.forEach((line) => { - line.tokens.forEach((token) => { - scopeRanges[token.scopeIndex].push(new vscode.Range( - new vscode.Position(line.line, token.character), - new vscode.Position(line.line, - token.character + token.length))); - }); - }); - return scopeRanges; - }; - - const fileUri1 = vscode.Uri.parse('file:///file1'); - const fileUri2 = vscode.Uri.parse('file:///file2'); - const fileUri1Str = fileUri1.toString(); - const fileUri2Str = fileUri2.toString(); - - class MockHighlighter extends semanticHighlighting.Highlighter { - applicationUriHistory: string[] = []; - // Override to make the highlighting calls accessible to the test. Also - // makes the test not depend on visible text editors. - applyHighlights(fileUri: vscode.Uri) { - this.applicationUriHistory.push(fileUri.toString()); - } - // Override to make it accessible from the test. - getDecorationRanges(fileUri: vscode.Uri) { - return super.getDecorationRanges(fileUri); - } - // Override to make tests not depend on visible text editors. - getVisibleTextEditorUris() { return [ fileUri1, fileUri2 ]; } - } - const highlighter = new MockHighlighter(scopeTable); - const tm = new semanticHighlighting.ThemeRuleMatcher([ - {scope : 'variable', foreground : '1'}, - {scope : 'entity.type', foreground : '2'}, - ]); - // Recolorizes when initialized. - highlighter.highlight(fileUri1, []); - assert.deepEqual(highlighter.applicationUriHistory, [ fileUri1Str ]); - highlighter.initialize(tm); - assert.deepEqual(highlighter.applicationUriHistory, - [ fileUri1Str, fileUri1Str, fileUri2Str ]); - // Groups decorations into the scopes used. - let highlightingsInLine: semanticHighlighting.SemanticHighlightingLine[] = [ - { - line : 1, - tokens : [ - {character : 1, length : 2, scopeIndex : 1}, - {character : 10, length : 2, scopeIndex : 2}, - ] - }, - { - line : 2, - tokens : [ - {character : 3, length : 2, scopeIndex : 1}, - {character : 6, length : 2, scopeIndex : 1}, - {character : 8, length : 2, scopeIndex : 2}, - ] - }, - ]; - - highlighter.highlight(fileUri1, highlightingsInLine); - assert.deepEqual(highlighter.applicationUriHistory, - [ fileUri1Str, fileUri1Str, fileUri2Str, fileUri1Str ]); - assert.deepEqual(highlighter.getDecorationRanges(fileUri1), - createHighlightingScopeRanges(highlightingsInLine)); - // Keeps state separate between files. - const highlightingsInLine1: - semanticHighlighting.SemanticHighlightingLine = { - line : 1, - tokens : [ - {character : 2, length : 1, scopeIndex : 0}, - ] - }; - highlighter.highlight(fileUri2, [ highlightingsInLine1 ]); - assert.deepEqual( - highlighter.applicationUriHistory, - [ fileUri1Str, fileUri1Str, fileUri2Str, fileUri1Str, fileUri2Str ]); - assert.deepEqual(highlighter.getDecorationRanges(fileUri2), - createHighlightingScopeRanges([ highlightingsInLine1 ])); - // Does full colorizations. - highlighter.highlight(fileUri1, [ highlightingsInLine1 ]); - assert.deepEqual(highlighter.applicationUriHistory, [ - fileUri1Str, fileUri1Str, fileUri2Str, fileUri1Str, fileUri2Str, - fileUri1Str - ]); - // After the incremental update to line 1, the old highlightings at line 1 - // will no longer exist in the array. - assert.deepEqual( - highlighter.getDecorationRanges(fileUri1), - createHighlightingScopeRanges( - [ highlightingsInLine1, ...highlightingsInLine.slice(1) ])); - // Closing a text document removes all highlightings for the file and no - // other files. - highlighter.removeFileHighlightings(fileUri1); - assert.deepEqual(highlighter.getDecorationRanges(fileUri1), []); - assert.deepEqual(highlighter.getDecorationRanges(fileUri2), - createHighlightingScopeRanges([ highlightingsInLine1 ])); - }); -}); diff --git a/clang-tools-extra/clangd/clients/clangd-vscode/tsconfig.json b/clang-tools-extra/clangd/clients/clangd-vscode/tsconfig.json deleted file mode 100644 index 71a62c71da02..000000000000 --- a/clang-tools-extra/clangd/clients/clangd-vscode/tsconfig.json +++ /dev/null @@ -1,29 +0,0 @@ -{ - "compilerOptions": { - "module": "commonjs", - "target": "es6", - "outDir": "out", - "lib": [ - "es6", - "es2015.core", - "es2015.collection", - "es2015.generator", - "es2015.iterable", - "es2015.promise", - "es2015.symbol", - "es2016.array.include" - ], - "sourceMap": true, - "rootDir": ".", - "alwaysStrict": true, - "noEmitOnError": true, - "noFallthroughCasesInSwitch": true, - "noImplicitAny": true, - "noImplicitReturns": true, - "noImplicitThis": true - }, - "exclude": [ - "node_modules", - ".vscode-test" - ] -} -- GitLab From 0736d1ccf32ba4e6fe860942d8a6d05f964f058e Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Wed, 22 Apr 2020 10:17:28 +0100 Subject: [PATCH 057/910] [ARM][MVE] Tail-predication: some more comments and debug messages. NFC. Finding the loop tripcount is the first crucial step in preparing a loop for tail-predication, and this adds a debug message if a tripcount cannot be found. And while I was at it, I added some more comments here and there. Differential Revision: https://reviews.llvm.org/D78485 --- llvm/lib/Target/ARM/MVETailPredication.cpp | 69 ++++++++++++++++------ 1 file changed, 52 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp index 26b71ba5b600..9325dd26bba7 100644 --- a/llvm/lib/Target/ARM/MVETailPredication.cpp +++ b/llvm/lib/Target/ARM/MVETailPredication.cpp @@ -8,8 +8,17 @@ // /// \file /// Armv8.1m introduced MVE, M-Profile Vector Extension, and low-overhead -/// branches to help accelerate DSP applications. These two extensions can be -/// combined to provide implicit vector predication within a low-overhead loop. +/// branches to help accelerate DSP applications. These two extensions, +/// combined with a new form of predication called tail-predication, can be used +/// to provide implicit vector predication within a low-overhead loop. +/// This is implicit because the predicate of active/inactive lanes is +/// calculated by hardware, and thus does not need to be explicitly passed +/// to vector instructions. The instructions responsible for this are the +/// DLSTP and WLSTP instructions, which setup a tail-predicated loop and the +/// the total number of data elements processed by the loop. The loop-end +/// LETP instruction is responsible for decrementing and setting the remaining +/// elements to be processed and generating the mask of active lanes. +/// /// The HardwareLoops pass inserts intrinsics identifying loops that the /// backend will attempt to convert into a low-overhead loop. The vectorizer is /// responsible for generating a vectorized loop in which the lanes are @@ -21,10 +30,16 @@ /// - A loop containing multiple VCPT instructions, predicating multiple VPT /// blocks of instructions operating on different vector types. /// -/// This pass inserts the inserts the VCTP intrinsic to represent the effect of -/// tail predication. This will be picked up by the ARM Low-overhead loop pass, -/// which performs the final transformation to a DLSTP or WLSTP tail-predicated -/// loop. +/// This pass: +/// 1) Pattern matches the scalar iteration count produced by the vectoriser. +/// The scalar loop iteration count represents the number of elements to be +/// processed. +/// TODO: this could be emitted using an intrinsic, similar to the hardware +/// loop intrinsics, so that we don't need to pattern match this here. +/// 2) Inserts the VCTP intrinsic to represent the effect of +/// tail predication. This will be picked up by the ARM Low-overhead loop +/// pass, which performs the final transformation to a DLSTP or WLSTP +/// tail-predicated loop. #include "ARM.h" #include "ARMSubtarget.h" @@ -58,16 +73,17 @@ namespace { // Bookkeeping for pattern matching the loop trip count and the number of // elements processed by the loop. struct TripCountPattern { - // The Predicate used by the masked loads/stores, i.e. an icmp instruction - // which calculates active/inactive lanes + // An icmp instruction that calculates a predicate of active/inactive lanes + // used by the masked loads/stores. Instruction *Predicate = nullptr; - // The add instruction that increments the IV + // The add instruction that increments the IV. Value *TripCount = nullptr; // The number of elements processed by the vector loop. Value *NumElements = nullptr; + // Other instructions in the icmp chain that calculate the predicate. VectorType *VecTy = nullptr; Instruction *Shuffle = nullptr; Instruction *Induction = nullptr; @@ -117,8 +133,9 @@ private: /// loop will process if it is a runtime value. bool ComputeRuntimeElements(TripCountPattern &TCP); - /// Is the icmp that generates an i1 vector, based upon a loop counter - /// and a limit that is defined outside the loop. + /// Return whether this is the icmp that generates an i1 vector, based + /// upon a loop counter and a limit that is defined outside the loop, + /// that generates the active/inactive lanes required for tail-predication. bool isTailPredicate(TripCountPattern &TCP); /// Insert the intrinsic to represent the effect of tail predication. @@ -241,6 +258,7 @@ bool MVETailPredication::runOnLoop(Loop *L, LPPassManager&) { return true; } + LLVM_DEBUG(dbgs() << "ARM TP: Can't tail-predicate this loop.\n"); return false; } @@ -563,10 +581,10 @@ static bool Cleanup(DenseMap &NewPredicates, if (I->hasNUsesOrMore(1)) continue; - for (auto &U : I->operands()) { + for (auto &U : I->operands()) if (auto *OpI = dyn_cast(U)) MaybeDead.insert(OpI); - } + I->dropAllReferences(); Dead.insert(I); } @@ -638,30 +656,47 @@ bool MVETailPredication::TryConvert(Value *TripCount) { SetVector Predicates; DenseMap NewPredicates; +#ifndef NDEBUG + // For debugging purposes, use this to indicate we have been able to + // pattern match the scalar loop trip count. + bool FoundScalarTC = false; +#endif + for (auto *I : MaskedInsts) { Intrinsic::ID ID = I->getIntrinsicID(); + // First, find the icmp used by this masked load/store. unsigned PredOp = ID == Intrinsic::masked_load ? 2 : 3; auto *Predicate = dyn_cast(I->getArgOperand(PredOp)); if (!Predicate || Predicates.count(Predicate)) continue; + // Step 1: using this icmp, now calculate the number of elements + // processed by this loop. TripCountPattern TCP(Predicate, TripCount, getVectorType(I)); - if (!(ComputeConstElements(TCP) || ComputeRuntimeElements(TCP))) continue; + LLVM_DEBUG(FoundScalarTC = true); + if (!isTailPredicate(TCP)) { - LLVM_DEBUG(dbgs() << "ARM TP: Not tail predicate: " << *Predicate << "\n"); + LLVM_DEBUG(dbgs() << "ARM TP: Not an icmp that generates tail predicate: " + << *Predicate << "\n"); continue; } - LLVM_DEBUG(dbgs() << "ARM TP: Found tail predicate: " << *Predicate << "\n"); + LLVM_DEBUG(dbgs() << "ARM TP: Found icmp generating tail predicate: " + << *Predicate << "\n"); Predicates.insert(Predicate); + + // Step 2: emit the VCTP intrinsic representing the effect of TP. InsertVCTPIntrinsic(TCP, NewPredicates); } - if (!NewPredicates.size()) + if (!NewPredicates.size()) { + LLVM_DEBUG(if (!FoundScalarTC) + dbgs() << "ARM TP: Can't determine loop itertion count\n"); return false; + } // Now clean up. ClonedVCTPInExitBlock = Cleanup(NewPredicates, Predicates, L); -- GitLab From 317c4913c642f8f7fa0fb150fd5e656b59f20a4a Mon Sep 17 00:00:00 2001 From: Georgii Rymar Date: Tue, 7 Apr 2020 18:20:51 +0300 Subject: [PATCH 058/910] [obj2yaml] - Fix the issue with dumping empty sections when dumping program headers. Imagine we have: ``` ProgramHeaders: - Type: PT_LOAD Flags: [ PF_W, PF_R ] Sections: - Section: .bar VAddr: 0x2000 Sections: - Name: .foo Type: SHT_PROGBITS Flags: [ SHF_ALLOC, SHF_EXECINSTR ] Address: 0x1000 - Name: .bar Type: SHT_PROGBITS Flags: [ SHF_ALLOC, SHF_EXECINSTR ] Address: 0x2000 ``` Both `.foo` and `.bar` share the same starting file offset, but `VA(.foo)` < `VA(PT_LOAD)`, we should not include it into segment. This patch fixes the issue. Differential revision: https://reviews.llvm.org/D77652 --- llvm/test/Object/obj2yaml.test | 1 - llvm/test/tools/obj2yaml/program-headers.yaml | 115 ++++++++++++++++++ llvm/tools/obj2yaml/elf2yaml.cpp | 16 ++- 3 files changed, 127 insertions(+), 5 deletions(-) diff --git a/llvm/test/Object/obj2yaml.test b/llvm/test/Object/obj2yaml.test index a4398fb1e313..a1b0d1eff561 100644 --- a/llvm/test/Object/obj2yaml.test +++ b/llvm/test/Object/obj2yaml.test @@ -664,7 +664,6 @@ Symbols: # ELF-AVR-NEXT: Flags: [ PF_X, PF_R ] # ELF-AVR-NEXT: Sections: # ELF-AVR-NEXT: - Section: .text -# ELF-AVR-NEXT: - Section: .data # ELF-AVR-NEXT: Align: 0x0000000000000002 # ELF-AVR-NEXT: - Type: PT_LOAD # ELF-AVR-NEXT: Flags: [ PF_W, PF_R ] diff --git a/llvm/test/tools/obj2yaml/program-headers.yaml b/llvm/test/tools/obj2yaml/program-headers.yaml index 5d56487f8c0c..740d34971c9d 100644 --- a/llvm/test/tools/obj2yaml/program-headers.yaml +++ b/llvm/test/tools/obj2yaml/program-headers.yaml @@ -574,3 +574,118 @@ Sections: Flags: [ SHF_ALLOC ] Size: 0x1 ShOffset: 0x0 + +## Check how we dump segments which contain empty sections. +# RUN: yaml2obj --docnum=7 %s -o %t7 + +## Show the layout of the object before we dump it using obj2yaml. +## Notes: 1) '.empty.foo', '.empty.bar1' and '.bar' have the same file offset, but '.empty.foo' +## has a VA that is outside of the segment, hence we should not include it in it. +## 2) '.bar1' ends at 0x79, which is the starting file offset of both '.empty.bar2' +## and '.empty.zed'. We should only include '.empty.bar2', because the VA of the +## '.empty.zed' section is outside the segment's virtual space. +# RUN: llvm-readelf -sections %t7 | FileCheck %s --check-prefix=ZERO-SIZE-MAPPING + +# ZERO-SIZE-MAPPING: Section Headers: +# ZERO-SIZE-MAPPING-NEXT: [Nr] Name Type Address Off Size +# ZERO-SIZE-MAPPING: [ 1] .empty.foo PROGBITS 0000000000001000 000078 000000 +# ZERO-SIZE-MAPPING-NEXT: [ 2] .empty.bar1 PROGBITS 0000000000002000 000078 000000 +# ZERO-SIZE-MAPPING-NEXT: [ 3] .bar PROGBITS 0000000000002000 000078 000001 +# ZERO-SIZE-MAPPING-NEXT: [ 4] .empty.bar2 PROGBITS 0000000000002001 000079 000000 +# ZERO-SIZE-MAPPING-NEXT: [ 5] .empty.zed PROGBITS 0000000000003000 000079 000000 + +# RUN: obj2yaml %t7 | FileCheck %s --check-prefix=ZERO-SIZE + +# ZERO-SIZE: ProgramHeaders: +# ZERO-SIZE-NEXT: - Type: PT_LOAD +# ZERO-SIZE-NEXT: Flags: [ PF_W, PF_R ] +# ZERO-SIZE-NEXT: Sections: +# ZERO-SIZE-NEXT: - Section: .empty.bar1 +# ZERO-SIZE-NEXT: - Section: .bar +# ZERO-SIZE-NEXT: - Section: .empty.bar2 +# ZERO-SIZE-NEXT: VAddr: 0x0000000000002000 +# ZERO-SIZE-NEXT: Sections: + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +ProgramHeaders: + - Type: PT_LOAD + Flags: [ PF_W, PF_R ] + Sections: + - Section: .bar + VAddr: 0x2000 +Sections: + - Name: .empty.foo + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0x1000 + - Name: .empty.bar1 + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0x2000 + - Name: .bar + Type: SHT_PROGBITS + Flags: [ SHF_WRITE, SHF_ALLOC ] + Address: 0x2000 + Size: 0x1 + - Name: .empty.bar2 + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0x2001 + - Name: .empty.zed + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0x3000 + +## Check how we dump a segment when we have sections that are outside of the virtual +## address space of a segment, but inside its file space. We do not include such sections +## in a segment when they are at the edges of a segment, because this is a normal case and +## it may mean they belong to a different segment. +# RUN: yaml2obj --docnum=8 %s -o %t8 +# RUN: obj2yaml %t8 | FileCheck %s --check-prefix=BROKEN-VA + +# BROKEN-VA: ProgramHeaders: +# BROKEN-VA-NEXT: - Type: PT_LOAD +# BROKEN-VA-NEXT: Flags: [ PF_W, PF_R ] +# BROKEN-VA-NEXT: Sections: +# BROKEN-VA-NEXT: - Section: .empty_middle +# BROKEN-VA-NEXT: VAddr: 0x0000000000001000 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +ProgramHeaders: + - Type: PT_LOAD + Flags: [ PF_W, PF_R ] + VAddr: 0x1000 + Sections: + - Section: .empty_begin + - Section: .empty_middle + - Section: .empty_end +Sections: + - Name: .empty_begin + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0xFEFEFEFE + - Type: Fill + Pattern: "00" + Size: 1 + Name: begin + - Name: .empty_middle + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0xFEFEFEFE + - Type: Fill + Pattern: "00" + Size: 1 + - Name: .empty_end + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Address: 0xFEFEFEFE diff --git a/llvm/tools/obj2yaml/elf2yaml.cpp b/llvm/tools/obj2yaml/elf2yaml.cpp index c145142f65bc..fe3f36f4e6da 100644 --- a/llvm/tools/obj2yaml/elf2yaml.cpp +++ b/llvm/tools/obj2yaml/elf2yaml.cpp @@ -305,17 +305,25 @@ static bool isInSegment(const ELFYAML::Section &Sec, SHdr.sh_offset >= Phdr.p_offset && (SHdr.sh_offset + SHdr.sh_size <= Phdr.p_offset + Phdr.p_filesz); - if (FileOffsetsMatch) + bool VirtualAddressesMatch = SHdr.sh_addr >= Phdr.p_vaddr && + SHdr.sh_addr <= Phdr.p_vaddr + Phdr.p_memsz; + + if (FileOffsetsMatch) { + // An empty section on the edges of a program header can be outside of the + // virtual address space of the segment. This means it is not included in + // the segment and we should ignore it. + if (SHdr.sh_size == 0 && (SHdr.sh_offset == Phdr.p_offset || + SHdr.sh_offset == Phdr.p_offset + Phdr.p_filesz)) + return VirtualAddressesMatch; return true; + } // SHT_NOBITS sections usually occupy no physical space in a file. Such // sections belong to a segment when they reside in the segment's virtual // address space. if (Sec.Type != ELF::SHT_NOBITS) return false; - - return SHdr.sh_addr >= Phdr.p_vaddr && - SHdr.sh_addr <= Phdr.p_vaddr + Phdr.p_memsz; + return VirtualAddressesMatch; } template -- GitLab From 87d33d9e09c6b727e108c6cd86b36743740e08cc Mon Sep 17 00:00:00 2001 From: Georgii Rymar Date: Fri, 17 Apr 2020 15:06:04 +0300 Subject: [PATCH 059/910] [yaml2obj] - Change how p_offset is calculated when creating segments. NFCI. This depends on D78361 and simplifies the computation of the `p_offset`. Differential revision: https://reviews.llvm.org/D78363 --- llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp index 3a673cf67e87..450856daa874 100644 --- a/llvm/lib/ObjectYAML/ELFEmitter.cpp +++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp @@ -759,18 +759,12 @@ void ELFState::setProgramHeaderLayout(std::vector &PHeaders, reportError("sections in the program header with index " + Twine(PhdrIdx) + " are not sorted by their file offset"); - if (YamlPhdr.Offset) { + if (YamlPhdr.Offset) PHeader.p_offset = *YamlPhdr.Offset; - } else { - if (YamlPhdr.Sections.size()) - PHeader.p_offset = UINT32_MAX; - else - PHeader.p_offset = 0; - - // Find the minimum offset for the program header. - for (const Fragment &F : Fragments) - PHeader.p_offset = std::min((uint64_t)PHeader.p_offset, F.Offset); - } + else if (!Fragments.empty()) + PHeader.p_offset = Fragments.front().Offset; + else + PHeader.p_offset = 0; // Find the maximum offset of the end of a section in order to set p_filesz // and p_memsz. When setting p_filesz, trailing SHT_NOBITS sections are not -- GitLab From 2bf56743172c536b201a6f68b497694253236bd4 Mon Sep 17 00:00:00 2001 From: Georgii Rymar Date: Thu, 16 Apr 2020 16:41:28 +0300 Subject: [PATCH 060/910] [yaml2obj] - Program headers: add an additional check for `Offset` The `Offset` field is used to set the file offset of a program header. In a normal object it should not be greater than the minimal offset of sections included into segment. This patch adds a check for that and adds tests. Differential revision: https://reviews.llvm.org/D78304 --- llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 ++- llvm/test/Object/invalid.test | 8 -- .../ELF/invalid-p_filesz-p_offset.test | 12 +- .../tools/llvm-readobj/ELF/gnu-notes.test | 8 +- .../ELF/program-header-size-offset.yaml | 120 +++++++++++++++++- 5 files changed, 128 insertions(+), 36 deletions(-) diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp index 450856daa874..c32c42b795e7 100644 --- a/llvm/lib/ObjectYAML/ELFEmitter.cpp +++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp @@ -759,12 +759,16 @@ void ELFState::setProgramHeaderLayout(std::vector &PHeaders, reportError("sections in the program header with index " + Twine(PhdrIdx) + " are not sorted by their file offset"); - if (YamlPhdr.Offset) - PHeader.p_offset = *YamlPhdr.Offset; - else if (!Fragments.empty()) - PHeader.p_offset = Fragments.front().Offset; - else - PHeader.p_offset = 0; + uint64_t PhdrFileOffset = Fragments.empty() ? 0 : Fragments.front().Offset; + if (YamlPhdr.Offset) { + if (!Fragments.empty() && *YamlPhdr.Offset > PhdrFileOffset) + reportError("'Offset' for segment with index " + Twine(PhdrIdx) + + " must be less than or equal to the minimum file offset of " + "all included sections (0x" + + Twine::utohexstr(PhdrFileOffset) + ")"); + PhdrFileOffset = *YamlPhdr.Offset; + } + PHeader.p_offset = PhdrFileOffset; // Find the maximum offset of the end of a section in order to set p_filesz // and p_memsz. When setting p_filesz, trailing SHT_NOBITS sections are not diff --git a/llvm/test/Object/invalid.test b/llvm/test/Object/invalid.test index 3a1ef2b3318c..a7363abcace0 100644 --- a/llvm/test/Object/invalid.test +++ b/llvm/test/Object/invalid.test @@ -485,17 +485,9 @@ FileHeader: Data: ELFDATA2LSB Type: ET_EXEC Machine: EM_X86_64 -Sections: - - Name: .dynamic - Type: SHT_DYNAMIC - Entries: - - Tag: DT_NULL - Value: 0 ProgramHeaders: - Type: PT_DYNAMIC Offset: 0xffff0000 - Sections: - - Section: .dynamic ## PT_DYNAMIC's p_filesz field is so large that p_offset + p_filesz is larger ## than the object size. Check llvm-readobj reports it. diff --git a/llvm/test/tools/llvm-objcopy/ELF/invalid-p_filesz-p_offset.test b/llvm/test/tools/llvm-objcopy/ELF/invalid-p_filesz-p_offset.test index b2f746e04200..db6b59189fb0 100644 --- a/llvm/test/tools/llvm-objcopy/ELF/invalid-p_filesz-p_offset.test +++ b/llvm/test/tools/llvm-objcopy/ELF/invalid-p_filesz-p_offset.test @@ -33,13 +33,7 @@ FileHeader: Data: ELFDATA2LSB Type: ET_EXEC Machine: EM_X86_64 -Sections: - - Name: .foo - Type: SHT_PROGBITS - Size: 1 ProgramHeaders: - - Type: PT_LOAD - Offset: 0x100000 - FileSize: 1 - Sections: - - Section: .foo + - Type: PT_LOAD + Offset: 0x100000 + FileSize: 1 diff --git a/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test b/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test index cb4ea1da48f7..366d435e8e48 100644 --- a/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test +++ b/llvm/test/tools/llvm-readobj/ELF/gnu-notes.test @@ -165,15 +165,9 @@ FileHeader: Data: ELFDATA2LSB Type: ET_CORE Machine: EM_X86_64 -Sections: - - Name: .note - Type: SHT_NOTE - Notes: [] ProgramHeaders: - - Type: PT_NOTE + - Type: PT_NOTE Offset: 0xffff0000 - Sections: - - Section: .note ## Test tools report an error if a note program header has an invalid size that ## goes past the end of file. diff --git a/llvm/test/tools/yaml2obj/ELF/program-header-size-offset.yaml b/llvm/test/tools/yaml2obj/ELF/program-header-size-offset.yaml index a2f727dab5fd..9b16b32e50a5 100644 --- a/llvm/test/tools/yaml2obj/ELF/program-header-size-offset.yaml +++ b/llvm/test/tools/yaml2obj/ELF/program-header-size-offset.yaml @@ -1,8 +1,8 @@ ## Show that yaml2obj properly emits program headers with explicit file size, ## memory size and offset parameters. -# RUN: yaml2obj %s -o %t -# RUN: llvm-readobj %t --program-headers | FileCheck %s +# RUN: yaml2obj --docnum=1 %s -o %t1 +# RUN: llvm-readobj %t1 --program-headers | FileCheck %s # CHECK: ProgramHeaders [ # CHECK: Offset: 0x1234 @@ -34,7 +34,7 @@ # CHECK: MemSize: 6 # CHECK: ] -!ELF +--- !ELF FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB @@ -92,13 +92,11 @@ ProgramHeaders: MemSize: 9 Sections: - Section: .text - # Program header with sections, invalid properties. + # Program header with invalid properties. - Type: 0x6abcdef0 Offset: 0x3000 FileSize: 3 MemSize: 2 - Sections: - - Section: .data # Program header with 2 SHT_NOBITS sections. - Type: 0x6abcdef0 Offset: 0x2004 @@ -106,3 +104,113 @@ ProgramHeaders: - Section: .data - Section: .nobits1 - Section: .nobits2 + +## Test the "Offset" property. + +## Check that by default the p_offset field of a segment is set to the +## offset of the section with the minimum offset. +# RUN: yaml2obj --docnum=2 %s -o %t2 +# RUN: llvm-readelf %t2 --sections --program-headers | \ +# RUN: FileCheck %s --check-prefixes=DEFAULT-OFFSET + +# DEFAULT-OFFSET: [Nr] Name Type Address Off +# DEFAULT-OFFSET: [ 1] .foo PROGBITS 0000000000001000 0000b0 +# DEFAULT-OFFSET-NEXT: [ 2] .bar PROGBITS 0000000000001001 0000b1 + +# DEFAULT-OFFSET: Type Offset +# DEFAULT-OFFSET-NEXT: LOAD 0x0000b0 +# DEFAULT-OFFSET-NEXT: LOAD 0x0000b1 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .foo + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x1 + Address: 0x1000 + - Name: .bar + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x1 +ProgramHeaders: + - Type: PT_LOAD + Sections: + - Section: .foo + - Section: .bar + - Type: PT_LOAD + Sections: + - Section: .bar + +## Check we can set the "Offset" value explicitly to be less than or equal to +## the offset of a section in the segment. +# RUN: yaml2obj --docnum=3 -DOFFSET=0x77 %s -o %t3 +# RUN: llvm-readelf %t3 --sections --program-headers | \ +# RUN: FileCheck %s --check-prefixes=VALID-OFFSET,VALID-OFFSET-LESS +# RUN: yaml2obj --docnum=3 -DOFFSET=0x78 %s -o %t4 +# RUN: llvm-readelf %t4 --sections --program-headers | \ +# RUN: FileCheck %s --check-prefixes=VALID-OFFSET,VALID-OFFSET-EQ + +# VALID-OFFSET: [Nr] Name Type Address Off +# VALID-OFFSET: [ 1] .foo PROGBITS 0000000000000000 000078 + +# VALID-OFFSET: Type Offset +# VALID-OFFSET-EQ: LOAD 0x000078 +# VALID-OFFSET-LESS: LOAD 0x000077 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .foo + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x1 +ProgramHeaders: + - Type: PT_LOAD + Offset: [[OFFSET]] + Sections: + - Section: .foo + +## Check we report an error when the "Offset" value is larger than the offset of a section in the segment. +# RUN: not yaml2obj --docnum=3 -DOFFSET=0x79 %s -o /dev/null 2>&1 | \ +# RUN: FileCheck %s --check-prefix=INVALID-OFFSET + +# INVALID-OFFSET: yaml2obj: error: 'Offset' for segment with index 1 must be less than or equal to the minimum file offset of all included sections (0x78) + +## Document that the "Offset" value is checked after the section offset is overriden using "ShOffset". +# RUN: yaml2obj --docnum=4 %s -o %t5 +# RUN: llvm-readelf %t5 --sections --program-headers | FileCheck %s --check-prefix=SHOFFSET + +# SHOFFSET: [Nr] Name Type Address Off +# SHOFFSET: [ 1] .foo PROGBITS 0000000000000000 ffffffff + +# SHOFFSET: Type Offset +# SHOFFSET-NEXT: LOAD 0xffffff00 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .foo + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Size: 0x1 +## Note: the real .foo offset is much less than 0xFFFFFFFF or +## 0xFFFFFF00, but no error is reported. + ShOffset: 0xFFFFFFFF +ProgramHeaders: + - Type: PT_LOAD + Offset: 0xFFFFFF00 + Sections: + - Section: .foo -- GitLab From b198f1f86ce09b86825dd6d80de2c72a617e27f7 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 22 Apr 2020 12:09:37 +0200 Subject: [PATCH 061/910] Make some static class members constexpr This allows them to be ODR used in C++17 mode. NFC. --- llvm/include/llvm/ADT/APFloat.h | 2 +- llvm/include/llvm/ADT/APInt.h | 2 +- llvm/include/llvm/ADT/Hashing.h | 8 ++++---- llvm/include/llvm/ADT/SparseMultiSet.h | 2 +- llvm/include/llvm/ADT/StringRef.h | 2 +- llvm/include/llvm/Support/BranchProbability.h | 4 ++-- llvm/include/llvm/Support/Error.h | 2 +- llvm/include/llvm/Support/ErrorOr.h | 2 +- llvm/include/llvm/Support/ScaledNumber.h | 4 ++-- .../llvm/Support/circular_raw_ostream.h | 4 ++-- llvm/include/llvm/Support/raw_ostream.h | 20 +++++++++---------- llvm/lib/Support/BranchProbability.cpp | 2 +- llvm/lib/Support/StringRef.cpp | 2 +- llvm/lib/Support/raw_ostream.cpp | 20 +++++++++---------- 14 files changed, 38 insertions(+), 38 deletions(-) diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h index 37aa6dce7f11..1c17f10691e7 100644 --- a/llvm/include/llvm/ADT/APFloat.h +++ b/llvm/include/llvm/ADT/APFloat.h @@ -142,7 +142,7 @@ enum lostFraction { // Example of truncated bits: // members. struct APFloatBase { typedef APInt::WordType integerPart; - static const unsigned integerPartWidth = APInt::APINT_BITS_PER_WORD; + static constexpr unsigned integerPartWidth = APInt::APINT_BITS_PER_WORD; /// A signed type to represent a floating point numbers unbiased exponent. typedef int32_t ExponentType; diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h index 0791a6d686a3..9f0fb04794ea 100644 --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -84,7 +84,7 @@ public: UP, }; - static const WordType WORDTYPE_MAX = ~WordType(0); + static constexpr WordType WORDTYPE_MAX = ~WordType(0); private: /// This union is used to store the integer value. When the diff --git a/llvm/include/llvm/ADT/Hashing.h b/llvm/include/llvm/ADT/Hashing.h index dac0e0556ff3..9ee310c879fd 100644 --- a/llvm/include/llvm/ADT/Hashing.h +++ b/llvm/include/llvm/ADT/Hashing.h @@ -157,10 +157,10 @@ inline uint32_t fetch32(const char *p) { } /// Some primes between 2^63 and 2^64 for various uses. -static const uint64_t k0 = 0xc3a5c85c97cb3127ULL; -static const uint64_t k1 = 0xb492b66fbe98f273ULL; -static const uint64_t k2 = 0x9ae16a3b2f90404fULL; -static const uint64_t k3 = 0xc949d7c7509e6557ULL; +static constexpr uint64_t k0 = 0xc3a5c85c97cb3127ULL; +static constexpr uint64_t k1 = 0xb492b66fbe98f273ULL; +static constexpr uint64_t k2 = 0x9ae16a3b2f90404fULL; +static constexpr uint64_t k3 = 0xc949d7c7509e6557ULL; /// Bitwise right rotate. /// Normally this will compile to a single instruction, especially if the diff --git a/llvm/include/llvm/ADT/SparseMultiSet.h b/llvm/include/llvm/ADT/SparseMultiSet.h index d9d3ff459267..307d2c3f84e5 100644 --- a/llvm/include/llvm/ADT/SparseMultiSet.h +++ b/llvm/include/llvm/ADT/SparseMultiSet.h @@ -94,7 +94,7 @@ class SparseMultiSet { /// tombstones, in which case they are actually nodes in a single-linked /// freelist of recyclable slots. struct SMSNode { - static const unsigned INVALID = ~0U; + static constexpr unsigned INVALID = ~0U; ValueT Data; unsigned Prev; diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index add5d37f89f7..98c120fe2d2e 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -56,7 +56,7 @@ namespace llvm { /// general safe to store a StringRef. class LLVM_GSL_POINTER StringRef { public: - static const size_t npos = ~size_t(0); + static constexpr size_t npos = ~size_t(0); using iterator = const char *; using const_iterator = const char *; diff --git a/llvm/include/llvm/Support/BranchProbability.h b/llvm/include/llvm/Support/BranchProbability.h index cd9d369b4f4e..6c7ad1fe2a52 100644 --- a/llvm/include/llvm/Support/BranchProbability.h +++ b/llvm/include/llvm/Support/BranchProbability.h @@ -32,8 +32,8 @@ class BranchProbability { uint32_t N; // Denominator, which is a constant value. - static const uint32_t D = 1u << 31; - static const uint32_t UnknownN = UINT32_MAX; + static constexpr uint32_t D = 1u << 31; + static constexpr uint32_t UnknownN = UINT32_MAX; // Construct a BranchProbability with only numerator assuming the denominator // is 1<<31. For internal use only. diff --git a/llvm/include/llvm/Support/Error.h b/llvm/include/llvm/Support/Error.h index b29a247ff8ce..9dd1bb7cb96d 100644 --- a/llvm/include/llvm/Support/Error.h +++ b/llvm/include/llvm/Support/Error.h @@ -440,7 +440,7 @@ template class LLVM_NODISCARD Expected { template friend class ExpectedAsOutParameter; template friend class Expected; - static const bool isRef = std::is_reference::value; + static constexpr bool isRef = std::is_reference::value; using wrap = std::reference_wrapper>; diff --git a/llvm/include/llvm/Support/ErrorOr.h b/llvm/include/llvm/Support/ErrorOr.h index 4750cd832ef7..1fbccc1d1e26 100644 --- a/llvm/include/llvm/Support/ErrorOr.h +++ b/llvm/include/llvm/Support/ErrorOr.h @@ -56,7 +56,7 @@ template class ErrorOr { template friend class ErrorOr; - static const bool isRef = std::is_reference::value; + static constexpr bool isRef = std::is_reference::value; using wrap = std::reference_wrapper>; diff --git a/llvm/include/llvm/Support/ScaledNumber.h b/llvm/include/llvm/Support/ScaledNumber.h index 552da34f357b..a5261e419986 100644 --- a/llvm/include/llvm/Support/ScaledNumber.h +++ b/llvm/include/llvm/Support/ScaledNumber.h @@ -418,7 +418,7 @@ namespace llvm { class raw_ostream; class ScaledNumberBase { public: - static const int DefaultPrecision = 10; + static constexpr int DefaultPrecision = 10; static void dump(uint64_t D, int16_t E, int Width); static raw_ostream &print(raw_ostream &OS, uint64_t D, int16_t E, int Width, @@ -499,7 +499,7 @@ public: private: typedef std::numeric_limits DigitsLimits; - static const int Width = sizeof(DigitsType) * 8; + static constexpr int Width = sizeof(DigitsType) * 8; static_assert(Width <= 64, "invalid integer width for digits"); private: diff --git a/llvm/include/llvm/Support/circular_raw_ostream.h b/llvm/include/llvm/Support/circular_raw_ostream.h index a72acd4fe002..d2f01ea6a7f2 100644 --- a/llvm/include/llvm/Support/circular_raw_ostream.h +++ b/llvm/include/llvm/Support/circular_raw_ostream.h @@ -27,12 +27,12 @@ namespace llvm { /// stream and is responsible for cleanup, memory management /// issues, etc. /// - static const bool TAKE_OWNERSHIP = true; + static constexpr bool TAKE_OWNERSHIP = true; /// REFERENCE_ONLY - Tell this stream it should not manage the /// held stream. /// - static const bool REFERENCE_ONLY = false; + static constexpr bool REFERENCE_ONLY = false; private: /// TheStream - The real stream we output to. We set it to be diff --git a/llvm/include/llvm/Support/raw_ostream.h b/llvm/include/llvm/Support/raw_ostream.h index 30a1e62330df..f7223dc8c8cf 100644 --- a/llvm/include/llvm/Support/raw_ostream.h +++ b/llvm/include/llvm/Support/raw_ostream.h @@ -86,16 +86,16 @@ public: RESET, }; - static const Colors BLACK = Colors::BLACK; - static const Colors RED = Colors::RED; - static const Colors GREEN = Colors::GREEN; - static const Colors YELLOW = Colors::YELLOW; - static const Colors BLUE = Colors::BLUE; - static const Colors MAGENTA = Colors::MAGENTA; - static const Colors CYAN = Colors::CYAN; - static const Colors WHITE = Colors::WHITE; - static const Colors SAVEDCOLOR = Colors::SAVEDCOLOR; - static const Colors RESET = Colors::RESET; + static constexpr Colors BLACK = Colors::BLACK; + static constexpr Colors RED = Colors::RED; + static constexpr Colors GREEN = Colors::GREEN; + static constexpr Colors YELLOW = Colors::YELLOW; + static constexpr Colors BLUE = Colors::BLUE; + static constexpr Colors MAGENTA = Colors::MAGENTA; + static constexpr Colors CYAN = Colors::CYAN; + static constexpr Colors WHITE = Colors::WHITE; + static constexpr Colors SAVEDCOLOR = Colors::SAVEDCOLOR; + static constexpr Colors RESET = Colors::RESET; explicit raw_ostream(bool unbuffered = false) : BufferMode(unbuffered ? BufferKind::Unbuffered diff --git a/llvm/lib/Support/BranchProbability.cpp b/llvm/lib/Support/BranchProbability.cpp index 195e2d58d8e1..60d5478a9052 100644 --- a/llvm/lib/Support/BranchProbability.cpp +++ b/llvm/lib/Support/BranchProbability.cpp @@ -19,7 +19,7 @@ using namespace llvm; -const uint32_t BranchProbability::D; +constexpr uint32_t BranchProbability::D; raw_ostream &BranchProbability::print(raw_ostream &OS) const { if (isUnknown()) diff --git a/llvm/lib/Support/StringRef.cpp b/llvm/lib/Support/StringRef.cpp index 104482de4ad7..6ae2a2b532aa 100644 --- a/llvm/lib/Support/StringRef.cpp +++ b/llvm/lib/Support/StringRef.cpp @@ -19,7 +19,7 @@ using namespace llvm; // MSVC emits references to this into the translation units which reference it. #ifndef _MSC_VER -const size_t StringRef::npos; +constexpr size_t StringRef::npos; #endif // strncasecmp() is not available on non-POSIX systems, so define an diff --git a/llvm/lib/Support/raw_ostream.cpp b/llvm/lib/Support/raw_ostream.cpp index 7e9428e5dbc9..fa69fe3c7154 100644 --- a/llvm/lib/Support/raw_ostream.cpp +++ b/llvm/lib/Support/raw_ostream.cpp @@ -65,16 +65,16 @@ using namespace llvm; -const raw_ostream::Colors raw_ostream::BLACK; -const raw_ostream::Colors raw_ostream::RED; -const raw_ostream::Colors raw_ostream::GREEN; -const raw_ostream::Colors raw_ostream::YELLOW; -const raw_ostream::Colors raw_ostream::BLUE; -const raw_ostream::Colors raw_ostream::MAGENTA; -const raw_ostream::Colors raw_ostream::CYAN; -const raw_ostream::Colors raw_ostream::WHITE; -const raw_ostream::Colors raw_ostream::SAVEDCOLOR; -const raw_ostream::Colors raw_ostream::RESET; +constexpr raw_ostream::Colors raw_ostream::BLACK; +constexpr raw_ostream::Colors raw_ostream::RED; +constexpr raw_ostream::Colors raw_ostream::GREEN; +constexpr raw_ostream::Colors raw_ostream::YELLOW; +constexpr raw_ostream::Colors raw_ostream::BLUE; +constexpr raw_ostream::Colors raw_ostream::MAGENTA; +constexpr raw_ostream::Colors raw_ostream::CYAN; +constexpr raw_ostream::Colors raw_ostream::WHITE; +constexpr raw_ostream::Colors raw_ostream::SAVEDCOLOR; +constexpr raw_ostream::Colors raw_ostream::RESET; raw_ostream::~raw_ostream() { // raw_ostream's subclasses should take care to flush the buffer -- GitLab From 17f6e18acf5bedd505a7a2194b556fc6f559ffb4 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin Date: Wed, 22 Apr 2020 09:38:48 +0100 Subject: [PATCH 062/910] [AArch64][SVE] Add SVE intrinsic for LD1RQ Summary: Adds the following intrinsic for contiguous load & replicate: - @llvm.aarch64.sve.ld1rq The LD1RQ intrinsic only needs the SImmS16XForm added by this patch. The others (SImmS2XForm, SImmS3XForm & SImmS4XForm) were added for consistency. Reviewers: andwar, sdesmalen, efriedma, cameron.mcinally, dancgr, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, danielkiss, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D76929 --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 2 + .../Target/AArch64/AArch64ISelLowering.cpp | 21 ++ llvm/lib/Target/AArch64/AArch64ISelLowering.h | 1 + .../lib/Target/AArch64/AArch64InstrFormats.td | 21 +- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 29 +++ .../CodeGen/AArch64/sve-intrinsics-loads.ll | 181 ++++++++++++++++++ 6 files changed, 251 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index c32fd480d95d..5edbe70b63d5 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1307,6 +1307,8 @@ def int_aarch64_sve_ldnt1 : AdvSIMD_1Vec_PredLoad_Intrinsic; def int_aarch64_sve_ldnf1 : AdvSIMD_1Vec_PredLoad_Intrinsic; def int_aarch64_sve_ldff1 : AdvSIMD_1Vec_PredLoad_Intrinsic; +def int_aarch64_sve_ld1rq : AdvSIMD_1Vec_PredLoad_Intrinsic; + // // Stores // diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index cd19696e672b..ba31520d8837 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1424,6 +1424,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { case AArch64ISD::LDNF1S: return "AArch64ISD::LDNF1S"; case AArch64ISD::LDFF1: return "AArch64ISD::LDFF1"; case AArch64ISD::LDFF1S: return "AArch64ISD::LDFF1S"; + case AArch64ISD::LD1RQ: return "AArch64ISD::LD1RQ"; case AArch64ISD::GLD1: return "AArch64ISD::GLD1"; case AArch64ISD::GLD1_SCALED: return "AArch64ISD::GLD1_SCALED"; case AArch64ISD::GLD1_SXTW: return "AArch64ISD::GLD1_SXTW"; @@ -11622,6 +11623,24 @@ static SDValue performLDNT1Combine(SDNode *N, SelectionDAG &DAG) { return L; } +static SDValue performLD1RQCombine(SDNode *N, SelectionDAG &DAG) { + SDLoc DL(N); + EVT VT = N->getValueType(0); + + EVT LoadVT = VT; + if (VT.isFloatingPoint()) + LoadVT = VT.changeTypeToInteger(); + + SDValue Ops[] = {N->getOperand(0), N->getOperand(2), N->getOperand(3)}; + SDValue Load = DAG.getNode(AArch64ISD::LD1RQ, DL, {LoadVT, MVT::Other}, Ops); + SDValue LoadChain = SDValue(Load.getNode(), 1); + + if (VT.isFloatingPoint()) + Load = DAG.getNode(ISD::BITCAST, DL, VT, Load.getValue(0)); + + return DAG.getMergeValues({ Load, LoadChain }, DL); +} + static SDValue performST1Combine(SDNode *N, SelectionDAG &DAG) { SDLoc DL(N); SDValue Data = N->getOperand(2); @@ -13211,6 +13230,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, return performNEONPostLDSTCombine(N, DCI, DAG); case Intrinsic::aarch64_sve_ldnt1: return performLDNT1Combine(N, DAG); + case Intrinsic::aarch64_sve_ld1rq: + return performLD1RQCombine(N, DAG); case Intrinsic::aarch64_sve_ldnt1_gather_scalar_offset: return performGatherLoadCombine(N, DAG, AArch64ISD::GLDNT1); case Intrinsic::aarch64_sve_ldnt1_gather: diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 23ee45286351..8749d808336e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -226,6 +226,7 @@ enum NodeType : unsigned { LDNF1S, LDFF1, LDFF1S, + LD1RQ, // Unsigned gather loads. GLD1, diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 9d254bdf6940..061e2a0ec619 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -483,6 +483,19 @@ def uimm6s16 : Operand, ImmLeafgetTargetConstant(N->getSExtValue() / 2, SDLoc(N), MVT::i64); +}]>; +def SImmS3XForm : SDNodeXFormgetTargetConstant(N->getSExtValue() / 3, SDLoc(N), MVT::i64); +}]>; +def SImmS4XForm : SDNodeXFormgetTargetConstant(N->getSExtValue() / 4, SDLoc(N), MVT::i64); +}]>; +def SImmS16XForm : SDNodeXFormgetTargetConstant(N->getSExtValue() / 16, SDLoc(N), MVT::i64); +}]>; + // simm6sN predicate - True if the immediate is a multiple of N in the range // [-32 * N, 31 * N]. def SImm6s1Operand : SImmScaledMemoryIndexed<6, 1>; @@ -506,27 +519,27 @@ def simm4s1 : Operand, ImmLeaf, ImmLeaf=-16 && Imm <= 14 && (Imm % 2) == 0x0; }]> { +[{ return Imm >=-16 && Imm <= 14 && (Imm % 2) == 0x0; }], SImmS2XForm> { let PrintMethod = "printImmScale<2>"; let ParserMatchClass = SImm4s2Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s3 : Operand, ImmLeaf=-24 && Imm <= 21 && (Imm % 3) == 0x0; }]> { +[{ return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; }], SImmS3XForm> { let PrintMethod = "printImmScale<3>"; let ParserMatchClass = SImm4s3Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s4 : Operand, ImmLeaf=-32 && Imm <= 28 && (Imm % 4) == 0x0; }]> { +[{ return Imm >=-32 && Imm <= 28 && (Imm % 4) == 0x0; }], SImmS4XForm> { let PrintMethod = "printImmScale<4>"; let ParserMatchClass = SImm4s4Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s16 : Operand, ImmLeaf=-128 && Imm <= 112 && (Imm % 16) == 0x0; }]> { +[{ return Imm >=-128 && Imm <= 112 && (Imm % 16) == 0x0; }], SImmS16XForm> { let PrintMethod = "printImmScale<16>"; let ParserMatchClass = SImm4s16Operand; let DecoderMethod = "DecodeSImm<4>"; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 1712cd260f33..52e0377fdecc 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -31,6 +31,16 @@ def AArch64ldff1 : SDNode<"AArch64ISD::LDFF1", SDT_AArch64_LD1, [SDNPHasChain, S def AArch64ldnf1s : SDNode<"AArch64ISD::LDNF1S", SDT_AArch64_LD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue, SDNPOutGlue]>; def AArch64ldff1s : SDNode<"AArch64ISD::LDFF1S", SDT_AArch64_LD1, [SDNPHasChain, SDNPMayLoad, SDNPOptInGlue, SDNPOutGlue]>; +// Contiguous load and replicate - node definitions +// + +def SDT_AArch64_LD1RQ : SDTypeProfile<1, 2, [ + SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>, + SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0,1> +]>; + +def AArch64ld1rq : SDNode<"AArch64ISD::LD1RQ", SDT_AArch64_LD1RQ, [SDNPHasChain, SDNPMayLoad]>; + // Gather loads - node definitions // def SDT_AArch64_GATHER_SV : SDTypeProfile<1, 4, [ @@ -1317,6 +1327,25 @@ multiclass sve_prefetch; + // LD1R of 128-bit masked data + def : Pat<(nxv16i8 (AArch64ld1rq PPR:$gp, GPR64:$base)), + (LD1RQ_B_IMM $gp, $base, (i64 0))>; + def : Pat<(nxv8i16 (AArch64ld1rq PPR:$gp, GPR64:$base)), + (LD1RQ_H_IMM $gp, $base, (i64 0))>; + def : Pat<(nxv4i32 (AArch64ld1rq PPR:$gp, GPR64:$base)), + (LD1RQ_W_IMM $gp, $base, (i64 0))>; + def : Pat<(nxv2i64 (AArch64ld1rq PPR:$gp, GPR64:$base)), + (LD1RQ_D_IMM $gp, $base, (i64 0))>; + + def : Pat<(nxv16i8 (AArch64ld1rq PPR:$gp, (add GPR64:$base, (i64 simm4s16:$imm)))), + (LD1RQ_B_IMM $gp, $base, simm4s16:$imm)>; + def : Pat<(nxv8i16 (AArch64ld1rq PPR:$gp, (add GPR64:$base, (i64 simm4s16:$imm)))), + (LD1RQ_H_IMM $gp, $base, simm4s16:$imm)>; + def : Pat<(nxv4i32 (AArch64ld1rq PPR:$gp, (add GPR64:$base, (i64 simm4s16:$imm)))), + (LD1RQ_W_IMM $gp, $base, simm4s16:$imm)>; + def : Pat<(nxv2i64 (AArch64ld1rq PPR:$gp, (add GPR64:$base, (i64 simm4s16:$imm)))), + (LD1RQ_D_IMM $gp, $base, simm4s16:$imm)>; + def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll index 8f180d008306..74717d393f55 100644 --- a/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll @@ -1,5 +1,178 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s +; +; LD1RQB +; + +define @ld1rqb_i8( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8: +; CHECK: ld1rqb { z0.b }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %addr) + ret %res +} + +define @ld1rqb_i8_imm( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8_imm: +; CHECK: ld1rqb { z0.b }, p0/z, [x0, #16] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i8, i8* %addr, i8 16 + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %ptr) + ret %res +} + +define @ld1rqb_i8_imm_lower_bound( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8_imm_lower_bound: +; CHECK: ld1rqb { z0.b }, p0/z, [x0, #-128] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i8, i8* %addr, i8 -128 + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %ptr) + ret %res +} + +define @ld1rqb_i8_imm_upper_bound( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8_imm_upper_bound: +; CHECK: ld1rqb { z0.b }, p0/z, [x0, #112] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i8, i8* %addr, i8 112 + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %ptr) + ret %res +} + +define @ld1rqb_i8_imm_out_of_lower_bound( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8_imm_out_of_lower_bound: +; CHECK: sub x8, x0, #129 +; CHECK-NEXT: ld1rqb { z0.b }, p0/z, [x8] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i8, i8* %addr, i64 -129 + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %ptr) + ret %res +} + +define @ld1rqb_i8_imm_out_of_upper_bound( %pred, i8* %addr) { +; CHECK-LABEL: ld1rqb_i8_imm_out_of_upper_bound: +; CHECK: add x8, x0, #113 +; CHECK-NEXT: ld1rqb { z0.b }, p0/z, [x8] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i8, i8* %addr, i64 113 + %res = call @llvm.aarch64.sve.ld1rq.nxv16i8( %pred, i8* %ptr) + ret %res +} + +; +; LD1RQH +; + +define @ld1rqh_i16( %pred, i16* %addr) { +; CHECK-LABEL: ld1rqh_i16: +; CHECK: ld1rqh { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv8i16( %pred, i16* %addr) + ret %res +} + +define @ld1rqh_f16( %pred, half* %addr) { +; CHECK-LABEL: ld1rqh_f16: +; CHECK: ld1rqh { z0.h }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv8f16( %pred, half* %addr) + ret %res +} + +define @ld1rqh_i16_imm( %pred, i16* %addr) { +; CHECK-LABEL: ld1rqh_i16_imm: +; CHECK: ld1rqh { z0.h }, p0/z, [x0, #-64] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i16, i16* %addr, i16 -32 + %res = call @llvm.aarch64.sve.ld1rq.nxv8i16( %pred, i16* %ptr) + ret %res +} + +define @ld1rqh_f16_imm( %pred, half* %addr) { +; CHECK-LABEL: ld1rqh_f16_imm: +; CHECK: ld1rqh { z0.h }, p0/z, [x0, #-16] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds half, half* %addr, i16 -8 + %res = call @llvm.aarch64.sve.ld1rq.nxv8f16( %pred, half* %ptr) + ret %res +} + +; +; LD1RQW +; + +define @ld1rqw_i32( %pred, i32* %addr) { +; CHECK-LABEL: ld1rqw_i32: +; CHECK: ld1rqw { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv4i32( %pred, i32* %addr) + ret %res +} + +define @ld1rqw_f32( %pred, float* %addr) { +; CHECK-LABEL: ld1rqw_f32: +; CHECK: ld1rqw { z0.s }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv4f32( %pred, float* %addr) + ret %res +} + +define @ld1rqw_i32_imm( %pred, i32* %addr) { +; CHECK-LABEL: ld1rqw_i32_imm: +; CHECK: ld1rqw { z0.s }, p0/z, [x0, #112] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i32, i32* %addr, i32 28 + %res = call @llvm.aarch64.sve.ld1rq.nxv4i32( %pred, i32* %ptr) + ret %res +} + +define @ld1rqw_f32_imm( %pred, float* %addr) { +; CHECK-LABEL: ld1rqw_f32_imm: +; CHECK: ld1rqw { z0.s }, p0/z, [x0, #32] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds float, float* %addr, i32 8 + %res = call @llvm.aarch64.sve.ld1rq.nxv4f32( %pred, float* %ptr) + ret %res +} + +; +; LD1RQD +; + +define @ld1rqd_i64( %pred, i64* %addr) { +; CHECK-LABEL: ld1rqd_i64: +; CHECK: ld1rqd { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv2i64( %pred, i64* %addr) + ret %res +} + +define @ld1rqd_f64( %pred, double* %addr) { +; CHECK-LABEL: ld1rqd_f64: +; CHECK: ld1rqd { z0.d }, p0/z, [x0] +; CHECK-NEXT: ret + %res = call @llvm.aarch64.sve.ld1rq.nxv2f64( %pred, double* %addr) + ret %res +} + +define @ld1rqd_i64_imm( %pred, i64* %addr) { +; CHECK-LABEL: ld1rqd_i64_imm: +; CHECK: ld1rqd { z0.d }, p0/z, [x0, #64] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds i64, i64* %addr, i64 8 + %res = call @llvm.aarch64.sve.ld1rq.nxv2i64( %pred, i64* %ptr) + ret %res +} + +define @ld1rqd_f64_imm( %pred, double* %addr) { +; CHECK-LABEL: ld1rqd_f64_imm: +; CHECK: ld1rqd { z0.d }, p0/z, [x0, #-128] +; CHECK-NEXT: ret + %ptr = getelementptr inbounds double, double* %addr, i64 -16 + %res = call @llvm.aarch64.sve.ld1rq.nxv2f64( %pred, double* %ptr) + ret %res +} + ; ; LDNT1B ; @@ -79,6 +252,14 @@ define @ldnt1d_f64( %pred, double* %addr) ret %res } +declare @llvm.aarch64.sve.ld1rq.nxv16i8(, i8*) +declare @llvm.aarch64.sve.ld1rq.nxv8i16(, i16*) +declare @llvm.aarch64.sve.ld1rq.nxv4i32(, i32*) +declare @llvm.aarch64.sve.ld1rq.nxv2i64(, i64*) +declare @llvm.aarch64.sve.ld1rq.nxv8f16(, half*) +declare @llvm.aarch64.sve.ld1rq.nxv4f32(, float*) +declare @llvm.aarch64.sve.ld1rq.nxv2f64(, double*) + declare @llvm.aarch64.sve.ldnt1.nxv16i8(, i8*) declare @llvm.aarch64.sve.ldnt1.nxv8i16(, i16*) declare @llvm.aarch64.sve.ldnt1.nxv4i32(, i32*) -- GitLab From 727e6fb84a3a6b5568d24edb794083ca2c750038 Mon Sep 17 00:00:00 2001 From: Lucas Prates Date: Wed, 22 Apr 2020 11:31:41 +0100 Subject: [PATCH 063/910] [NFC][llvm][X86] Adding missing -mtiple to X86 test. The modified test was missing the specification of the intended triple in its run line, assuming X86 is the default. --- llvm/test/CodeGen/X86/pr45563.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/X86/pr45563.ll b/llvm/test/CodeGen/X86/pr45563.ll index 0c205f665b82..06509a77ca76 100644 --- a/llvm/test/CodeGen/X86/pr45563.ll +++ b/llvm/test/CodeGen/X86/pr45563.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O3 -mattr=avx | FileCheck %s +; RUN: llc < %s -O3 -mattr=avx -mtriple=x86_64-unknown-unknown | FileCheck %s ; Bug 45563: ; The LowerMLOAD() method AVX masked load branch should -- GitLab From e9aac2c3ef4ccbe26a05e9aaea90e0df66cec04d Mon Sep 17 00:00:00 2001 From: James Henderson Date: Mon, 20 Apr 2020 14:23:01 +0100 Subject: [PATCH 064/910] [llvm-objdump] Look in all viable sections for call/branch targets Prior to this patch, llvm-objdump would only look in the last section (according to the section header table order) that matched an address for a symbol when identifying the target symbol of a call or branch operation. If there are multiple sections with the same address, due to some of them being empty, it did not look in those, even if the symbol couldn't be found in the first section looked in. This patch causes llvm-objdump to look in all sections for possible candidate symbols. If there are multiple possible symbols, it picks one from a non-empty section, if possible (as that is more likely to be the "real" symbol since functions can't really be in emptiy sections), before falling back to those in empty sections. If all else fails, it falls back to absolute symbols as it did before. Differential Revision: https://reviews.llvm.org/D78549 Reviewed by: grimar, Higuoxing --- .../X86/disassemble-same-section-addr.test | 91 +++++++++++++++++-- llvm/tools/llvm-objdump/llvm-objdump.cpp | 66 ++++++++------ 2 files changed, 122 insertions(+), 35 deletions(-) diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test index cbb77884f0c3..4b0da011c9d4 100644 --- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test +++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test @@ -4,14 +4,34 @@ ## the section. The test uses YAML for the input, as we need a fully linked ELF ## to reproduce the original failure. -# RUN: yaml2obj %s -o %t1 -D SECTION=.second -# RUN: llvm-objdump -d %t1 | FileCheck %s -# RUN: yaml2obj %s -o %t2 -D SECTION=.first -## FIXME: this case should print "" too. -# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefix=FAIL +## Two empty sections, one with symbol in, one without. +# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS +# RUN: llvm-objdump -d %t1 | FileCheck %s --check-prefix=TARGET +# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS +# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefix=TARGET -# CHECK: callq 0x5 -# FAIL: callq 0x5{{$}} +## Two sections, one empty with symbol, other non-empty, without symbol. +# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS +# RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=TARGET +# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS +# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=TARGET + +## Fall back to absolute symbol if no symbol found in candidate sections. +# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS +# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=ABSOLUTE + +## Show that other symbols with reserved st_shndx values are treated as absolute +## symbols. +# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC +# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=ABSOLUTE + +## Print no target if no symbol in section/absolute symbol found. +# RUN: llvm-objcopy %t5 %t7 -N other +# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL + +# TARGET: callq 0x5 +# ABSOLUTE: callq 0x5 +# FAIL: callq 0x5{{$}} --- !ELF FileHeader: @@ -24,16 +44,71 @@ Sections: Type: SHT_PROGBITS Flags: [SHF_ALLOC, SHF_EXECINSTR] Address: 0x0 - Content: e800000000 # Call instruction to next address. + Content: e800000000 ## Call instruction to next address. - Name: .first Type: SHT_PROGBITS Flags: [SHF_ALLOC, SHF_EXECINSTR] Address: 0x5 + Size: [[SIZE1]] - Name: .second Type: SHT_PROGBITS Flags: [SHF_ALLOC, SHF_EXECINSTR] Address: 0x5 + Size: [[SIZE2]] Symbols: - Name: target Section: [[SECTION]] Value: 0x5 + - Name: other + Index: [[INDEX]] + Value: 0x0 + +## Two empty sections, both with symbols. +# RUN: yaml2obj %s --docnum=2 -o %t7 -D SIZE1=0 -D SIZE2=0 -D SYMVAL1=0x5 -D SYMVAL2=0x5 +# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=SECOND + +## Two sections, both with symbols, one empty, the other not. +# RUN: yaml2obj %s --docnum=2 -o %t8 -D SIZE1=1 -D SIZE2=0 -D SYMVAL1=0x5 -D SYMVAL2=0x5 +# RUN: llvm-objdump -d %t8 | FileCheck %s --check-prefix=FIRST +# RUN: yaml2obj %s --docnum=2 -o %t9 -D SIZE1=0 -D SIZE2=1 -D SYMVAL1=0x5 -D SYMVAL2=0x5 +# RUN: llvm-objdump -d %t9 | FileCheck %s --check-prefix=SECOND + +## Two sections, both with symbols, one empty, other not, symbol in non-empty +## section has value higher than target address. +# RUN: yaml2obj %s --docnum=2 -o %t10 -D SIZE1=1 -D SIZE2=0 -D SYMVAL1=0x6 -D SYMVAL2=0x5 +# RUN: llvm-objdump -d %t10 | FileCheck %s --check-prefix=SECOND +# RUN: yaml2obj %s --docnum=2 -o %t11 -D SIZE1=0 -D SIZE2=1 -D SYMVAL1=0x5 -D SYMVAL2=0x6 +# RUN: llvm-objdump -d %t11 | FileCheck %s --check-prefix=FIRST + +# FIRST: callq 0x5 +# SECOND: callq 0x5 + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .caller + Type: SHT_PROGBITS + Flags: [SHF_ALLOC, SHF_EXECINSTR] + Address: 0x0 + Content: e800000000 ## Call instruction to next address. + - Name: .first + Type: SHT_PROGBITS + Flags: [SHF_ALLOC, SHF_EXECINSTR] + Address: 0x5 + Size: [[SIZE1]] + - Name: .second + Type: SHT_PROGBITS + Flags: [SHF_ALLOC, SHF_EXECINSTR] + Address: 0x5 + Size: [[SIZE2]] +Symbols: + - Name: first + Section: .first + Value: [[SYMVAL1]] + - Name: second + Section: .second + Value: [[SYMVAL2]] diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 0eeb337c1b7b..4ce8f691acbc 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -1245,12 +1245,17 @@ static void disassembleObject(const Target *TheTarget, const ObjectFile *Obj, addPltEntries(Obj, AllSymbols, Saver); // Create a mapping from virtual address to section. An empty section can - // cause more than one section at the same address. Use a stable sort to - // stabilize the output. + // cause more than one section at the same address. Sort such sections to be + // before same-addressed non-empty sections so that symbol lookups prefer the + // non-empty section. std::vector> SectionAddresses; for (SectionRef Sec : Obj->sections()) SectionAddresses.emplace_back(Sec.getAddress(), Sec); - llvm::stable_sort(SectionAddresses, llvm::less_first()); + llvm::stable_sort(SectionAddresses, [](const auto &LHS, const auto &RHS) { + if (LHS.first != RHS.first) + return LHS.first < RHS.first; + return LHS.second.getSize() < RHS.second.getSize(); + }); // Linked executables (.exe and .dll files) typically don't include a real // symbol table but they might contain an export table. @@ -1520,41 +1525,48 @@ static void disassembleObject(const Target *TheTarget, const ObjectFile *Obj, // through a relocation. // // In a non-relocatable object, the target may be in any section. + // In that case, locate the section(s) containing the target address + // and find the symbol in one of those, if possible. // // N.B. We don't walk the relocations in the relocatable case yet. - auto *TargetSectionSymbols = &Symbols; + std::vector TargetSectionSymbols; if (!Obj->isRelocatableObject()) { - auto It = partition_point( + auto It = llvm::partition_point( SectionAddresses, [=](const std::pair &O) { return O.first <= Target; }); - if (It != SectionAddresses.begin()) { + uint64_t TargetSecAddr = 0; + while (It != SectionAddresses.begin()) { --It; - TargetSectionSymbols = &AllSymbols[It->second]; - } else { - TargetSectionSymbols = &AbsoluteSymbols; + if (TargetSecAddr == 0) + TargetSecAddr = It->first; + if (It->first != TargetSecAddr) + break; + TargetSectionSymbols.push_back(&AllSymbols[It->second]); } + } else { + TargetSectionSymbols.push_back(&Symbols); } - - // Find the last symbol in the section whose offset is less than - // or equal to the target. If there isn't a section that contains - // the target, find the nearest preceding absolute symbol. - auto TargetSym = partition_point( - *TargetSectionSymbols, - [=](const SymbolInfoTy &O) { - return O.Addr <= Target; - }); - if (TargetSym == TargetSectionSymbols->begin()) { - TargetSectionSymbols = &AbsoluteSymbols; - TargetSym = partition_point( - AbsoluteSymbols, - [=](const SymbolInfoTy &O) { - return O.Addr <= Target; - }); + TargetSectionSymbols.push_back(&AbsoluteSymbols); + + // Find the last symbol in the first candidate section whose offset + // is less than or equal to the target. If there are no such + // symbols, try in the next section and so on, before finally using + // the nearest preceding absolute symbol (if any), if there are no + // other valid symbols. + const SymbolInfoTy *TargetSym = nullptr; + for (const SectionSymbolsTy *TargetSymbols : TargetSectionSymbols) { + auto It = llvm::partition_point( + *TargetSymbols, + [=](const SymbolInfoTy &O) { return O.Addr <= Target; }); + if (It != TargetSymbols->begin()) { + TargetSym = &*(It - 1); + break; + } } - if (TargetSym != TargetSectionSymbols->begin()) { - --TargetSym; + + if (TargetSym != nullptr) { uint64_t TargetAddress = TargetSym->Addr; std::string TargetName = TargetSym->Name.str(); if (Demangle) -- GitLab From 673612a0358b6ec953749d7c57ff33da73954e11 Mon Sep 17 00:00:00 2001 From: Peter Smith Date: Wed, 22 Apr 2020 11:57:13 +0100 Subject: [PATCH 065/910] [LLD][ELF][ARM] Replace adr, ldr with .inst .reloc in test [NFC] After D78301 MC no longer emits a relocation for this case. Change to use .inst and .reloc to synthesize the same instruction and relocation. One more test case I missed. --- lld/test/ELF/arm-thumb-pc8-weak.s | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/lld/test/ELF/arm-thumb-pc8-weak.s b/lld/test/ELF/arm-thumb-pc8-weak.s index e0fe2442347e..e42f48963179 100644 --- a/lld/test/ELF/arm-thumb-pc8-weak.s +++ b/lld/test/ELF/arm-thumb-pc8-weak.s @@ -1,7 +1,7 @@ // REQUIRES: arm -// RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv6a-none-linux-gnueabi %s -o %t +// RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv5-none-linux-gnueabi %s -o %t // RUN: ld.lld %t -o %t2 -// RUN: llvm-objdump --no-show-raw-insn --triple=thumbv6a-none-linux-gnueabi -d %t2 +// RUN: llvm-objdump --no-show-raw-insn --triple=thumbv6a-none-linux-gnueabi -d %t2 | FileCheck %s /// Check that the ARM ABI rules for undefined weak symbols are applied. /// Relative relocations are resolved to the place. Although we can't encode @@ -16,9 +16,12 @@ .global _start _start: /// R_ARM_THM_PC8 - adr r0, target - ldr r0, target - -// CHECK: 000110b4 _start: -// CHECK-NEXT: 110b4: adr r0, #0 + /// adr r0, target + .inst.n 0xa0ff + .reloc 0, R_ARM_THM_PC8, target + /// ldr r0, target + .inst.n 0x48ff + .reloc 2, R_ARM_THM_PC8, target +// CHECK: 000200b4 <_start>: +// CHECK-NEXT: 200b4: adr r0, #0 // CHECK-NEXT: ldr r0, [pc, #0] -- GitLab From b2f06bd20bdec80f2637463644b690f54fe09fdc Mon Sep 17 00:00:00 2001 From: David Zarzycki Date: Wed, 22 Apr 2020 07:45:47 -0400 Subject: [PATCH 066/910] [libc++ testing] Fix unused variable warning turned error --- .../test/std/strings/basic.string.hash/char_type_hash.fail.cpp | 1 + .../strings/string.view/string.view.hash/char_type.hash.fail.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/libcxx/test/std/strings/basic.string.hash/char_type_hash.fail.cpp b/libcxx/test/std/strings/basic.string.hash/char_type_hash.fail.cpp index a4f3f8c483b7..9d90af9f2018 100644 --- a/libcxx/test/std/strings/basic.string.hash/char_type_hash.fail.cpp +++ b/libcxx/test/std/strings/basic.string.hash/char_type_hash.fail.cpp @@ -57,6 +57,7 @@ void test() { typedef std::basic_string > str_t; std::hash h; // expected-error-re 4 {{{{call to implicitly-deleted default constructor of 'std::hash'|implicit instantiation of undefined template}} {{.+}}}}}} + (void)h; } int main(int, char**) { diff --git a/libcxx/test/std/strings/string.view/string.view.hash/char_type.hash.fail.cpp b/libcxx/test/std/strings/string.view/string.view.hash/char_type.hash.fail.cpp index a44873fb1008..2f9293598395 100644 --- a/libcxx/test/std/strings/string.view/string.view.hash/char_type.hash.fail.cpp +++ b/libcxx/test/std/strings/string.view/string.view.hash/char_type.hash.fail.cpp @@ -58,6 +58,7 @@ void test() { typedef std::basic_string_view > strv_t; std::hash h; // expected-error-re 4 {{{{call to implicitly-deleted default constructor of 'std::hash'|implicit instantiation of undefined template}} {{.+}}}}}} + (void)h; } int main(int, char**) { -- GitLab From d625b4b081f9ea2d96d5bdfc1f05925b30d8b1a3 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 17 Apr 2020 09:25:37 +0100 Subject: [PATCH 067/910] [AMDGPU] Add missing AReg classes Add 96-bit, 160-bit and 256-bit AReg classes to match VReg and SReg. NFC as far as I know, but it may avoid weird legalization problems. Differential Revision: https://reviews.llvm.org/D78348 --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 12 ++++++++++++ llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td | 2 +- .../lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 3 +++ .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 1 + .../Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 6 +++++- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 +++++++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 +++++++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 13 +++++++++++++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 3 +++ 9 files changed, 56 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 42ac97aabec9..f1b3cd9b8d20 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -798,6 +798,10 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( } else if (AMDGPU::SReg_96RegClass.contains(Reg)) { IsSGPR = true; Width = 3; + } else if (AMDGPU::AReg_96RegClass.contains(Reg)) { + IsSGPR = false; + IsAGPR = true; + Width = 3; } else if (AMDGPU::SReg_128RegClass.contains(Reg)) { assert(!AMDGPU::TTMP_128RegClass.contains(Reg) && "trap handler registers should not be used"); @@ -816,6 +820,10 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( } else if (AMDGPU::SReg_160RegClass.contains(Reg)) { IsSGPR = true; Width = 5; + } else if (AMDGPU::AReg_160RegClass.contains(Reg)) { + IsSGPR = false; + IsAGPR = true; + Width = 5; } else if (AMDGPU::SReg_256RegClass.contains(Reg)) { assert(!AMDGPU::TTMP_256RegClass.contains(Reg) && "trap handler registers should not be used"); @@ -824,6 +832,10 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( } else if (AMDGPU::VReg_256RegClass.contains(Reg)) { IsSGPR = false; Width = 8; + } else if (AMDGPU::AReg_256RegClass.contains(Reg)) { + IsSGPR = false; + IsAGPR = true; + Width = 8; } else if (AMDGPU::SReg_512RegClass.contains(Reg)) { assert(!AMDGPU::TTMP_512RegClass.contains(Reg) && "trap handler registers should not be used"); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td index af6e8f7ccbf2..df5b106bea09 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td @@ -18,5 +18,5 @@ def VGPRRegBank : RegisterBank<"VGPR", def VCCRegBank : RegisterBank <"VCC", [SReg_1]>; def AGPRRegBank : RegisterBank <"AGPR", - [AGPR_32, AReg_64, AReg_128, AReg_512, AReg_1024] + [AGPR_32, AReg_64, AReg_96, AReg_128, AReg_160, AReg_256, AReg_512, AReg_1024] >; diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index f31925c848fb..17ab79ac62c2 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1942,7 +1942,10 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) { default: return -1; case 1: return AMDGPU::AGPR_32RegClassID; case 2: return AMDGPU::AReg_64RegClassID; + case 3: return AMDGPU::AReg_96RegClassID; case 4: return AMDGPU::AReg_128RegClassID; + case 5: return AMDGPU::AReg_160RegClassID; + case 8: return AMDGPU::AReg_256RegClassID; case 16: return AMDGPU::AReg_512RegClassID; case 32: return AMDGPU::AReg_1024RegClassID; } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index f563e169ace8..ea3b70cf8426 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -930,6 +930,7 @@ unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { return AGPR_32RegClassID; case OPW64: return AReg_64RegClassID; case OPW128: return AReg_128RegClassID; + case OPW256: return AReg_256RegClassID; case OPW512: return AReg_512RegClassID; case OPW1024: return AReg_1024RegClassID; } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 05c8ff53dd3e..125a2f22c0e5 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -418,7 +418,11 @@ SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo, // instructions use acc[0:1] modifier bits to distinguish. These bits are // encoded as a virtual 9th bit of the register for these operands. if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || - MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg)) + MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || + MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || + MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || + MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || + MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg)) Enc |= 512; return Enc; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index e4fe2e527c3e..79d661ffab0b 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10657,9 +10657,18 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 64: RC = &AMDGPU::AReg_64RegClass; break; + case 96: + RC = &AMDGPU::AReg_96RegClass; + break; case 128: RC = &AMDGPU::AReg_128RegClass; break; + case 160: + RC = &AMDGPU::AReg_160RegClass; + break; + case 256: + RC = &AMDGPU::AReg_256RegClass; + break; case 512: RC = &AMDGPU::AReg_512RegClass; break; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index d969fddde0e5..84c7ea4224ca 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1309,8 +1309,14 @@ SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) { return &AMDGPU::AGPR_32RegClass; case 64: return &AMDGPU::AReg_64RegClass; + case 96: + return &AMDGPU::AReg_96RegClass; case 128: return &AMDGPU::AReg_128RegClass; + case 160: + return &AMDGPU::AReg_160RegClass; + case 256: + return &AMDGPU::AReg_256RegClass; case 512: return &AMDGPU::AReg_512RegClass; case 1024: @@ -1362,13 +1368,16 @@ SIRegisterInfo::getPhysRegClass(MCRegister Reg) const { &AMDGPU::AReg_64RegClass, &AMDGPU::VReg_96RegClass, &AMDGPU::SReg_96RegClass, + &AMDGPU::AReg_96RegClass, &AMDGPU::VReg_128RegClass, &AMDGPU::SReg_128RegClass, &AMDGPU::AReg_128RegClass, &AMDGPU::VReg_160RegClass, &AMDGPU::SReg_160RegClass, + &AMDGPU::AReg_160RegClass, &AMDGPU::VReg_256RegClass, &AMDGPU::SReg_256RegClass, + &AMDGPU::AReg_256RegClass, &AMDGPU::VReg_512RegClass, &AMDGPU::SReg_512RegClass, &AMDGPU::AReg_512RegClass, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 32a4cd60f0ae..2f737eaa8912 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -519,14 +519,24 @@ def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, (add (sequence "AGPR%u", 0, 255))> { let AllocationPriority = 1; let Size = 32; + let Weight = 1; } // AGPR 64-bit registers def AGPR_64 : SIRegisterTuples.ret, AGPR_32, 255, 1, 2, "a">; +// AGPR 96-bit registers +def AGPR_96 : SIRegisterTuples.ret, AGPR_32, 255, 1, 3, "a">; + // AGPR 128-bit registers def AGPR_128 : SIRegisterTuples.ret, AGPR_32, 255, 1, 4, "a">; +// AGPR 160-bit registers +def AGPR_160 : SIRegisterTuples.ret, AGPR_32, 255, 1, 5, "a">; + +// AGPR 256-bit registers +def AGPR_256 : SIRegisterTuples.ret, AGPR_32, 255, 1, 8, "a">; + // AGPR 512-bit registers def AGPR_512 : SIRegisterTuples.ret, AGPR_32, 255, 1, 16, "a">; @@ -752,7 +762,10 @@ class ARegClass regTypes, dag regList> : def AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], (add AGPR_64)>; +def AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>; +def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; +def AReg_256 : ARegClass<8, [v8i32, v8f32], (add AGPR_256)>; def AReg_512 : ARegClass<16, [v16i32, v16f32], (add AGPR_512)>; def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>; diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 4f8d9e925df1..33d8aab00af8 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1104,6 +1104,7 @@ unsigned getRegBitWidth(unsigned RCID) { case AMDGPU::SGPR_96RegClassID: case AMDGPU::SReg_96RegClassID: case AMDGPU::VReg_96RegClassID: + case AMDGPU::AReg_96RegClassID: return 96; case AMDGPU::SGPR_128RegClassID: case AMDGPU::SReg_128RegClassID: @@ -1113,9 +1114,11 @@ unsigned getRegBitWidth(unsigned RCID) { case AMDGPU::SGPR_160RegClassID: case AMDGPU::SReg_160RegClassID: case AMDGPU::VReg_160RegClassID: + case AMDGPU::AReg_160RegClassID: return 160; case AMDGPU::SReg_256RegClassID: case AMDGPU::VReg_256RegClassID: + case AMDGPU::AReg_256RegClassID: return 256; case AMDGPU::SReg_512RegClassID: case AMDGPU::VReg_512RegClassID: -- GitLab From dbdffe3ee9d6fd4739bef5f03e61f052a95e72ca Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Thu, 16 Apr 2020 17:02:19 +0100 Subject: [PATCH 068/910] [AMDGPU] Add 192-bit register classes Differential Revision: https://reviews.llvm.org/D78312 --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 10 +++++ llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td | 6 +-- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 6 +++ .../AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 1 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 ++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 ++++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 35 +++++++++++---- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 4 ++ .../AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll | 9 ---- .../AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 34 ++++++++++++++ .../GlobalISel/inst-select-concat-vectors.mir | 24 +++++----- .../GlobalISel/inst-select-merge-values.mir | 29 +++++------- .../GlobalISel/inst-select-unmerge-values.mir | 15 +++---- .../AMDGPU/GlobalISel/zextload-xfail.ll | 9 ---- .../CodeGen/AMDGPU/GlobalISel/zextload.ll | 44 +++++++++++++++++++ llvm/test/CodeGen/AMDGPU/ipra-regmask.ll | 6 +-- 16 files changed, 178 insertions(+), 72 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index f1b3cd9b8d20..4e1a7842a1ee 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -824,6 +824,16 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage( IsSGPR = false; IsAGPR = true; Width = 5; + } else if (AMDGPU::VReg_192RegClass.contains(Reg)) { + IsSGPR = false; + Width = 6; + } else if (AMDGPU::SReg_192RegClass.contains(Reg)) { + IsSGPR = true; + Width = 6; + } else if (AMDGPU::AReg_192RegClass.contains(Reg)) { + IsSGPR = false; + IsAGPR = true; + Width = 6; } else if (AMDGPU::SReg_256RegClass.contains(Reg)) { assert(!AMDGPU::TTMP_256RegClass.contains(Reg) && "trap handler registers should not be used"); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td index df5b106bea09..dfb13767bfe2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td @@ -7,16 +7,16 @@ //===----------------------------------------------------------------------===// def SGPRRegBank : RegisterBank<"SGPR", - [SGPR_LO16, SReg_32, SReg_64, SReg_128, SReg_256, SReg_512, SReg_1024] + [SGPR_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024] >; def VGPRRegBank : RegisterBank<"VGPR", - [VGPR_LO16, VGPR_HI16, VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512, VReg_1024] + [VGPR_LO16, VGPR_HI16, VGPR_32, VReg_64, VReg_96, VReg_128, VReg_160, VReg_192, VReg_256, VReg_512, VReg_1024] >; // It is helpful to distinguish conditions from ordinary SGPRs. def VCCRegBank : RegisterBank <"VCC", [SReg_1]>; def AGPRRegBank : RegisterBank <"AGPR", - [AGPR_32, AReg_64, AReg_96, AReg_128, AReg_160, AReg_256, AReg_512, AReg_1024] + [AGPR_32, AReg_64, AReg_96, AReg_128, AReg_160, AReg_192, AReg_256, AReg_512, AReg_1024] >; diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 17ab79ac62c2..09fde4bc741a 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -278,6 +278,7 @@ public: isRegClass(AMDGPU::VReg_96RegClassID) || isRegClass(AMDGPU::VReg_128RegClassID) || isRegClass(AMDGPU::VReg_160RegClassID) || + isRegClass(AMDGPU::VReg_192RegClassID) || isRegClass(AMDGPU::VReg_256RegClassID) || isRegClass(AMDGPU::VReg_512RegClassID) || isRegClass(AMDGPU::VReg_1024RegClassID); @@ -1915,6 +1916,7 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) { case 3: return AMDGPU::VReg_96RegClassID; case 4: return AMDGPU::VReg_128RegClassID; case 5: return AMDGPU::VReg_160RegClassID; + case 6: return AMDGPU::VReg_192RegClassID; case 8: return AMDGPU::VReg_256RegClassID; case 16: return AMDGPU::VReg_512RegClassID; case 32: return AMDGPU::VReg_1024RegClassID; @@ -1933,7 +1935,10 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) { default: return -1; case 1: return AMDGPU::SGPR_32RegClassID; case 2: return AMDGPU::SGPR_64RegClassID; + case 3: return AMDGPU::SGPR_96RegClassID; case 4: return AMDGPU::SGPR_128RegClassID; + case 5: return AMDGPU::SGPR_160RegClassID; + case 6: return AMDGPU::SReg_192RegClassID; case 8: return AMDGPU::SGPR_256RegClassID; case 16: return AMDGPU::SGPR_512RegClassID; } @@ -1945,6 +1950,7 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) { case 3: return AMDGPU::AReg_96RegClassID; case 4: return AMDGPU::AReg_128RegClassID; case 5: return AMDGPU::AReg_160RegClassID; + case 6: return AMDGPU::AReg_192RegClassID; case 8: return AMDGPU::AReg_256RegClassID; case 16: return AMDGPU::AReg_512RegClassID; case 32: return AMDGPU::AReg_1024RegClassID; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 125a2f22c0e5..4461d2be13c8 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -422,6 +422,7 @@ SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo, MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || + MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg)) Enc |= 512; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 79d661ffab0b..b32dfb665d79 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10608,6 +10608,9 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 160: RC = &AMDGPU::SReg_160RegClass; break; + case 192: + RC = &AMDGPU::SReg_192RegClass; + break; case 256: RC = &AMDGPU::SReg_256RegClass; break; @@ -10636,6 +10639,9 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 160: RC = &AMDGPU::VReg_160RegClass; break; + case 192: + RC = &AMDGPU::VReg_192RegClass; + break; case 256: RC = &AMDGPU::VReg_256RegClass; break; @@ -10666,6 +10672,9 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 160: RC = &AMDGPU::AReg_160RegClass; break; + case 192: + RC = &AMDGPU::AReg_192RegClass; + break; case 256: RC = &AMDGPU::AReg_256RegClass; break; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 84c7ea4224ca..40252f43d033 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1291,6 +1291,8 @@ SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) { return &AMDGPU::VReg_128RegClass; case 160: return &AMDGPU::VReg_160RegClass; + case 192: + return &AMDGPU::VReg_192RegClass; case 256: return &AMDGPU::VReg_256RegClass; case 512: @@ -1315,6 +1317,8 @@ SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) { return &AMDGPU::AReg_128RegClass; case 160: return &AMDGPU::AReg_160RegClass; + case 192: + return &AMDGPU::AReg_192RegClass; case 256: return &AMDGPU::AReg_256RegClass; case 512: @@ -1341,6 +1345,8 @@ SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) { return &AMDGPU::SReg_128RegClass; case 160: return &AMDGPU::SReg_160RegClass; + case 192: + return &AMDGPU::SReg_192RegClass; case 256: return &AMDGPU::SReg_256RegClass; case 512: @@ -1375,6 +1381,9 @@ SIRegisterInfo::getPhysRegClass(MCRegister Reg) const { &AMDGPU::VReg_160RegClass, &AMDGPU::SReg_160RegClass, &AMDGPU::AReg_160RegClass, + &AMDGPU::VReg_192RegClass, + &AMDGPU::SReg_192RegClass, + &AMDGPU::AReg_192RegClass, &AMDGPU::VReg_256RegClass, &AMDGPU::SReg_256RegClass, &AMDGPU::AReg_256RegClass, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 2f737eaa8912..4f563d80432b 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -59,6 +59,7 @@ class getSubRegs { list ret3 = [sub0, sub1, sub2]; list ret4 = [sub0, sub1, sub2, sub3]; list ret5 = [sub0, sub1, sub2, sub3, sub4]; + list ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; list ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; list ret16 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, @@ -77,8 +78,10 @@ class getSubRegs { !if(!eq(size, 3), ret3, !if(!eq(size, 4), ret4, !if(!eq(size, 5), ret5, - !if(!eq(size, 8), ret8, - !if(!eq(size, 16), ret16, ret32)))))); + !if(!eq(size, 6), ret6, + !if(!eq(size, 8), ret8, + !if(!eq(size, 16), ret16, + ret32))))))); } // Generates list of sequential register tuple names. @@ -359,6 +362,9 @@ def SGPR_128Regs : SIRegisterTuples.ret, SGPR_32, 105, 4, 4, "s">; // SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. def SGPR_160Regs : SIRegisterTuples.ret, SGPR_32, 105, 4, 5, "s">; +// SGPR 192-bit registers +def SGPR_192Regs : SIRegisterTuples.ret, SGPR_32, 105, 4, 6, "s">; + // SGPR 256-bit registers def SGPR_256Regs : SIRegisterTuples.ret, SGPR_32, 105, 4, 8, "s">; @@ -505,6 +511,9 @@ def VGPR_128 : SIRegisterTuples.ret, VGPR_32, 255, 1, 4, "v">; // VGPR 160-bit registers def VGPR_160 : SIRegisterTuples.ret, VGPR_32, 255, 1, 5, "v">; +// VGPR 192-bit registers +def VGPR_192 : SIRegisterTuples.ret, VGPR_32, 255, 1, 6, "v">; + // VGPR 256-bit registers def VGPR_256 : SIRegisterTuples.ret, VGPR_32, 255, 1, 8, "v">; @@ -534,6 +543,9 @@ def AGPR_128 : SIRegisterTuples.ret, AGPR_32, 255, 1, 4, "a">; // AGPR 160-bit registers def AGPR_160 : SIRegisterTuples.ret, AGPR_32, 255, 1, 5, "a">; +// AGPR 192-bit registers +def AGPR_192 : SIRegisterTuples.ret, AGPR_32, 255, 1, 6, "a">; + // AGPR 256-bit registers def AGPR_256 : SIRegisterTuples.ret, AGPR_32, 255, 1, 8, "a">; @@ -686,10 +698,15 @@ def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, let AllocationPriority = 16; } -def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256Regs)> { +def SReg_192 : RegisterClass<"AMDGPU", [untyped], 32, (add SGPR_192Regs)> { + let Size = 192; let AllocationPriority = 17; } +def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256Regs)> { + let AllocationPriority = 18; +} + def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> { let isAllocatable = 0; } @@ -698,12 +715,12 @@ def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256, TTMP_256)> { // Requires 4 s_mov_b64 to copy let CopyCost = 4; - let AllocationPriority = 17; + let AllocationPriority = 18; } def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add SGPR_512Regs)> { - let AllocationPriority = 18; + let AllocationPriority = 19; } def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, @@ -715,7 +732,7 @@ def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add SGPR_512, TTMP_512)> { // Requires 8 s_mov_b64 to copy let CopyCost = 8; - let AllocationPriority = 18; + let AllocationPriority = 19; } def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, @@ -725,13 +742,13 @@ def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 3 def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, (add SGPR_1024Regs)> { - let AllocationPriority = 19; + let AllocationPriority = 20; } def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, (add SGPR_1024)> { let CopyCost = 16; - let AllocationPriority = 19; + let AllocationPriority = 20; } // Register class for all vector registers (VGPRs + Interploation Registers) @@ -750,6 +767,7 @@ def VReg_64 : VRegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], def VReg_96 : VRegClass<3, [v3i32, v3f32], (add VGPR_96)>; def VReg_128 : VRegClass<4, [v4i32, v4f32, v2i64, v2f64, i128], (add VGPR_128)>; def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>; +def VReg_192 : VRegClass<6, [untyped], (add VGPR_192)>; def VReg_256 : VRegClass<8, [v8i32, v8f32], (add VGPR_256)>; def VReg_512 : VRegClass<16, [v16i32, v16f32], (add VGPR_512)>; def VReg_1024 : VRegClass<32, [v32i32, v32f32], (add VGPR_1024)>; @@ -765,6 +783,7 @@ def AReg_64 : ARegClass<2, [i64, f64, v2i32, v2f32, v4f16, v4i16], def AReg_96 : ARegClass<3, [v3i32, v3f32], (add AGPR_96)>; def AReg_128 : ARegClass<4, [v4i32, v4f32, v2i64, v2f64], (add AGPR_128)>; def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>; +def AReg_192 : ARegClass<6, [untyped], (add AGPR_192)>; def AReg_256 : ARegClass<8, [v8i32, v8f32], (add AGPR_256)>; def AReg_512 : ARegClass<16, [v16i32, v16f32], (add AGPR_512)>; def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>; diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 33d8aab00af8..983870032efb 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1116,6 +1116,10 @@ unsigned getRegBitWidth(unsigned RCID) { case AMDGPU::VReg_160RegClassID: case AMDGPU::AReg_160RegClassID: return 160; + case AMDGPU::SReg_192RegClassID: + case AMDGPU::VReg_192RegClassID: + case AMDGPU::AReg_192RegClassID: + return 192; case AMDGPU::SReg_256RegClassID: case AMDGPU::VReg_256RegClassID: case AMDGPU::AReg_256RegClassID: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll deleted file mode 100644 index 95ddf2045648..000000000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: not --crash llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s -; RUN: not --crash llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s - -define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind { - %trunc = trunc i32 %arg0 to i24 - %val = bitcast i24 %trunc to <3 x i8> - %cvt = uitofp <3 x i8> %val to <3 x float> - ret <3 x float> %cvt -} \ No newline at end of file diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll index 4bfc7e3e6744..09e2d1ad0826 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll @@ -191,6 +191,40 @@ define <2 x float> @v_uitofp_v2i8_to_v2f32(i16 %arg0) nounwind { ret <2 x float> %cvt } +define <3 x float> @v_uitofp_v3i8_to_v3f32(i32 %arg0) nounwind { +; SI-LABEL: v_uitofp_v3i8_to_v3f32: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; SI-NEXT: s_movk_i32 s4, 0xff +; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v1 +; SI-NEXT: v_and_b32_e32 v0, s4, v0 +; SI-NEXT: v_and_b32_e32 v1, s4, v1 +; SI-NEXT: v_and_b32_e32 v2, s4, v2 +; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 +; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 +; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_uitofp_v3i8_to_v3f32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: s_movk_i32 s4, 0xff +; VI-NEXT: v_mov_b32_e32 v2, s4 +; VI-NEXT: v_and_b32_sdwa v1, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD +; VI-NEXT: v_cvt_f32_ubyte0_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 +; VI-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v0 +; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 +; VI-NEXT: v_mov_b32_e32 v0, v3 +; VI-NEXT: s_setpc_b64 s[30:31] + %trunc = trunc i32 %arg0 to i24 + %val = bitcast i24 %trunc to <3 x i8> + %cvt = uitofp <3 x i8> %val to <3 x float> + ret <3 x float> %cvt +} + define <4 x float> @v_uitofp_v4i8_to_v4f32(i32 %arg0) nounwind { ; SI-LABEL: v_uitofp_v4i8_to_v4f32: ; SI: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir index 35d4e8e647e7..938b7af5b972 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir @@ -3,9 +3,7 @@ # RUN: FileCheck -check-prefix=ERR %s < %t # ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %3:sgpr(<12 x s16>) = G_CONCAT_VECTORS %0:sgpr(<4 x s16>), %1:sgpr(<4 x s16>), %2:sgpr(<4 x s16>) (in function: test_concat_vectors_s_v12s16_s_v4s16_s_v4s16_s_v4s16) -# ERR-NEXT: remark: :0:0: cannot select: %3:vgpr(<12 x s16>) = G_CONCAT_VECTORS %0:vgpr(<4 x s16>), %1:vgpr(<4 x s16>), %2:vgpr(<4 x s16>) (in function: test_concat_vectors_v_v12s16_v_v4s16_v_v4s16_v_v4s16) -# ERR-NEXT: remark: :0:0: cannot select: %2:sgpr(<6 x s64>) = G_CONCAT_VECTORS %0:sgpr(<3 x s64>), %1:sgpr(<3 x s64>) (in function: test_concat_vectors_s_v6s64_s_v3s64_s_v3s64) +# ERR: remark: :0:0: cannot select: %2:sgpr(<6 x s64>) = G_CONCAT_VECTORS %0:sgpr(<3 x s64>), %1:sgpr(<3 x s64>) (in function: test_concat_vectors_s_v6s64_s_v3s64_s_v3s64) # ERR-NOT: remark: --- @@ -282,11 +280,11 @@ body: | liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN-LABEL: name: test_concat_vectors_s_v12s16_s_v4s16_s_v4s16_s_v4s16 - ; GCN: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3 - ; GCN: [[COPY2:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5 - ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:sgpr(<12 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>), [[COPY2]](<4 x s16>) - ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<12 x s16>) + ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 + ; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 + ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_192 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5 + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1 %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3 %2:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5 @@ -304,11 +302,11 @@ body: | liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 ; GCN-LABEL: name: test_concat_vectors_v_v12s16_v_v4s16_v_v4s16_v_v4s16 - ; GCN: [[COPY:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1 - ; GCN: [[COPY1:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3 - ; GCN: [[COPY2:%[0-9]+]]:vgpr(<4 x s16>) = COPY $vgpr4_vgpr5 - ; GCN: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<12 x s16>) = G_CONCAT_VECTORS [[COPY]](<4 x s16>), [[COPY1]](<4 x s16>), [[COPY2]](<4 x s16>) - ; GCN: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<12 x s16>) + ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 + ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 + ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_192 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5 + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] %0:vgpr(<4 x s16>) = COPY $vgpr0_vgpr1 %1:vgpr(<4 x s16>) = COPY $vgpr2_vgpr3 %2:vgpr(<4 x s16>) = COPY $vgpr4_vgpr5 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir index 207814ccd8c8..153b2860177e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir @@ -1,12 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %3:sgpr(s192) = G_MERGE_VALUES %0:sgpr(s64), %1:sgpr(s64), %2:sgpr(s64) (in function: test_merge_values_s_s192_s_s64_s_s64_s_s64) -# ERR-NEXT: remark: :0:0: cannot select: %3:vgpr(s192) = G_MERGE_VALUES %0:vgpr(s64), %1:vgpr(s64), %2:vgpr(s64) (in function: test_merge_values_v_s192_v_s64_v_s64_v_s64) -# ERR-NOT: remark: +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s | FileCheck -check-prefix=GCN %s --- name: test_merge_values_v_s64_v_s32_v_s32 @@ -346,11 +339,11 @@ body: | ; GCN-LABEL: name: test_merge_values_s_s192_s_s64_s_s64_s_s64 ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 - ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 - ; GCN: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 - ; GCN: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr4_sgpr5 - ; GCN: [[MV:%[0-9]+]]:sgpr(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64) - ; GCN: S_ENDPGM 0, implicit [[MV]](s192) + ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 + ; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 + ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_192 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5 + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] %0:sgpr(s64) = COPY $sgpr0_sgpr1 %1:sgpr(s64) = COPY $sgpr2_sgpr3 %2:sgpr(s64) = COPY $sgpr4_sgpr5 @@ -370,11 +363,11 @@ body: | ; GCN-LABEL: name: test_merge_values_v_s192_v_s64_v_s64_v_s64 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 - ; GCN: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GCN: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 - ; GCN: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr4_vgpr5 - ; GCN: [[MV:%[0-9]+]]:vgpr(s192) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64), [[COPY2]](s64) - ; GCN: S_ENDPGM 0, implicit [[MV]](s192) + ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 + ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3 + ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5 + ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_192 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3, [[COPY2]], %subreg.sub4_sub5 + ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] %0:vgpr(s64) = COPY $vgpr0_vgpr1 %1:vgpr(s64) = COPY $vgpr2_vgpr3 %2:vgpr(s64) = COPY $vgpr4_vgpr5 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir index f96dd5129e02..901e04a9c979 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir @@ -1,10 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s 2> %t | FileCheck -check-prefix=GCN %s -# RUN: FileCheck -check-prefix=ERR %s < %t - -# ERR-NOT: remark: -# ERR: remark: :0:0: cannot select: %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0:sgpr(s192) (in function: test_unmerge_values_s_s64_s_s64_s64_s_s192) -# ERR-NOT: remark: +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -o - %s | FileCheck -check-prefix=GCN %s --- name: test_unmerge_values_v_s32_v_s32_v_s64 @@ -185,9 +180,11 @@ body: | ; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s64_s_s192 ; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 - ; GCN: [[DEF:%[0-9]+]]:sgpr(s192) = G_IMPLICIT_DEF - ; GCN: [[UV:%[0-9]+]]:sgpr(s64), [[UV1:%[0-9]+]]:sgpr(s64), [[UV2:%[0-9]+]]:sgpr(s64) = G_UNMERGE_VALUES [[DEF]](s192) - ; GCN: S_ENDPGM 0, implicit [[UV]](s64), implicit [[UV1]](s64), implicit [[UV2]](s64) + ; GCN: [[DEF:%[0-9]+]]:sreg_192 = IMPLICIT_DEF + ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub0_sub1 + ; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub2_sub3 + ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[DEF]].sub4_sub5 + ; GCN: S_ENDPGM 0, implicit [[COPY]], implicit [[COPY1]], implicit [[COPY2]] %0:sgpr(s192) = G_IMPLICIT_DEF %1:sgpr(s64), %2:sgpr(s64), %3:sgpr(s64) = G_UNMERGE_VALUES %0 S_ENDPGM 0, implicit %1, implicit %2, implicit %3 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll deleted file mode 100644 index dc5f9e4a29f2..000000000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: not --crash llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s -; RUN: not --crash llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s -; RUN: not --crash llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s - -define i96 @zextload_global_i32_to_i96(i32 addrspace(1)* %ptr) { - %load = load i32, i32 addrspace(1)* %ptr - %ext = zext i32 %load to i96 - ret i96 %ext -} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll index df52912c7013..f853a87e97d8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll @@ -134,6 +134,50 @@ define i64 @zextload_global_i32_to_i64(i32 addrspace(1)* %ptr) { ret i64 %ext } +define i96 @zextload_global_i32_to_i96(i32 addrspace(1)* %ptr) { +; GFX9-LABEL: zextload_global_i32_to_i96: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: global_load_dword v0, v[2:3], off +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: zextload_global_i32_to_i96: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v3, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: flat_load_dword v0, v[2:3] +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: v_mov_b32_e32 v3, 0 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-LABEL: zextload_global_i32_to_i96: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_mov_b32_e32 v3, v1 +; GFX6-NEXT: v_mov_b32_e32 v2, v0 +; GFX6-NEXT: s_mov_b32 s6, 0 +; GFX6-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-NEXT: s_mov_b64 s[4:5], 0 +; GFX6-NEXT: buffer_load_dword v0, v[2:3], s[4:7], 0 addr64 +; GFX6-NEXT: v_mov_b32_e32 v2, 0 +; GFX6-NEXT: v_mov_b32_e32 v1, 0 +; GFX6-NEXT: v_mov_b32_e32 v3, 0 +; GFX6-NEXT: s_waitcnt vmcnt(0) +; GFX6-NEXT: s_setpc_b64 s[30:31] + %load = load i32, i32 addrspace(1)* %ptr + %ext = zext i32 %load to i96 + ret i96 %ext +} + define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) { ; GFX9-LABEL: zextload_global_i32_to_i128: ; GFX9: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll index f1132fc773d4..d4084e40fc8f 100644 --- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll @@ -1,19 +1,19 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; Make sure the expected regmask is generated for sub/superregisters. -; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr0_vgpr1 $vgpr0_vgpr1_vgpr2 {{$}} +; CHECK-DAG: csr Clobbered Registers: $vgpr0 $vgpr0_hi16 $vgpr0_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr0_vgpr1 $vgpr0_vgpr1_vgpr2 {{$}} define void @csr() #0 { call void asm sideeffect "", "~{v0},~{v36},~{v37}"() #0 ret void } -; CHECK-DAG: subregs_for_super Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}} +; CHECK-DAG: subregs_for_super Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}} define void @subregs_for_super() #0 { call void asm sideeffect "", "~{v0},~{v1}"() #0 ret void } -; CHECK-DAG: Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}} +; CHECK-DAG: clobbered_reg_with_sub Clobbered Registers: $vgpr0 $vgpr1 $vgpr0_hi16 $vgpr1_hi16 $vgpr0_lo16 $vgpr1_lo16 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 $vgpr0_vgpr1_vgpr2_vgpr3 $vgpr1_vgpr2_vgpr3_vgpr4 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 $vgpr0_vgpr1 $vgpr1_vgpr2 $vgpr0_vgpr1_vgpr2 $vgpr1_vgpr2_vgpr3 {{$}} define void @clobbered_reg_with_sub() #0 { call void asm sideeffect "", "~{v[0:1]}"() #0 ret void -- GitLab From 4d44ce7437816501154da4c3a8d68a854a3c23eb Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 22 Apr 2020 14:57:57 +0300 Subject: [PATCH 069/910] [NFC][InstCombine] Add shuffle negation tests --- .../InstCombine/sub-of-negatible.ll | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index 40cb4aa29446..21f695f40172 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -622,3 +622,56 @@ define i8 @negate_zext_wrongwidth(i8 %x, i2 %y) { %t1 = sub i8 %x, %t0 ret i8 %t1 } + +define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @negate_shufflevector_oneinput_reverse( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> +; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] +; CHECK-NEXT: ret <2 x i4> [[T2]] +; + %t0 = shl <2 x i4> , %x + %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> + %t2 = sub <2 x i4> %y, %t1 + ret <2 x i4> %t2 +} +define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @negate_shufflevector_oneinput_second_lane_is_undef( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> +; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] +; CHECK-NEXT: ret <2 x i4> [[T2]] +; + %t0 = shl <2 x i4> , %x + %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> + %t2 = sub <2 x i4> %y, %t1 + ret <2 x i4> %t2 +} +define <2 x i4> @negate_shufflevector_twoinputs(<2 x i4> %x, <2 x i4> %y, <2 x i4> %z) { +; CHECK-LABEL: @negate_shufflevector_twoinputs( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = xor <2 x i4> [[Y:%.*]], +; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> [[T1]], <2 x i32> +; CHECK-NEXT: [[T3:%.*]] = sub <2 x i4> [[Z:%.*]], [[T2]] +; CHECK-NEXT: ret <2 x i4> [[T3]] +; + %t0 = shl <2 x i4> , %x + %t1 = xor <2 x i4> %y, + %t2 = shufflevector <2 x i4> %t0, <2 x i4> %t1, <2 x i32> + %t3 = sub <2 x i4> %z, %t2 + ret <2 x i4> %t3 +} +define <2 x i4> @negate_shufflevector_oneinput_extrause(<2 x i4> %x, <2 x i4> %y) { +; CHECK-LABEL: @negate_shufflevector_oneinput_extrause( +; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> +; CHECK-NEXT: call void @use_v2i4(<2 x i4> [[T1]]) +; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] +; CHECK-NEXT: ret <2 x i4> [[T2]] +; + %t0 = shl <2 x i4> , %x + %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> + call void @use_v2i4(<2 x i4> %t1) + %t2 = sub <2 x i4> %y, %t1 + ret <2 x i4> %t2 +} -- GitLab From 67266d879c715cdcfb790acf0153da757dafd195 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 22 Apr 2020 14:58:39 +0300 Subject: [PATCH 070/910] [InstCombine] Negator: shufflevector is negatible All these folds are correct as per alive-tv --- .../InstCombine/InstCombineNegator.cpp | 16 +++++++++++++++ .../InstCombine/sub-of-negatible.ll | 20 +++++++++---------- 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp index 32f37c6d04cf..e119a383e9db 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp @@ -111,6 +111,10 @@ LLVM_NODISCARD Value *Negator::visit(Value *V, unsigned Depth) { ++NumValuesVisitedInThisNegator; #endif + // -(undef) -> undef. + if (match(V, m_Undef())) + return V; + // In i1, negation can simply be ignored. if (V->getType()->isIntOrIntVectorTy(1)) return V; @@ -265,6 +269,18 @@ LLVM_NODISCARD Value *Negator::visit(Value *V, unsigned Depth) { return Builder.CreateSelect(I->getOperand(0), NegOp1, NegOp2, I->getName() + ".neg", /*MDFrom=*/I); } + case Instruction::ShuffleVector: { + // `shufflevector` is negatible if both operands are negatible. + ShuffleVectorInst *Shuf = cast(I); + Value *NegOp0 = visit(I->getOperand(0), Depth + 1); + if (!NegOp0) // Early return. + return nullptr; + Value *NegOp1 = visit(I->getOperand(1), Depth + 1); + if (!NegOp1) + return nullptr; + return Builder.CreateShuffleVector(NegOp0, NegOp1, Shuf->getShuffleMask(), + I->getName() + ".neg"); + } case Instruction::Trunc: { // `trunc` is negatible if its operand is negatible. Value *NegOp = visit(I->getOperand(0), Depth + 1); diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index 21f695f40172..d676c0ba0936 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -625,9 +625,9 @@ define i8 @negate_zext_wrongwidth(i8 %x, i2 %y) { define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y) { ; CHECK-LABEL: @negate_shufflevector_oneinput_reverse( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> -; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] +; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> undef, <2 x i32> +; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]] ; CHECK-NEXT: ret <2 x i4> [[T2]] ; %t0 = shl <2 x i4> , %x @@ -637,9 +637,9 @@ define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y) } define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, <2 x i4> %y) { ; CHECK-LABEL: @negate_shufflevector_oneinput_second_lane_is_undef( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> -; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] +; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> undef, <2 x i32> +; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]] ; CHECK-NEXT: ret <2 x i4> [[T2]] ; %t0 = shl <2 x i4> , %x @@ -649,10 +649,10 @@ define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, } define <2 x i4> @negate_shufflevector_twoinputs(<2 x i4> %x, <2 x i4> %y, <2 x i4> %z) { ; CHECK-LABEL: @negate_shufflevector_twoinputs( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> , [[X:%.*]] -; CHECK-NEXT: [[T1:%.*]] = xor <2 x i4> [[Y:%.*]], -; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> [[T1]], <2 x i32> -; CHECK-NEXT: [[T3:%.*]] = sub <2 x i4> [[Z:%.*]], [[T2]] +; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> , [[X:%.*]] +; CHECK-NEXT: [[T1_NEG:%.*]] = add <2 x i4> [[Y:%.*]], +; CHECK-NEXT: [[T2_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> [[T1_NEG]], <2 x i32> +; CHECK-NEXT: [[T3:%.*]] = add <2 x i4> [[T2_NEG]], [[Z:%.*]] ; CHECK-NEXT: ret <2 x i4> [[T3]] ; %t0 = shl <2 x i4> , %x -- GitLab From 72f565899dd4bf1fcb183555ba9089b7452b3f8a Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski Date: Tue, 7 Apr 2020 11:09:01 +0100 Subject: [PATCH 071/910] [SveEmitter] Implement builtins for gathers/scatters This patch adds builtins for: * regular, first-faulting and non-temporal gather loads * regular and non-temporal scatter stores Differential Revision: https://reviews.llvm.org/D77735 --- clang/include/clang/Basic/TargetBuiltins.h | 1 + clang/include/clang/Basic/arm_sve.td | 281 ++++++++++++++ clang/lib/CodeGen/CGBuiltin.cpp | 163 +++++++- clang/lib/CodeGen/CodeGenFunction.h | 14 +- .../aarch64-sve-intrinsics/acle_sve_ld1.c | 343 +++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ld1sb.c | 144 ++++++++ .../aarch64-sve-intrinsics/acle_sve_ld1sh.c | 256 +++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ld1sw.c | 128 +++++++ .../aarch64-sve-intrinsics/acle_sve_ld1ub.c | 144 ++++++++ .../aarch64-sve-intrinsics/acle_sve_ld1uh.c | 256 +++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ld1uw.c | 128 +++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1.c | 342 +++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1sb.c | 144 ++++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1sh.c | 264 +++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1sw.c | 136 +++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1ub.c | 152 ++++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1uh.c | 264 +++++++++++++ .../aarch64-sve-intrinsics/acle_sve_ldff1uw.c | 136 +++++++ .../aarch64-sve2-intrinsics/acle_sve2_ldnt1.c | 349 ++++++++++++++++++ .../acle_sve2_ldnt1sb.c | 167 +++++++++ .../acle_sve2_ldnt1sh.c | 259 +++++++++++++ .../acle_sve2_ldnt1sw.c | 169 +++++++++ .../acle_sve2_ldnt1ub.c | 167 +++++++++ .../acle_sve2_ldnt1uh.c | 259 +++++++++++++ .../acle_sve2_ldnt1uw.c | 169 +++++++++ .../aarch64-sve2-intrinsics/acle_sve2_stnt1.c | 349 ++++++++++++++++++ .../acle_sve2_stnt1b.c | 167 +++++++++ .../acle_sve2_stnt1h.c | 259 +++++++++++++ .../acle_sve2_stnt1w.c | 169 +++++++++ clang/utils/TableGen/SveEmitter.cpp | 5 + 30 files changed, 5781 insertions(+), 3 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sb.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sh.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sw.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1ub.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uh.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uw.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c create mode 100644 clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 0821926a6881..0533b1291664 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -222,6 +222,7 @@ namespace clang { bool isStructLoad() const { return Flags & IsStructLoad; } bool isStructStore() const { return Flags & IsStructStore; } bool isZExtReturn() const { return Flags & IsZExtReturn; } + bool isByteIndexed() const { return Flags & IsByteIndexed; } uint64_t getBits() const { return Flags; } bool isFlagSet(uint64_t Flag) const { return Flags & Flag; } diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index cd01662b0858..88ea0d59b394 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -58,6 +58,7 @@ // ------------------- // prototype: return (arg, arg, ...) // +// x: vector of signed integers // u: vector of unsigned integers // d: default // c: const pointer type @@ -155,6 +156,9 @@ def IsScatterStore : FlagType<0x00010000>; def IsStructLoad : FlagType<0x00020000>; def IsStructStore : FlagType<0x00040000>; def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default +// : : +// : : +def IsByteIndexed : FlagType<0x02000000>; // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h class ImmCheckType { @@ -226,6 +230,84 @@ def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoad, def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32>; def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32>; +// Load one vector (vector base) +def SVLD1_GATHER_BASES_U : MInst<"svld1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SB_GATHER_BASES_U : MInst<"svld1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UB_GATHER_BASES_U : MInst<"svld1ub_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SH_GATHER_BASES_U : MInst<"svld1sh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UH_GATHER_BASES_U : MInst<"svld1uh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SW_GATHER_BASES_U : MInst<"svld1sw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UW_GATHER_BASES_U : MInst<"svld1uw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; + +// Load one vector (scalar base, signed vector offset in bytes) +def SVLD1_GATHER_64B_OFFSETS_S : MInst<"svld1_gather_[{3}]offset[_{d}]", "dPcx", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ld1_gather">; +def SVLD1SB_GATHER_64B_OFFSETS_S : MInst<"svld1sb_gather_[{3}]offset_{d}", "dPSx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ld1_gather">; +def SVLD1UB_GATHER_64B_OFFSETS_S : MInst<"svld1ub_gather_[{3}]offset_{d}", "dPWx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather">; +def SVLD1SH_GATHER_64B_OFFSETS_S : MInst<"svld1sh_gather_[{3}]offset_{d}", "dPTx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ld1_gather">; +def SVLD1UH_GATHER_64B_OFFSETS_S : MInst<"svld1uh_gather_[{3}]offset_{d}", "dPXx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather">; +def SVLD1SW_GATHER_64B_OFFSETS_S : MInst<"svld1sw_gather_[{3}]offset_{d}", "dPUx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ld1_gather">; +def SVLD1UW_GATHER_64B_OFFSETS_S : MInst<"svld1uw_gather_[{3}]offset_{d}", "dPYx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather">; + +def SVLD1_GATHER_32B_OFFSETS_S : MInst<"svld1_gather_[{3}]offset[_{d}]", "dPcx", "iUif", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ld1_gather_sxtw">; +def SVLD1SB_GATHER_32B_OFFSETS_S : MInst<"svld1sb_gather_[{3}]offset_{d}", "dPSx", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ld1_gather_sxtw">; +def SVLD1UB_GATHER_32B_OFFSETS_S : MInst<"svld1ub_gather_[{3}]offset_{d}", "dPWx", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_sxtw">; +def SVLD1SH_GATHER_32B_OFFSETS_S : MInst<"svld1sh_gather_[{3}]offset_{d}", "dPTx", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ld1_gather_sxtw">; +def SVLD1UH_GATHER_32B_OFFSETS_S : MInst<"svld1uh_gather_[{3}]offset_{d}", "dPXx", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_sxtw">; + +// Load one vector (scalar base, unsigned vector offset in bytes) +def SVLD1_GATHER_64B_OFFSETS_U : MInst<"svld1_gather_[{3}]offset[_{d}]", "dPcu", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ld1_gather">; +def SVLD1SB_GATHER_64B_OFFSETS_U : MInst<"svld1sb_gather_[{3}]offset_{d}", "dPSu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ld1_gather">; +def SVLD1UB_GATHER_64B_OFFSETS_U : MInst<"svld1ub_gather_[{3}]offset_{d}", "dPWu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather">; +def SVLD1SH_GATHER_64B_OFFSETS_U : MInst<"svld1sh_gather_[{3}]offset_{d}", "dPTu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ld1_gather">; +def SVLD1UH_GATHER_64B_OFFSETS_U : MInst<"svld1uh_gather_[{3}]offset_{d}", "dPXu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather">; +def SVLD1SW_GATHER_64B_OFFSETS_U : MInst<"svld1sw_gather_[{3}]offset_{d}", "dPUu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ld1_gather">; +def SVLD1UW_GATHER_64B_OFFSETS_U : MInst<"svld1uw_gather_[{3}]offset_{d}", "dPYu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather">; + +def SVLD1_GATHER_32B_OFFSETS_U : MInst<"svld1_gather_[{3}]offset[_{d}]", "dPcu", "iUif", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ld1_gather_uxtw">; +def SVLD1SB_GATHER_32B_OFFSETS_U : MInst<"svld1sb_gather_[{3}]offset_{d}", "dPSu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ld1_gather_uxtw">; +def SVLD1UB_GATHER_32B_OFFSETS_U : MInst<"svld1ub_gather_[{3}]offset_{d}", "dPWu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_uxtw">; +def SVLD1SH_GATHER_32B_OFFSETS_U : MInst<"svld1sh_gather_[{3}]offset_{d}", "dPTu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ld1_gather_uxtw">; +def SVLD1UH_GATHER_32B_OFFSETS_U : MInst<"svld1uh_gather_[{3}]offset_{d}", "dPXu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_uxtw">; + +// Load one vector (vector base, signed scalar offset in bytes) +def SVLD1_GATHER_OFFSET_S : MInst<"svld1_gather[_{2}base]_offset_{d}", "dPul", "ilUiUlfd", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SB_GATHER_OFFSET_S : MInst<"svld1sb_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UB_GATHER_OFFSET_S : MInst<"svld1ub_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SH_GATHER_OFFSET_S : MInst<"svld1sh_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UH_GATHER_OFFSET_S : MInst<"svld1uh_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SW_GATHER_OFFSET_S : MInst<"svld1sw_gather[_{2}base]_offset_{d}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UW_GATHER_OFFSET_S : MInst<"svld1uw_gather[_{2}base]_offset_{d}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; + +// Load one vector (scalar base, signed vector index) +def SVLD1_GATHER_64B_INDICES_S : MInst<"svld1_gather_[{3}]index[_{d}]", "dPcx", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_index">; +def SVLD1SH_GATHER_64B_INDICES_S : MInst<"svld1sh_gather_[{3}]index_{d}", "dPTx", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_index">; +def SVLD1UH_GATHER_64B_INDICES_S : MInst<"svld1uh_gather_[{3}]index_{d}", "dPXx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_index">; +def SVLD1SW_GATHER_64B_INDICES_S : MInst<"svld1sw_gather_[{3}]index_{d}", "dPUx", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_index">; +def SVLD1UW_GATHER_64B_INDICES_S : MInst<"svld1uw_gather_[{3}]index_{d}", "dPYx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather_index">; + +def SVLD1_GATHER_32B_INDICES_S : MInst<"svld1_gather_[{3}]index[_{d}]", "dPcx", "iUif", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_sxtw_index">; +def SVLD1SH_GATHER_32B_INDICES_S : MInst<"svld1sh_gather_[{3}]index_{d}", "dPTx", "iUi", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_sxtw_index">; +def SVLD1UH_GATHER_32B_INDICES_S : MInst<"svld1uh_gather_[{3}]index_{d}", "dPXx", "iUi", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_sxtw_index">; + +// Load one vector (scalar base, unsigned vector index) +def SVLD1_GATHER_64B_INDICES_U : MInst<"svld1_gather_[{3}]index[_{d}]", "dPcu", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_index">; +def SVLD1SH_GATHER_64B_INDICES_U : MInst<"svld1sh_gather_[{3}]index_{d}", "dPTu", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_index">; +def SVLD1UH_GATHER_64B_INDICES_U : MInst<"svld1uh_gather_[{3}]index_{d}", "dPXu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_index">; +def SVLD1SW_GATHER_64B_INDICES_U : MInst<"svld1sw_gather_[{3}]index_{d}", "dPUu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_index">; +def SVLD1UW_GATHER_64B_INDICES_U : MInst<"svld1uw_gather_[{3}]index_{d}", "dPYu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather_index">; + +def SVLD1_GATHER_32B_INDICES_U : MInst<"svld1_gather_[{3}]index[_{d}]", "dPcu", "iUif", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_uxtw_index">; +def SVLD1SH_GATHER_32B_INDICES_U : MInst<"svld1sh_gather_[{3}]index_{d}", "dPTu", "iUi", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_uxtw_index">; +def SVLD1UH_GATHER_32B_INDICES_U : MInst<"svld1uh_gather_[{3}]index_{d}", "dPXu", "iUi", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_uxtw_index">; + +// Load one vector (vector base, signed scalar index) +def SVLD1_GATHER_INDEX_S : MInst<"svld1_gather[_{2}base]_index_{d}", "dPul", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SH_GATHER_INDEX_S : MInst<"svld1sh_gather[_{2}base]_index_{d}", "dPul", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UH_GATHER_INDEX_S : MInst<"svld1uh_gather[_{2}base]_index_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1SW_GATHER_INDEX_S : MInst<"svld1sw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; +def SVLD1UW_GATHER_INDEX_S : MInst<"svld1uw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; + + // First-faulting load one vector (scalar base) def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; def SVLDFF1SB : MInst<"svldff1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldff1">; @@ -244,6 +326,83 @@ def SVLDFF1UH_VNUM : MInst<"svldff1uh_vnum_{d}", "dPXl", "ilUiUl", [IsL def SVLDFF1SW_VNUM : MInst<"svldff1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32, "aarch64_sve_ldff1">; def SVLDFF1UW_VNUM : MInst<"svldff1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1">; +// First-faulting load one vector (vector base) +def SVLDFF1_GATHER_BASES_U : MInst<"svldff1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SB_GATHER_BASES_U : MInst<"svldff1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UB_GATHER_BASES_U : MInst<"svldff1ub_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SH_GATHER_BASES_U : MInst<"svldff1sh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UH_GATHER_BASES_U : MInst<"svldff1uh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SW_GATHER_BASES_U : MInst<"svldff1sw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UW_GATHER_BASES_U : MInst<"svldff1uw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; + +// First-faulting load one vector (scalar base, signed vector offset in bytes) +def SVLDFF1_GATHER_64B_OFFSETS_S : MInst<"svldff1_gather_[{3}]offset[_{d}]", "dPcx", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldff1_gather">; +def SVLDFF1SB_GATHER_64B_OFFSETS_S : MInst<"svldff1sb_gather_[{3}]offset_{d}", "dPSx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldff1_gather">; +def SVLDFF1UB_GATHER_64B_OFFSETS_S : MInst<"svldff1ub_gather_[{3}]offset_{d}", "dPWx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather">; +def SVLDFF1SH_GATHER_64B_OFFSETS_S : MInst<"svldff1sh_gather_[{3}]offset_{d}", "dPTx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldff1_gather">; +def SVLDFF1UH_GATHER_64B_OFFSETS_S : MInst<"svldff1uh_gather_[{3}]offset_{d}", "dPXx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather">; +def SVLDFF1SW_GATHER_64B_OFFSETS_S : MInst<"svldff1sw_gather_[{3}]offset_{d}", "dPUx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldff1_gather">; +def SVLDFF1UW_GATHER_64B_OFFSETS_S : MInst<"svldff1uw_gather_[{3}]offset_{d}", "dPYx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather">; + +def SVLDFF1_GATHER_32B_OFFSETS_S : MInst<"svldff1_gather_[{3}]offset[_{d}]", "dPcx", "iUif", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldff1_gather_sxtw">; +def SVLDFF1SB_GATHER_32B_OFFSETS_S : MInst<"svldff1sb_gather_[{3}]offset_{d}", "dPSx", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldff1_gather_sxtw">; +def SVLDFF1UB_GATHER_32B_OFFSETS_S : MInst<"svldff1ub_gather_[{3}]offset_{d}", "dPWx", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather_sxtw">; +def SVLDFF1SH_GATHER_32B_OFFSETS_S : MInst<"svldff1sh_gather_[{3}]offset_{d}", "dPTx", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldff1_gather_sxtw">; +def SVLDFF1UH_GATHER_32B_OFFSETS_S : MInst<"svldff1uh_gather_[{3}]offset_{d}", "dPXx", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_sxtw">; + +// First-faulting load one vector (scalar base, unsigned vector offset in bytes) +def SVLDFF1_GATHER_64B_OFFSETS_U : MInst<"svldff1_gather_[{3}]offset[_{d}]", "dPcu", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldff1_gather">; +def SVLDFF1SB_GATHER_64B_OFFSETS_U : MInst<"svldff1sb_gather_[{3}]offset_{d}", "dPSu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldff1_gather">; +def SVLDFF1UB_GATHER_64B_OFFSETS_U : MInst<"svldff1ub_gather_[{3}]offset_{d}", "dPWu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather">; +def SVLDFF1SH_GATHER_64B_OFFSETS_U : MInst<"svldff1sh_gather_[{3}]offset_{d}", "dPTu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldff1_gather">; +def SVLDFF1UH_GATHER_64B_OFFSETS_U : MInst<"svldff1uh_gather_[{3}]offset_{d}", "dPXu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather">; +def SVLDFF1SW_GATHER_64B_OFFSETS_U : MInst<"svldff1sw_gather_[{3}]offset_{d}", "dPUu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldff1_gather">; +def SVLDFF1UW_GATHER_64B_OFFSETS_U : MInst<"svldff1uw_gather_[{3}]offset_{d}", "dPYu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather">; + +def SVLDFF1_GATHER_32B_OFFSETS_U : MInst<"svldff1_gather_[{3}]offset[_{d}]", "dPcu", "iUif", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldff1_gather_uxtw">; +def SVLDFF1SB_GATHER_32B_OFFSETS_U : MInst<"svldff1sb_gather_[{3}]offset_{d}", "dPSu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldff1_gather_uxtw">; +def SVLDFF1UB_GATHER_32B_OFFSETS_U : MInst<"svldff1ub_gather_[{3}]offset_{d}", "dPWu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather_uxtw">; +def SVLDFF1SH_GATHER_32B_OFFSETS_U : MInst<"svldff1sh_gather_[{3}]offset_{d}", "dPTu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldff1_gather_uxtw">; +def SVLDFF1UH_GATHER_32B_OFFSETS_U : MInst<"svldff1uh_gather_[{3}]offset_{d}", "dPXu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_uxtw">; + +// First-faulting load one vector (vector base, signed scalar offset in bytes) +def SVLDFF1_GATHER_OFFSET_S : MInst<"svldff1_gather[_{2}base]_offset_{d}", "dPul", "ilUiUlfd", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SB_GATHER_OFFSET_S : MInst<"svldff1sb_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UB_GATHER_OFFSET_S : MInst<"svldff1ub_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SH_GATHER_OFFSET_S : MInst<"svldff1sh_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UH_GATHER_OFFSET_S : MInst<"svldff1uh_gather[_{2}base]_offset_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SW_GATHER_OFFSET_S : MInst<"svldff1sw_gather[_{2}base]_offset_{d}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UW_GATHER_OFFSET_S : MInst<"svldff1uw_gather[_{2}base]_offset_{d}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; + +// First-faulting load one vector (scalar base, signed vector index) +def SVLDFF1_GATHER_64B_INDICES_S : MInst<"svldff1_gather_[{3}]index[_{d}]", "dPcx", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1SH_GATHER_64B_INDICES_S : MInst<"svldff1sh_gather_[{3}]index_{d}", "dPTx", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1UH_GATHER_64B_INDICES_S : MInst<"svldff1uh_gather_[{3}]index_{d}", "dPXx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1SW_GATHER_64B_INDICES_S : MInst<"svldff1sw_gather_[{3}]index_{d}", "dPUx", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1UW_GATHER_64B_INDICES_S : MInst<"svldff1uw_gather_[{3}]index_{d}", "dPYx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_index">; + +def SVLDFF1_GATHER_32B_INDICES_S : MInst<"svldff1_gather_[{3}]index[_{d}]", "dPcx", "iUif", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_sxtw_index">; +def SVLDFF1SH_GATHER_32B_INDICES_S : MInst<"svldff1sh_gather_[{3}]index_{d}", "dPTx", "iUi", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_sxtw_index">; +def SVLDFF1UH_GATHER_32B_INDICES_S : MInst<"svldff1uh_gather_[{3}]index_{d}", "dPXx", "iUi", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_sxtw_index">; + +// First-faulting load one vector (scalar base, unsigned vector index) +def SVLDFF1_GATHER_64B_INDICES_U : MInst<"svldff1_gather_[{3}]index[_{d}]", "dPcu", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1SH_GATHER_64B_INDICES_U : MInst<"svldff1sh_gather_[{3}]index_{d}", "dPTu", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1UH_GATHER_64B_INDICES_U : MInst<"svldff1uh_gather_[{3}]index_{d}", "dPXu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1SW_GATHER_64B_INDICES_U : MInst<"svldff1sw_gather_[{3}]index_{d}", "dPUu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldff1_gather_index">; +def SVLDFF1UW_GATHER_64B_INDICES_U : MInst<"svldff1uw_gather_[{3}]index_{d}", "dPYu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_index">; + +def SVLDFF1_GATHER_32B_INDICES_U : MInst<"svldff1_gather_[{3}]index[_{d}]", "dPcu", "iUif", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_uxtw_index">; +def SVLDFF1SH_GATHER_32B_INDICES_U : MInst<"svldff1sh_gather_[{3}]index_{d}", "dPTu", "iUi", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_uxtw_index">; +def SVLDFF1UH_GATHER_32B_INDICES_U : MInst<"svldff1uh_gather_[{3}]index_{d}", "dPXu", "iUi", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_uxtw_index">; + +// First-faulting load one vector (vector base, signed scalar index) +def SVLDFF1_GATHER_INDEX_S : MInst<"svldff1_gather[_{2}base]_index_{d}", "dPul", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SH_GATHER_INDEX_S : MInst<"svldff1sh_gather[_{2}base]_index_{d}", "dPul", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UH_GATHER_INDEX_S : MInst<"svldff1uh_gather[_{2}base]_index_{d}", "dPul", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1SW_GATHER_INDEX_S : MInst<"svldff1sw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; +def SVLDFF1UW_GATHER_INDEX_S : MInst<"svldff1uw_gather[_{2}base]_index_{d}", "dPul", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldff1_gather_scalar_offset">; + // Non-faulting load one vector (scalar base) def SVLDNF1 : MInst<"svldnf1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnf1">; def SVLDNF1SB : MInst<"svldnf1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ldnf1">; @@ -376,3 +535,125 @@ def SVQDECH_U : SInst<"svqdech_pat[_{d}]", "ddIi", "Us", MergeNone, "aarch64_s // Integer arithmetic def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; def SVDOT_LANE_U : SInst<"svdot_lane[_{d}]", "ddqqi", "UiUl", MergeNone, "aarch64_sve_udot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; + +//////////////////////////////////////////////////////////////////////////////// +// SVE2 - Non-temporal gather/scatter +let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in { +// Non-temporal gather load one vector (vector base) +def SVLDNT1_GATHER_BASES_U : MInst<"svldnt1_gather[_{2}base]_{0}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SB_GATHER_BASES_U : MInst<"svldnt1sb_gather[_{2}base]_{0}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UB_GATHER_BASES_U : MInst<"svldnt1ub_gather[_{2}base]_{0}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SH_GATHER_BASES_U : MInst<"svldnt1sh_gather[_{2}base]_{0}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UH_GATHER_BASES_U : MInst<"svldnt1uh_gather[_{2}base]_{0}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SW_GATHER_BASES_U : MInst<"svldnt1sw_gather[_{2}base]_{0}", "dPu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UW_GATHER_BASES_U : MInst<"svldnt1uw_gather[_{2}base]_{0}", "dPu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; + +// Non-temporal gather load one vector (scalar base, signed vector offset in bytes) +def SVLDNT1_GATHER_64B_OFFSETS_S : MInst<"svldnt1_gather_[{3}]offset[_{0}]", "dPcx", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SB_GATHER_64B_OFFSETS_S : MInst<"svldnt1sb_gather_[{3}]offset_{0}", "dPSx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UB_GATHER_64B_OFFSETS_S : MInst<"svldnt1ub_gather_[{3}]offset_{0}", "dPWx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SH_GATHER_64B_OFFSETS_S : MInst<"svldnt1sh_gather_[{3}]offset_{0}", "dPTx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UH_GATHER_64B_OFFSETS_S : MInst<"svldnt1uh_gather_[{3}]offset_{0}", "dPXx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SW_GATHER_64B_OFFSETS_S : MInst<"svldnt1sw_gather_[{3}]offset_{0}", "dPUx", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UW_GATHER_64B_OFFSETS_S : MInst<"svldnt1uw_gather_[{3}]offset_{0}", "dPYx", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather">; + +// Non-temporal gather load one vector (scalar base, unsigned vector offset in bytes) +def SVLDNT1_GATHER_64B_OFFSETS_U : MInst<"svldnt1_gather_[{3}]offset[_{0}]", "dPcu", "lUld", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SB_GATHER_64B_OFFSETS_U : MInst<"svldnt1sb_gather_[{3}]offset_{0}", "dPSu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UB_GATHER_64B_OFFSETS_U : MInst<"svldnt1ub_gather_[{3}]offset_{0}", "dPWu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SH_GATHER_64B_OFFSETS_U : MInst<"svldnt1sh_gather_[{3}]offset_{0}", "dPTu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UH_GATHER_64B_OFFSETS_U : MInst<"svldnt1uh_gather_[{3}]offset_{0}", "dPXu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather">; +def SVLDNT1SW_GATHER_64B_OFFSETS_U : MInst<"svldnt1sw_gather_[{3}]offset_{0}", "dPUu", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldnt1_gather">; +def SVLDNT1UW_GATHER_64B_OFFSETS_U : MInst<"svldnt1uw_gather_[{3}]offset_{0}", "dPYu", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather">; + +def SVLDNT1_GATHER_32B_OFFSETS_U : MInst<"svldnt1_gather_[{3}]offset[_{0}]", "dPcu", "iUif", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldnt1_gather_uxtw">; +def SVLDNT1SB_GATHER_32B_OFFSETS_U : MInst<"svldnt1sb_gather_[{3}]offset_{0}", "dPSu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldnt1_gather_uxtw">; +def SVLDNT1UB_GATHER_32B_OFFSETS_U : MInst<"svldnt1ub_gather_[{3}]offset_{0}", "dPWu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnt1_gather_uxtw">; +def SVLDNT1SH_GATHER_32B_OFFSETS_U : MInst<"svldnt1sh_gather_[{3}]offset_{0}", "dPTu", "iUi", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldnt1_gather_uxtw">; +def SVLDNT1UH_GATHER_32B_OFFSETS_U : MInst<"svldnt1uh_gather_[{3}]offset_{0}", "dPXu", "iUi", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_uxtw">; + +// Non-temporal gather load one vector (vector base, scalar offset in bytes) +def SVLDNT1_GATHER_OFFSET_S : MInst<"svldnt1_gather[_{2}base]_offset_{0}", "dPul", "ilUiUlfd", [IsGatherLoad, IsByteIndexed], MemEltTyDefault, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SB_GATHER_OFFSET_S : MInst<"svldnt1sb_gather[_{2}base]_offset_{0}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt8, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UB_GATHER_OFFSET_S : MInst<"svldnt1ub_gather[_{2}base]_offset_{0}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SH_GATHER_OFFSET_S : MInst<"svldnt1sh_gather[_{2}base]_offset_{0}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UH_GATHER_OFFSET_S : MInst<"svldnt1uh_gather[_{2}base]_offset_{0}", "dPul", "ilUiUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SW_GATHER_OFFSET_S : MInst<"svldnt1sw_gather[_{2}base]_offset_{0}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UW_GATHER_OFFSET_S : MInst<"svldnt1uw_gather[_{2}base]_offset_{0}", "dPul", "lUl", [IsGatherLoad, IsByteIndexed, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; + +// Non-temporal gather load one vector (scalar base, signed vector index) +def SVLDNT1_GATHER_64B_INDICES_S : MInst<"svldnt1_gather_[{3}]index[_{0}]", "dPcx", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1SH_GATHER_64B_INDICES_S : MInst<"svldnt1sh_gather_[{3}]index_{0}", "dPTx", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1UH_GATHER_64B_INDICES_S : MInst<"svldnt1uh_gather_[{3}]index_{0}", "dPXx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1SW_GATHER_64B_INDICES_S : MInst<"svldnt1sw_gather_[{3}]index_{0}", "dPUx", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1UW_GATHER_64B_INDICES_S : MInst<"svldnt1uw_gather_[{3}]index_{0}", "dPYx", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather_index">; + +// Non temporal gather load one vector (scalar base, unsigned vector index) +def SVLDNT1_GATHER_64B_INDICES_U : MInst<"svldnt1_gather_[{3}]index[_{0}]", "dPcu", "lUld", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1SH_GATHER_64B_INDICES_U : MInst<"svldnt1sh_gather_[{3}]index_{0}", "dPTu", "lUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1UH_GATHER_64B_INDICES_U : MInst<"svldnt1uh_gather_[{3}]index_{0}", "dPXu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1SW_GATHER_64B_INDICES_U : MInst<"svldnt1sw_gather_[{3}]index_{0}", "dPUu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldnt1_gather_index">; +def SVLDNT1UW_GATHER_64B_INDICES_U : MInst<"svldnt1uw_gather_[{3}]index_{0}", "dPYu", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather_index">; + +// Non-temporal gather load one vector (vector base, signed scalar index) +def SVLDNT1_GATHER_INDEX_S : MInst<"svldnt1_gather[_{2}base]_index_{0}", "dPul", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SH_GATHER_INDEX_S : MInst<"svldnt1sh_gather[_{2}base]_index_{0}", "dPul", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UH_GATHER_INDEX_S : MInst<"svldnt1uh_gather[_{2}base]_index_{0}", "dPul", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1SW_GATHER_INDEX_S : MInst<"svldnt1sw_gather[_{2}base]_index_{0}", "dPul", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; +def SVLDNT1UW_GATHER_INDEX_S : MInst<"svldnt1uw_gather[_{2}base]_index_{0}", "dPul", "lUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ldnt1_gather_scalar_offset">; + +// Non-temporal scatter store one vector (vector base) +def SVSTNT1_SCATTER_BASES_U : MInst<"svstnt1_scatter[_{2}base_{d}]", "vPud", "ilUiUlfd", [IsScatterStore], MemEltTyDefault, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1B_SCATTER_BASES_U : MInst<"svstnt1b_scatter[_{2}base_{d}]", "vPud", "ilUiUl", [IsScatterStore], MemEltTyInt8, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1H_SCATTER_BASES_U : MInst<"svstnt1h_scatter[_{2}base_{d}]", "vPud", "ilUiUl", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1W_SCATTER_BASES_U : MInst<"svstnt1w_scatter[_{2}base_{d}]", "vPud", "lUl", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_scalar_offset">; + +// Non-temporal scatter store one vector (scalar base, signed vector offset in bytes) +def SVSTNT1_SCATTER_64B_OFFSETS_S : MInst<"svstnt1_scatter_[{3}]offset[_{d}]", "vPpxd", "lUld", [IsScatterStore, IsByteIndexed], MemEltTyDefault, "aarch64_sve_stnt1_scatter">; +def SVSTNT1B_SCATTER_64B_OFFSETS_SS : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPAxd", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter">; +def SVSTNT1B_SCATTER_64B_OFFSETS_SU : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPExd", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter">; +def SVSTNT1H_SCATTER_64B_OFFSETS_SS : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPBxd", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter">; +def SVSTNT1H_SCATTER_64B_OFFSETS_SU : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPFxd", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter">; +def SVSTNT1W_SCATTER_64B_OFFSETS_SS : MInst<"svstnt1w_scatter_[{3}]offset[_{d}]", "vPCxd", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt32, "aarch64_sve_stnt1_scatter">; +def SVSTNT1W_SCATTER_64B_OFFSETS_SU : MInst<"svstnt1w_scatter_[{3}]offset[_{d}]", "vPGxd", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt32, "aarch64_sve_stnt1_scatter">; + +// Non-temporal scatter store one vector (scalar base, unsigned vector offset in bytes) +def SVSTNT1_SCATTER_64B_OFFSETS_U : MInst<"svstnt1_scatter_[{3}]offset[_{d}]", "vPpud", "lUld", [IsScatterStore, IsByteIndexed], MemEltTyDefault, "aarch64_sve_stnt1_scatter">; +def SVSTNT1B_SCATTER_64B_OFFSETS_US : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPAud", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter">; +def SVSTNT1B_SCATTER_64B_OFFSETS_UU : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPEud", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter">; +def SVSTNT1H_SCATTER_64B_OFFSETS_US : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPBud", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter">; +def SVSTNT1H_SCATTER_64B_OFFSETS_UU : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPFud", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter">; +def SVSTNT1W_SCATTER_64B_OFFSETS_US : MInst<"svstnt1w_scatter_[{3}]offset[_{d}]", "vPCud", "l", [IsScatterStore, IsByteIndexed], MemEltTyInt32, "aarch64_sve_stnt1_scatter">; +def SVSTNT1W_SCATTER_64B_OFFSETS_UU : MInst<"svstnt1w_scatter_[{3}]offset[_{d}]", "vPGud", "Ul", [IsScatterStore, IsByteIndexed], MemEltTyInt32, "aarch64_sve_stnt1_scatter">; + +def SVSTNT1_SCATTER_32B_OFFSETS_U : MInst<"svstnt1_scatter_[{3}]offset[_{d}]", "vPpud", "iUif", [IsScatterStore, IsByteIndexed], MemEltTyDefault, "aarch64_sve_stnt1_scatter_uxtw">; +def SVSTNT1B_SCATTER_32B_OFFSETS_US : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPAud", "i", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter_uxtw">; +def SVSTNT1B_SCATTER_32B_OFFSETS_UU : MInst<"svstnt1b_scatter_[{3}]offset[_{d}]", "vPEud", "Ui", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter_uxtw">; +def SVSTNT1H_SCATTER_32B_OFFSETS_US : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPBud", "i", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter_uxtw">; +def SVSTNT1H_SCATTER_32B_OFFSETS_UU : MInst<"svstnt1h_scatter_[{3}]offset[_{d}]", "vPFud", "Ui", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter_uxtw">; + +// Non-temporal scatter store one vector (vector base, scalar offset in bytes) +def SVSTNT1_SCATTER_OFFSET_S : MInst<"svstnt1_scatter[_{2}base]_offset[_{d}]", "vPuld", "ilUiUlfd", [IsScatterStore, IsByteIndexed], MemEltTyDefault, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1B_SCATTER_OFFSET_S : MInst<"svstnt1b_scatter[_{2}base]_offset[_{d}]", "vPuld", "ilUiUl", [IsScatterStore, IsByteIndexed], MemEltTyInt8, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1H_SCATTER_OFFSET_S : MInst<"svstnt1h_scatter[_{2}base]_offset[_{d}]", "vPuld", "ilUiUl", [IsScatterStore, IsByteIndexed], MemEltTyInt16, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1W_SCATTER_OFFSET_S : MInst<"svstnt1w_scatter[_{2}base]_offset[_{d}]", "vPuld", "lUl", [IsScatterStore, IsByteIndexed], MemEltTyInt32, "aarch64_sve_stnt1_scatter_scalar_offset">; + +// Non-temporal scatter store one vector (scalar base, signed vector index) +def SVSTNT1_SCATTER_INDICES_S : MInst<"svstnt1_scatter_[{3}]index[_{d}]", "vPpxd", "lUld", [IsScatterStore], MemEltTyDefault, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1H_SCATTER_INDICES_SS : MInst<"svstnt1h_scatter_[{3}]index[_{d}]", "vPBxd", "l", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1H_SCATTER_INDICES_SU : MInst<"svstnt1h_scatter_[{3}]index[_{d}]", "vPFxd", "Ul", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1W_SCATTER_INDICES_SS : MInst<"svstnt1w_scatter_[{3}]index[_{d}]", "vPCxd", "l", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1W_SCATTER_INDICES_SU : MInst<"svstnt1w_scatter_[{3}]index[_{d}]", "vPGxd", "Ul", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_index">; + +// Non-temporal scatter store one vector (scalar base, unsigned vector index) +def SVSTNT1_SCATTER_INDICES_U : MInst<"svstnt1_scatter_[{3}]index[_{d}]", "vPpud", "lUld", [IsScatterStore], MemEltTyDefault, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1H_SCATTER_INDICES_US : MInst<"svstnt1h_scatter_[{3}]index[_{d}]", "vPBud", "l", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1H_SCATTER_INDICES_UU : MInst<"svstnt1h_scatter_[{3}]index[_{d}]", "vPFud", "Ul", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1W_SCATTER_INDICES_US : MInst<"svstnt1w_scatter_[{3}]index[_{d}]", "vPCud", "l", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_index">; +def SVSTNT1W_SCATTER_INDICES_UU : MInst<"svstnt1w_scatter_[{3}]index[_{d}]", "vPGud", "Ul", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_index">; + +// Non-temporal scatter store one vector (vector base, signed scalar index) +def SVSTNT1_SCATTER_INDEX_S : MInst<"svstnt1_scatter[_{2}base]_index[_{d}]", "vPuld", "ilUiUlfd", [IsScatterStore], MemEltTyDefault, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1H_SCATTER_INDEX_S : MInst<"svstnt1h_scatter[_{2}base]_index[_{d}]", "vPuld", "ilUiUl", [IsScatterStore], MemEltTyInt16, "aarch64_sve_stnt1_scatter_scalar_offset">; +def SVSTNT1W_SCATTER_INDEX_S : MInst<"svstnt1w_scatter[_{2}base]_index[_{d}]", "vPuld", "lUl", [IsScatterStore], MemEltTyInt32, "aarch64_sve_stnt1_scatter_scalar_offset">; +} diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index b2fb2638c1a5..57d57af74d18 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7463,8 +7463,56 @@ Value *CodeGenFunction::vectorWrapScalar16(Value *Op) { return Op; } +/// SVEBuiltinMemEltTy - Returns the memory element type for this memory +/// access builtin. Only required if it can't be inferred from the base pointer +/// operand. +llvm::Type *CodeGenFunction::SVEBuiltinMemEltTy(SVETypeFlags TypeFlags) { + switch (TypeFlags.getMemEltType()) { + case SVETypeFlags::MemEltTyDefault: + return getEltType(TypeFlags); + case SVETypeFlags::MemEltTyInt8: + return Builder.getInt8Ty(); + case SVETypeFlags::MemEltTyInt16: + return Builder.getInt16Ty(); + case SVETypeFlags::MemEltTyInt32: + return Builder.getInt32Ty(); + case SVETypeFlags::MemEltTyInt64: + return Builder.getInt64Ty(); + } + llvm_unreachable("Unknown MemEltType"); +} + +llvm::Type *CodeGenFunction::getEltType(SVETypeFlags TypeFlags) { + switch (TypeFlags.getEltType()) { + default: + llvm_unreachable("Invalid SVETypeFlag!"); + + case SVETypeFlags::EltTyInt8: + return Builder.getInt8Ty(); + case SVETypeFlags::EltTyInt16: + return Builder.getInt16Ty(); + case SVETypeFlags::EltTyInt32: + return Builder.getInt32Ty(); + case SVETypeFlags::EltTyInt64: + return Builder.getInt64Ty(); + + case SVETypeFlags::EltTyFloat16: + return Builder.getHalfTy(); + case SVETypeFlags::EltTyFloat32: + return Builder.getFloatTy(); + case SVETypeFlags::EltTyFloat64: + return Builder.getDoubleTy(); + + case SVETypeFlags::EltTyBool8: + case SVETypeFlags::EltTyBool16: + case SVETypeFlags::EltTyBool32: + case SVETypeFlags::EltTyBool64: + return Builder.getInt1Ty(); + } +} + // Return the llvm vector type corresponding to the specified element TypeFlags. -llvm::Type *CodeGenFunction::getSVEType(const SVETypeFlags &TypeFlags) { +llvm::VectorType *CodeGenFunction::getSVEType(const SVETypeFlags &TypeFlags) { switch (TypeFlags.getEltType()) { default: llvm_unreachable("Invalid SVETypeFlag!"); @@ -7528,6 +7576,113 @@ Value *CodeGenFunction::EmitSVEPredicateCast(Value *Pred, return C; } +Value *CodeGenFunction::EmitSVEGatherLoad(SVETypeFlags TypeFlags, + SmallVectorImpl &Ops, + unsigned IntID) { + auto *ResultTy = getSVEType(TypeFlags); + auto *OverloadedTy = llvm::VectorType::get(SVEBuiltinMemEltTy(TypeFlags), + ResultTy->getElementCount()); + + // At the ACLE level there's only one predicate type, svbool_t, which is + // mapped to . However, this might be incompatible with the + // actual type being loaded. For example, when loading doubles (i64) the + // predicated should be instead. At the IR level the type of + // the predicate and the data being loaded must match. Cast accordingly. + Ops[0] = EmitSVEPredicateCast(Ops[0], OverloadedTy); + + Function *F = nullptr; + if (Ops[1]->getType()->isVectorTy()) + // This is the "vector base, scalar offset" case. In order to uniquely + // map this built-in to an LLVM IR intrinsic, we need both the return type + // and the type of the vector base. + F = CGM.getIntrinsic(IntID, {OverloadedTy, Ops[1]->getType()}); + else + // This is the "scalar base, vector offset case". The type of the offset + // is encoded in the name of the intrinsic. We only need to specify the + // return type in order to uniquely map this built-in to an LLVM IR + // intrinsic. + F = CGM.getIntrinsic(IntID, OverloadedTy); + + // Pass 0 when the offset is missing. This can only be applied when using + // the "vector base" addressing mode for which ACLE allows no offset. The + // corresponding LLVM IR always requires an offset. + if (Ops.size() == 2) { + assert(Ops[1]->getType()->isVectorTy() && "Scalar base requires an offset"); + Ops.push_back(ConstantInt::get(Int64Ty, 0)); + } + + // For "vector base, scalar index" scale the index so that it becomes a + // scalar offset. + if (!TypeFlags.isByteIndexed() && Ops[1]->getType()->isVectorTy()) { + unsigned BytesPerElt = + OverloadedTy->getElementType()->getScalarSizeInBits() / 8; + Value *Scale = ConstantInt::get(Int64Ty, BytesPerElt); + Ops[2] = Builder.CreateMul(Ops[2], Scale); + } + + Value *Call = Builder.CreateCall(F, Ops); + + // The following sext/zext is only needed when ResultTy != OverloadedTy. In + // other cases it's folded into a nop. + return TypeFlags.isZExtReturn() ? Builder.CreateZExt(Call, ResultTy) + : Builder.CreateSExt(Call, ResultTy); +} + +Value *CodeGenFunction::EmitSVEScatterStore(SVETypeFlags TypeFlags, + SmallVectorImpl &Ops, + unsigned IntID) { + auto *SrcDataTy = getSVEType(TypeFlags); + auto *OverloadedTy = llvm::VectorType::get(SVEBuiltinMemEltTy(TypeFlags), + SrcDataTy->getElementCount()); + + // In ACLE the source data is passed in the last argument, whereas in LLVM IR + // it's the first argument. Move it accordingly. + Ops.insert(Ops.begin(), Ops.pop_back_val()); + + Function *F = nullptr; + if (Ops[2]->getType()->isVectorTy()) + // This is the "vector base, scalar offset" case. In order to uniquely + // map this built-in to an LLVM IR intrinsic, we need both the return type + // and the type of the vector base. + F = CGM.getIntrinsic(IntID, {OverloadedTy, Ops[2]->getType()}); + else + // This is the "scalar base, vector offset case". The type of the offset + // is encoded in the name of the intrinsic. We only need to specify the + // return type in order to uniquely map this built-in to an LLVM IR + // intrinsic. + F = CGM.getIntrinsic(IntID, OverloadedTy); + + // Pass 0 when the offset is missing. This can only be applied when using + // the "vector base" addressing mode for which ACLE allows no offset. The + // corresponding LLVM IR always requires an offset. + if (Ops.size() == 3) { + assert(Ops[1]->getType()->isVectorTy() && "Scalar base requires an offset"); + Ops.push_back(ConstantInt::get(Int64Ty, 0)); + } + + // Truncation is needed when SrcDataTy != OverloadedTy. In other cases it's + // folded into a nop. + Ops[0] = Builder.CreateTrunc(Ops[0], OverloadedTy); + + // At the ACLE level there's only one predicate type, svbool_t, which is + // mapped to . However, this might be incompatible with the + // actual type being stored. For example, when storing doubles (i64) the + // predicated should be instead. At the IR level the type of + // the predicate and the data being stored must match. Cast accordingly. + Ops[1] = EmitSVEPredicateCast(Ops[1], OverloadedTy); + + // For "vector base, scalar index" scale the index so that it becomes a + // scalar offset. + if (!TypeFlags.isByteIndexed() && Ops[2]->getType()->isVectorTy()) { + unsigned BytesPerElt = + OverloadedTy->getElementType()->getScalarSizeInBits() / 8; + Value *Scale = ConstantInt::get(Int64Ty, BytesPerElt); + Ops[3] = Builder.CreateMul(Ops[3], Scale); + } + + return Builder.CreateCall(F, Ops); +} + Value *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr *E, llvm::Type *ReturnTy, SmallVectorImpl &Ops, @@ -7639,8 +7794,12 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, TypeFlags.isZExtReturn()); else if (TypeFlags.isStore()) return EmitSVEMaskedStore(E, Ops, Builtin->LLVMIntrinsic); + else if (TypeFlags.isGatherLoad()) + return EmitSVEGatherLoad(TypeFlags, Ops, Builtin->LLVMIntrinsic); + else if (TypeFlags.isScatterStore()) + return EmitSVEScatterStore(TypeFlags, Ops, Builtin->LLVMIntrinsic); else if (Builtin->LLVMIntrinsic != 0) { - llvm::Type* OverloadedTy = getSVEType(TypeFlags); + llvm::VectorType *OverloadedTy = getSVEType(TypeFlags); if (TypeFlags.getMergeType() == SVETypeFlags::MergeZeroExp) InsertExplicitZeroOperand(Builder, Ty, Ops); diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 2429f5d4a445..786117a1429e 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3903,9 +3903,21 @@ public: llvm::Value *EmitNeonRShiftImm(llvm::Value *Vec, llvm::Value *Amt, llvm::Type *Ty, bool usgn, const char *name); llvm::Value *vectorWrapScalar16(llvm::Value *Op); + /// SVEBuiltinMemEltTy - Returns the memory element type for this memory + /// access builtin. Only required if it can't be inferred from the base + /// pointer operand. + llvm::Type *SVEBuiltinMemEltTy(SVETypeFlags TypeFlags); - llvm::Type *getSVEType(const SVETypeFlags &TypeFlags); + llvm::Type *getEltType(SVETypeFlags TypeFlags); + + llvm::VectorType *getSVEType(const SVETypeFlags &TypeFlags); llvm::Value *EmitSVEPredicateCast(llvm::Value *Pred, llvm::VectorType *VTy); + llvm::Value *EmitSVEGatherLoad(SVETypeFlags TypeFlags, + llvm::SmallVectorImpl &Ops, + unsigned IntID); + llvm::Value *EmitSVEScatterStore(SVETypeFlags TypeFlags, + llvm::SmallVectorImpl &Ops, + unsigned IntID); llvm::Value *EmitSVEMaskedLoad(const CallExpr *, llvm::Type *ReturnTy, SmallVectorImpl &Ops, unsigned BuiltinID, bool IsZExtReturn); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c index 5ff56627048b..e38fd569fcf4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c @@ -117,6 +117,7 @@ svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base) // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1,_f64,,)(pg, base); } + svint8_t test_svld1_vnum_s8(svbool_t pg, const int8_t *base, int64_t vnum) { // CHECK-LABEL: test_svld1_vnum_s8 @@ -235,3 +236,345 @@ svfloat64_t test_svld1_vnum_f64(svbool_t pg, const float64_t *base, int64_t vnum // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svld1_vnum,_f64,,)(pg, base, vnum); } + +svint32_t test_svld1_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1_gather_u32base_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svld1_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svld1_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1_gather_u32base_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svld1_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _u64, )(pg, bases); +} + +svfloat32_t test_svld1_gather_u32base_f32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1_gather_u32base_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _f32, )(pg, bases); +} + +svfloat64_t test_svld1_gather_u64base_f64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1_gather_u64base_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _f64, )(pg, bases); +} + +svint32_t test_svld1_gather_s32offset_s32(svbool_t pg, const int32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_s32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32( %[[PG]], i32* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, offset, _s32)(pg, base, offsets); +} + +svint64_t test_svld1_gather_s64offset_s64(svbool_t pg, const int64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i64( %[[PG]], i64* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, offset, _s64)(pg, base, offsets); +} + +svuint32_t test_svld1_gather_s32offset_u32(svbool_t pg, const uint32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_s32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i32( %[[PG]], i32* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, offset, _u32)(pg, base, offsets); +} + +svuint64_t test_svld1_gather_s64offset_u64(svbool_t pg, const uint64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i64( %[[PG]], i64* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, offset, _u64)(pg, base, offsets); +} + +svfloat32_t test_svld1_gather_s32offset_f32(svbool_t pg, const float32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_s32offset_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4f32( %[[PG]], float* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, offset, _f32)(pg, base, offsets); +} + +svfloat64_t test_svld1_gather_s64offset_f64(svbool_t pg, const float64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_s64offset_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2f64( %[[PG]], double* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svld1_gather_u32offset_s32(svbool_t pg, const int32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_u32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32( %[[PG]], i32* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, offset, _s32)(pg, base, offsets); +} + +svint64_t test_svld1_gather_u64offset_s64(svbool_t pg, const int64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i64( %[[PG]], i64* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, offset, _s64)(pg, base, offsets); +} + +svuint32_t test_svld1_gather_u32offset_u32(svbool_t pg, const uint32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_u32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i32( %[[PG]], i32* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, offset, _u32)(pg, base, offsets); +} + +svuint64_t test_svld1_gather_u64offset_u64(svbool_t pg, const uint64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i64( %[[PG]], i64* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, offset, _u64)(pg, base, offsets); +} + +svfloat32_t test_svld1_gather_u32offset_f32(svbool_t pg, const float32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1_gather_u32offset_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4f32( %[[PG]], float* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, offset, _f32)(pg, base, offsets); +} + +svfloat64_t test_svld1_gather_u64offset_f64(svbool_t pg, const float64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1_gather_u64offset_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2f64( %[[PG]], double* %base, %offsets) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svld1_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u32base_offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svld1_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svld1_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u32base_offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svld1_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svfloat32_t test_svld1_gather_u32base_offset_f32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u32base_offset_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _offset_f32, )(pg, bases, offset); +} + +svfloat64_t test_svld1_gather_u64base_offset_f64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1_gather_u64base_offset_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _offset_f64, )(pg, bases, offset); +} + +svint32_t test_svld1_gather_s32index_s32(svbool_t pg, const int32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1_gather_s32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32( %[[PG]], i32* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, index, _s32)(pg, base, indices); +} + +svint64_t test_svld1_gather_s64index_s64(svbool_t pg, const int64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1_gather_s64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i64( %[[PG]], i64* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, index, _s64)(pg, base, indices); +} + +svuint32_t test_svld1_gather_s32index_u32(svbool_t pg, const uint32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1_gather_s32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32( %[[PG]], i32* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, index, _u32)(pg, base, indices); +} + +svuint64_t test_svld1_gather_s64index_u64(svbool_t pg, const uint64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1_gather_s64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i64( %[[PG]], i64* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, index, _u64)(pg, base, indices); +} + +svfloat32_t test_svld1_gather_s32index_f32(svbool_t pg, const float32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1_gather_s32index_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4f32( %[[PG]], float* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s32, index, _f32)(pg, base, indices); +} + +svfloat64_t test_svld1_gather_s64index_f64(svbool_t pg, const float64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1_gather_s64index_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2f64( %[[PG]], double* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, s64, index, _f64)(pg, base, indices); +} + +svint32_t test_svld1_gather_u32index_s32(svbool_t pg, const int32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1_gather_u32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32( %[[PG]], i32* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, index, _s32)(pg, base, indices); +} + +svint64_t test_svld1_gather_u64index_s64(svbool_t pg, const int64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1_gather_u64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i64( %[[PG]], i64* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, index, _s64)(pg, base, indices); +} + +svuint32_t test_svld1_gather_u32index_u32(svbool_t pg, const uint32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1_gather_u32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i32( %[[PG]], i32* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, index, _u32)(pg, base, indices); +} + +svuint64_t test_svld1_gather_u64index_u64(svbool_t pg, const uint64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1_gather_u64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i64( %[[PG]], i64* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, index, _u64)(pg, base, indices); +} + +svfloat32_t test_svld1_gather_u32index_f32(svbool_t pg, const float32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1_gather_u32index_f32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4f32( %[[PG]], float* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u32, index, _f32)(pg, base, indices); +} + +svfloat64_t test_svld1_gather_u64index_f64(svbool_t pg, const float64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1_gather_u64index_f64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2f64( %[[PG]], double* %base, %indices) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather_, u64, index, _f64)(pg, base, indices); +} + +svint32_t test_svld1_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u32base_index_s32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svld1_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u64base_index_s64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 3 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svld1_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u32base_index_u32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svld1_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u64base_index_u64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 3 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i64.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _index_u64, )(pg, bases, index); +} + +svfloat32_t test_svld1_gather_u32base_index_f32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u32base_index_f32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4f32.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u32base, _index_f32, )(pg, bases, index); +} + +svfloat64_t test_svld1_gather_u64base_index_f64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1_gather_u64base_index_f64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 3 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2f64.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: ret %[[LOAD]] + return SVE_ACLE_FUNC(svld1_gather, _u64base, _index_f64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c index e9c3a8c9dd6c..dc6637412e96 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c @@ -147,3 +147,147 @@ svuint64_t test_svld1sb_vnum_u64(svbool_t pg, const int8_t *base, int64_t vnum) // CHECK: ret %[[SEXT]] return svld1sb_vnum_u64(pg, base, vnum); } + +svint32_t test_svld1sb_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1sb_gather_u32base_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svld1sb_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sb_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svld1sb_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1sb_gather_u32base_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svld1sb_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sb_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svld1sb_gather_s32offset_s32(svbool_t pg, const int8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_s32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1sb_gather_s64offset_s64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1sb_gather_s32offset_u32(svbool_t pg, const int8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_s32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1sb_gather_s64offset_u64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1sb_gather_u32offset_s32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_u32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1sb_gather_u64offset_s64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1sb_gather_u32offset_u32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_u32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1sb_gather_u64offset_u64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sb_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1sb_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sb_gather_u32base_offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svld1sb_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sb_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svld1sb_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sb_gather_u32base_offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svld1sb_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sb_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sb_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c index a62f86cd91ff..bc38a44c4c20 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c @@ -101,3 +101,259 @@ svuint64_t test_svld1sh_vnum_u64(svbool_t pg, const int16_t *base, int64_t vnum) // CHECK: ret %[[SEXT]] return svld1sh_vnum_u64(pg, base, vnum); } + +svint32_t test_svld1sh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1sh_gather_u32base_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svld1sh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sh_gather_u64base_s64 + // CHECK: %[[PG.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svld1sh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1sh_gather_u32base_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svld1sh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sh_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svld1sh_gather_s32offset_s32(svbool_t pg, const int16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_s32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1sh_gather_s64offset_s64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1sh_gather_s32offset_u32(svbool_t pg, const int16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_s32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1sh_gather_s64offset_u64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1sh_gather_u32offset_s32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_u32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1sh_gather_u64offset_s64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_u64offset_s64 + // CHECK: %[[PG]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1sh_gather_u32offset_u32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_u32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1sh_gather_u64offset_u64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sh_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1sh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sh_gather_u32base_offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svld1sh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sh_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svld1sh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sh_gather_u32base_offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %2 + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svld1sh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sh_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint32_t test_svld1sh_gather_s32index_s32(svbool_t pg, const int16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1sh_gather_s32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s32, index_s32, )(pg, base, indices); +} + +svint64_t test_svld1sh_gather_s64index_s64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1sh_gather_s64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svld1sh_gather_s32index_u32(svbool_t pg, const int16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1sh_gather_s32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svld1sh_gather_s64index_u64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1sh_gather_s64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint32_t test_svld1sh_gather_u32index_s32(svbool_t pg, const int16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1sh_gather_u32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u32, index_s32, )(pg, base, indices); +} + +svint64_t test_svld1sh_gather_u64index_s64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1sh_gather_u64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svld1sh_gather_u32index_u32(svbool_t pg, const int16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1sh_gather_u32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svld1sh_gather_u64index_u64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1sh_gather_u64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svld1sh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sh_gather_u32base_index_s32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svld1sh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sh_gather_u64base_index_s64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svld1sh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sh_gather_u32base_index_u32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svld1sh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sh_gather_u64base_index_u64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c index 79af6fd339aa..8bb18009f8da 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c @@ -55,3 +55,131 @@ svuint64_t test_svld1sw_vnum_u64(svbool_t pg, const int32_t *base, int64_t vnum) // CHECK: ret %[[SEXT]] return svld1sw_vnum_u64(pg, base, vnum); } + +svint64_t test_svld1sw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sw_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svld1sw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1sw_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svld1sw_gather_s64offset_s64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sw_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svld1sw_gather_s64offset_u64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1sw_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svld1sw_gather_u64offset_s64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sw_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svld1sw_gather_u64offset_u64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1sw_gather_u64offset_u64 + // CHECK: %[[PG]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svld1sw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sw_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svld1sw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1sw_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svld1sw_gather_s64index_s64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1sw_gather_s64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svld1sw_gather_s64index_u64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1sw_gather_s64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svld1sw_gather_u64index_s64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1sw_gather_u64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svld1sw_gather_u64index_u64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1sw_gather_u64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svld1sw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sw_gather_u64base_index_s64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: ret %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svld1sw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1sw_gather_u64base_index_u64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[SEXT:.*]] = sext %[[LOAD]] to + // CHECK: %[[SEXT]] + return SVE_ACLE_FUNC(svld1sw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c index fa430cc7bf50..31fda97f37c3 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c @@ -147,3 +147,147 @@ svuint64_t test_svld1ub_vnum_u64(svbool_t pg, const uint8_t *base, int64_t vnum) // CHECK: ret %[[ZEXT]] return svld1ub_vnum_u64(pg, base, vnum); } + +svint32_t test_svld1ub_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1ub_gather_u32base_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svld1ub_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1ub_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svld1ub_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1ub_gather_u32base_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svld1ub_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1ub_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svld1ub_gather_s32offset_s32(svbool_t pg, const uint8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_s32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1ub_gather_s64offset_s64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1ub_gather_s32offset_u32(svbool_t pg, const uint8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_s32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1ub_gather_s64offset_u64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1ub_gather_u32offset_s32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_u32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1ub_gather_u64offset_s64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1ub_gather_u32offset_u32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_u32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1ub_gather_u64offset_u64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1ub_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i8( %[[PG]], i8* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1ub_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1ub_gather_u32base_offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svld1ub_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1ub_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svld1ub_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1ub_gather_u32base_offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i8.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svld1ub_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1ub_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i8.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1ub_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c index 32de2decd8db..0cf1378c370d 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c @@ -101,3 +101,259 @@ svuint64_t test_svld1uh_vnum_u64(svbool_t pg, const uint16_t *base, int64_t vnum // CHECK: ret %[[ZEXT]] return svld1uh_vnum_u64(pg, base, vnum); } + +svint32_t test_svld1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1uh_gather_u32base_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svld1uh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1uh_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svld1uh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svld1uh_gather_u32base_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: et %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svld1uh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1uh_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svld1uh_gather_s32offset_s32(svbool_t pg, const uint16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_s32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1uh_gather_s64offset_s64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %1 to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1uh_gather_s32offset_u32(svbool_t pg, const uint16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_s32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1uh_gather_s64offset_u64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %1 to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1uh_gather_u32offset_s32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_u32offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svld1uh_gather_u64offset_s64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svld1uh_gather_u32offset_u32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_u32offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.nxv4i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svld1uh_gather_u64offset_u64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1uh_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i16( %[[PG]], i16* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %1 to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svld1uh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uh_gather_u32base_offset_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svld1uh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uh_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svld1uh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uh_gather_u32base_offset_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %2 + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svld1uh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uh_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint32_t test_svld1uh_gather_s32index_s32(svbool_t pg, const uint16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1uh_gather_s32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s32, index_s32, )(pg, base, indices); +} + +svint64_t test_svld1uh_gather_s64index_s64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1uh_gather_s64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svld1uh_gather_s32index_u32(svbool_t pg, const uint16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svld1uh_gather_s32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svld1uh_gather_s64index_u64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1uh_gather_s64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint32_t test_svld1uh_gather_u32index_s32(svbool_t pg, const uint16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1uh_gather_u32index_s32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u32, index_s32, )(pg, base, indices); +} + +svint64_t test_svld1uh_gather_u64index_s64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1uh_gather_u64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svld1uh_gather_u32index_u32(svbool_t pg, const uint16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svld1uh_gather_u32index_u32 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.uxtw.index.nxv4i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svld1uh_gather_u64index_u64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1uh_gather_u64index_u64 + // CHECK: %[[PG]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i16( %[[PG]], i16* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svld1uh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uh_gather_u32base_index_s32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svld1uh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uh_gather_u64base_index_s64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svld1uh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uh_gather_u32base_index_u32 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svld1uh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uh_gather_u64base_index_u64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 1 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c index 1c6275712611..b2f21dc66d3b 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c @@ -55,3 +55,131 @@ svuint64_t test_svld1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vnum // CHECK: ret %[[ZEXT]] return svld1uw_vnum_u64(pg, base, vnum); } + +svint64_t test_svld1uw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1uw_gather_u64base_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svld1uw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svld1uw_gather_u64base_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 0) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svld1uw_gather_s64offset_s64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1uw_gather_s64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svld1uw_gather_s64offset_u64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svld1uw_gather_s64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svld1uw_gather_u64offset_s64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1uw_gather_u64offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svld1uw_gather_u64offset_u64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svld1uw_gather_u64offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.nxv2i32( %[[PG]], i32* %base, %offsets) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svld1uw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uw_gather_u64base_offset_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svld1uw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svld1uw_gather_u64base_offset_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %offset) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svld1uw_gather_s64index_s64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1uw_gather_s64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %1 to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svld1uw_gather_s64index_u64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svld1uw_gather_s64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %1 to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svld1uw_gather_u64index_s64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1uw_gather_u64index_s64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[ZEXT]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svld1uw_gather_u64index_u64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svld1uw_gather_u64index_u64 + // CHECK: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.index.nxv2i32( %[[PG]], i32* %base, %indices) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svld1uw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uw_gather_u64base_index_s64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: ret %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svld1uw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svld1uw_gather_u64base_index_u64 + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[SHL:.*]] = shl i64 %index, 2 + // CHECK: %[[LOAD:.*]] = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %[[PG]], %bases, i64 %[[SHL]]) + // CHECK: %[[ZEXT:.*]] = zext %[[LOAD]] to + // CHECK: %[[ZEXT]] + return SVE_ACLE_FUNC(svld1uw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c index 9b2b3f3117a0..291d7c682501 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c @@ -225,3 +225,345 @@ svfloat64_t test_svldff1_vnum_f64(svbool_t pg, const float64_t *base, int64_t vn // CHECK: ret %[[LOAD]] return SVE_ACLE_FUNC(svldff1_vnum,_f64,,)(pg, base, vnum); } + +svint32_t test_svldff1_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldff1_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldff1_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldff1_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _u64, )(pg, bases); +} + +svfloat32_t test_svldff1_gather_u32base_f32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1_gather_u32base_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _f32, )(pg, bases); +} + +svfloat64_t test_svldff1_gather_u64base_f64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1_gather_u64base_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _f64, )(pg, bases); +} + +svint32_t test_svldff1_gather_s32offset_s32(svbool_t pg, const int32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, offset, _s32)(pg, base, offsets); +} + +svint64_t test_svldff1_gather_s64offset_s64(svbool_t pg, const int64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, offset, _s64)(pg, base, offsets); +} + +svuint32_t test_svldff1_gather_s32offset_u32(svbool_t pg, const uint32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, offset, _u32)(pg, base, offsets); +} + +svuint64_t test_svldff1_gather_s64offset_u64(svbool_t pg, const uint64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, offset, _u64)(pg, base, offsets); +} + +svfloat32_t test_svldff1_gather_s32offset_f32(svbool_t pg, const float32_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s32offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4f32( [[PG]], float* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, offset, _f32)(pg, base, offsets); +} + +svfloat64_t test_svldff1_gather_s64offset_f64(svbool_t pg, const float64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_s64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2f64( [[PG]], double* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svldff1_gather_u32offset_s32(svbool_t pg, const int32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, offset, _s32)(pg, base, offsets); +} + +svint64_t test_svldff1_gather_u64offset_s64(svbool_t pg, const int64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, offset, _s64)(pg, base, offsets); +} + +svuint32_t test_svldff1_gather_u32offset_u32(svbool_t pg, const uint32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, offset, _u32)(pg, base, offsets); +} + +svuint64_t test_svldff1_gather_u64offset_u64(svbool_t pg, const uint64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, offset, _u64)(pg, base, offsets); +} + +svfloat32_t test_svldff1_gather_u32offset_f32(svbool_t pg, const float32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u32offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4f32( [[PG]], float* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, offset, _f32)(pg, base, offsets); +} + +svfloat64_t test_svldff1_gather_u64offset_f64(svbool_t pg, const float64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1_gather_u64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2f64( [[PG]], double* %base, %offsets) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svldff1_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldff1_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldff1_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldff1_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svfloat32_t test_svldff1_gather_u32base_offset_f32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u32base_offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _offset_f32, )(pg, bases, offset); +} + +svfloat64_t test_svldff1_gather_u64base_offset_f64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1_gather_u64base_offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _offset_f64, )(pg, bases, offset); +} + +svint32_t test_svldff1_gather_s32index_s32(svbool_t pg, const int32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_s32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32( [[PG]], i32* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, index, _s32)(pg, base, indices); +} + +svint64_t test_svldff1_gather_s64index_s64(svbool_t pg, const int64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, index, _s64)(pg, base, indices); +} + +svuint32_t test_svldff1_gather_s32index_u32(svbool_t pg, const uint32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_s32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32( [[PG]], i32* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, index, _u32)(pg, base, indices); +} + +svuint64_t test_svldff1_gather_s64index_u64(svbool_t pg, const uint64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, index, _u64)(pg, base, indices); +} + +svfloat32_t test_svldff1_gather_s32index_f32(svbool_t pg, const float32_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_s32index_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4f32( [[PG]], float* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s32, index, _f32)(pg, base, indices); +} + +svfloat64_t test_svldff1_gather_s64index_f64(svbool_t pg, const float64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_s64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2f64( [[PG]], double* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, s64, index, _f64)(pg, base, indices); +} + +svint32_t test_svldff1_gather_u32index_s32(svbool_t pg, const int32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_u32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32( [[PG]], i32* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, index, _s32)(pg, base, indices); +} + +svint64_t test_svldff1_gather_u64index_s64(svbool_t pg, const int64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, index, _s64)(pg, base, indices); +} + +svuint32_t test_svldff1_gather_u32index_u32(svbool_t pg, const uint32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_u32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i32( [[PG]], i32* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, index, _u32)(pg, base, indices); +} + +svuint64_t test_svldff1_gather_u64index_u64(svbool_t pg, const uint64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, index, _u64)(pg, base, indices); +} + +svfloat32_t test_svldff1_gather_u32index_f32(svbool_t pg, const float32_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1_gather_u32index_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4f32( [[PG]], float* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u32, index, _f32)(pg, base, indices); +} + +svfloat64_t test_svldff1_gather_u64index_f64(svbool_t pg, const float64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1_gather_u64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2f64( [[PG]], double* %base, %indices) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather_, u64, index, _f64)(pg, base, indices); +} + +svint32_t test_svldff1_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldff1_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldff1_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldff1_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _index_u64, )(pg, bases, index); +} + +svfloat32_t test_svldff1_gather_u32base_index_f32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u32base_index_f32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u32base, _index_f32, )(pg, bases, index); +} + +svfloat64_t test_svldff1_gather_u64base_index_f64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1_gather_u64base_index_f64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + return SVE_ACLE_FUNC(svldff1_gather, _u64base, _index_f64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c index c32ba7a218c1..6d5a964e1cf7 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c @@ -141,3 +141,147 @@ svuint64_t test_svldff1sb_vnum_u64(svbool_t pg, const int8_t *base, int64_t vnum // CHECK: ret %[[SEXT]] return svldff1sb_vnum_u64(pg, base, vnum); } + +svint32_t test_svldff1sb_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1sb_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldff1sb_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sb_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldff1sb_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1sb_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldff1sb_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sb_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svldff1sb_gather_s32offset_s32(svbool_t pg, const int8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_s32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1sb_gather_s64offset_s64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1sb_gather_s32offset_u32(svbool_t pg, const int8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_s32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1sb_gather_s64offset_u64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1sb_gather_u32offset_s32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1sb_gather_u64offset_s64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1sb_gather_u32offset_u32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1sb_gather_u64offset_u64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sb_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1sb_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sb_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldff1sb_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sb_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldff1sb_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sb_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldff1sb_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sb_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sb_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c index 4921a408eaf3..3c60dcb8b295 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c @@ -1,7 +1,15 @@ // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s #include +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + svint32_t test_svldff1sh_s32(svbool_t pg, const int16_t *base) { // CHECK-LABEL: test_svldff1sh_s32 @@ -89,3 +97,259 @@ svuint64_t test_svldff1sh_vnum_u64(svbool_t pg, const int16_t *base, int64_t vnu // CHECK: ret %[[SEXT]] return svldff1sh_vnum_u64(pg, base, vnum); } + +svint32_t test_svldff1sh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldff1sh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldff1sh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldff1sh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svldff1sh_gather_s32offset_s32(svbool_t pg, const int16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_s32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1sh_gather_s64offset_s64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1sh_gather_s32offset_u32(svbool_t pg, const int16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_s32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1sh_gather_s64offset_u64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1sh_gather_u32offset_s32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1sh_gather_u64offset_s64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1sh_gather_u32offset_u32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1sh_gather_u64offset_u64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sh_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1sh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldff1sh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldff1sh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldff1sh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint32_t test_svldff1sh_gather_s32index_s32(svbool_t pg, const int16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_s32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s32, index_s32, )(pg, base, indices); +} + +svint64_t test_svldff1sh_gather_s64index_s64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svldff1sh_gather_s32index_u32(svbool_t pg, const int16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_s32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svldff1sh_gather_s64index_u64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldff1sh_gather_u32index_s32(svbool_t pg, const int16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_u32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u32, index_s32, )(pg, base, indices); +} + +svint64_t test_svldff1sh_gather_u64index_s64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svldff1sh_gather_u32index_u32(svbool_t pg, const int16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_u32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svldff1sh_gather_u64index_u64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1sh_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldff1sh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldff1sh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldff1sh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sh_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldff1sh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sh_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c index 7b65d32d1315..6c65979c32d4 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c @@ -1,7 +1,15 @@ // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s #include +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + svint64_t test_svldff1sw_s64(svbool_t pg, const int32_t *base) { // CHECK-LABEL: test_svldff1sw_s64 @@ -45,3 +53,131 @@ svuint64_t test_svldff1sw_vnum_u64(svbool_t pg, const int32_t *base, int64_t vnu // CHECK: ret %[[SEXT]] return svldff1sw_vnum_u64(pg, base, vnum); } + +svint64_t test_svldff1sw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svldff1sw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldff1sw_gather_s64offset_s64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sw_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldff1sw_gather_s64offset_u64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1sw_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldff1sw_gather_u64offset_s64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sw_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldff1sw_gather_u64offset_u64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1sw_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldff1sw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svldff1sw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldff1sw_gather_s64index_s64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1sw_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldff1sw_gather_s64index_u64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1sw_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldff1sw_gather_u64index_s64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1sw_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldff1sw_gather_u64index_u64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1sw_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldff1sw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svldff1sw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1sw_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + return SVE_ACLE_FUNC(svldff1sw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c index c098adde24e9..a6c117970877 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c @@ -1,7 +1,15 @@ // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s #include +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + svint16_t test_svldff1ub_s16(svbool_t pg, const uint8_t *base) { // CHECK-LABEL: test_svldff1ub_s16 @@ -133,3 +141,147 @@ svuint64_t test_svldff1ub_vnum_u64(svbool_t pg, const uint8_t *base, int64_t vnu // CHECK: ret %[[ZEXT]] return svldff1ub_vnum_u64(pg, base, vnum); } + +svint32_t test_svldff1ub_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1ub_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldff1ub_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1ub_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldff1ub_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1ub_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldff1ub_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1ub_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svldff1ub_gather_s32offset_s32(svbool_t pg, const uint8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_s32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1ub_gather_s64offset_s64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1ub_gather_s32offset_u32(svbool_t pg, const uint8_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_s32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1ub_gather_s64offset_u64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1ub_gather_u32offset_s32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1ub_gather_u64offset_s64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1ub_gather_u32offset_u32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1ub_gather_u64offset_u64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1ub_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1ub_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1ub_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldff1ub_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1ub_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldff1ub_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1ub_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldff1ub_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1ub_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1ub_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c index fd5211e6c831..b335f3184d4c 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c @@ -1,7 +1,15 @@ // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s #include +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + svint32_t test_svldff1uh_s32(svbool_t pg, const uint16_t *base) { // CHECK-LABEL: test_svldff1uh_s32 @@ -89,3 +97,259 @@ svuint64_t test_svldff1uh_vnum_u64(svbool_t pg, const uint16_t *base, int64_t vn // CHECK: ret %[[ZEXT]] return svldff1uh_vnum_u64(pg, base, vnum); } + +svint32_t test_svldff1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldff1uh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldff1uh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldff1uh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _u64, )(pg, bases); +} + +svint32_t test_svldff1uh_gather_s32offset_s32(svbool_t pg, const uint16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_s32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1uh_gather_s64offset_s64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1uh_gather_s32offset_u32(svbool_t pg, const uint16_t *base, svint32_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_s32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1uh_gather_s64offset_u64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1uh_gather_u32offset_s32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldff1uh_gather_u64offset_s64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldff1uh_gather_u32offset_u32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldff1uh_gather_u64offset_u64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1uh_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldff1uh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldff1uh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldff1uh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldff1uh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint32_t test_svldff1uh_gather_s32index_s32(svbool_t pg, const uint16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_s32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s32, index_s32, )(pg, base, indices); +} + +svint64_t test_svldff1uh_gather_s64index_s64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svldff1uh_gather_s32index_u32(svbool_t pg, const uint16_t *base, svint32_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_s32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svldff1uh_gather_s64index_u64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldff1uh_gather_u32index_s32(svbool_t pg, const uint16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_u32index_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u32, index_s32, )(pg, base, indices); +} + +svint64_t test_svldff1uh_gather_u64index_s64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint32_t test_svldff1uh_gather_u32index_u32(svbool_t pg, const uint16_t *base, svuint32_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_u32index_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.uxtw.index.nxv4i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u32, index_u32, )(pg, base, indices); +} + +svuint64_t test_svldff1uh_gather_u64index_u64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1uh_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldff1uh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldff1uh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldff1uh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uh_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldff1uh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uh_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c index bdcfca49afa9..0b47a0630d58 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c @@ -1,7 +1,15 @@ // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s #include +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + svint64_t test_svldff1uw_s64(svbool_t pg, const uint32_t *base) { // CHECK-LABEL: test_svldff1uw_s64 @@ -45,3 +53,131 @@ svuint64_t test_svldff1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vn // CHECK: ret %[[ZEXT]] return svldff1uw_vnum_u64(pg, base, vnum); } + +svint64_t test_svldff1uw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svldff1uw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldff1uw_gather_s64offset_s64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1uw_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldff1uw_gather_s64offset_u64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldff1uw_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldff1uw_gather_u64offset_s64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1uw_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldff1uw_gather_u64offset_u64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldff1uw_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldff1uw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svldff1uw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldff1uw_gather_s64index_s64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1uw_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldff1uw_gather_s64index_u64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldff1uw_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldff1uw_gather_u64index_s64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1uw_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldff1uw_gather_u64index_u64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldff1uw_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldff1uw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svldff1uw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldff1uw_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + return SVE_ACLE_FUNC(svldff1uw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1.c new file mode 100644 index 000000000000..1f00744afe51 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1.c @@ -0,0 +1,349 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint32_t test_svldnt1_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_s32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldnt1_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldnt1_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_u32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldnt1_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _u64, )(pg, bases); +} + +svfloat32_t test_svldnt1_gather_u32base_f32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u32base_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_f32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_f32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _f32, )(pg, bases); +} + +svfloat64_t test_svldnt1_gather_u64base_f64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1_gather_u64base_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_f64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _f64, )(pg, bases); +} + +svint64_t test_svldnt1_gather_s64offset_s64(svbool_t pg, const int64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, offset, _s64)(pg, base, offsets); +} + +svuint64_t test_svldnt1_gather_s64offset_u64(svbool_t pg, const uint64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, offset, _u64)(pg, base, offsets); +} + +svfloat64_t test_svldnt1_gather_s64offset_f64(svbool_t pg, const float64_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_s64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2f64( [[PG]], double* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64offset_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svldnt1_gather_u32offset_s32(svbool_t pg, const int32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32offset_s32'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u32, offset, _s32)(pg, base, offsets); +} + +svint64_t test_svldnt1_gather_u64offset_s64(svbool_t pg, const int64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, offset, _s64)(pg, base, offsets); +} + +svuint32_t test_svldnt1_gather_u32offset_u32(svbool_t pg, const uint32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i32( [[PG]], i32* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32offset_u32'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u32, offset, _u32)(pg, base, offsets); +} + +svuint64_t test_svldnt1_gather_u64offset_u64(svbool_t pg, const uint64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i64( [[PG]], i64* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, offset, _u64)(pg, base, offsets); +} + +svfloat32_t test_svldnt1_gather_u32offset_f32(svbool_t pg, const float32_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u32offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4f32( [[PG]], float* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32offset_f32'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u32, offset, _f32)(pg, base, offsets); +} + +svfloat64_t test_svldnt1_gather_u64offset_f64(svbool_t pg, const float64_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1_gather_u64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2f64( [[PG]], double* %base, %offsets) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64offset_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, offset, _f64)(pg, base, offsets); +} + +svint32_t test_svldnt1_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldnt1_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldnt1_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldnt1_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svfloat32_t test_svldnt1_gather_u32base_offset_f32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u32base_offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_f32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_offset_f32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _offset_f32, )(pg, bases, offset); +} + +svfloat64_t test_svldnt1_gather_u64base_offset_f64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1_gather_u64base_offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_offset_f64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_offset_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _offset_f64, )(pg, bases, offset); +} + +svint64_t test_svldnt1_gather_s64index_s64(svbool_t pg, const int64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64index_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, index, _s64)(pg, base, indices); +} + +svuint64_t test_svldnt1_gather_s64index_u64(svbool_t pg, const uint64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64index_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, index, _u64)(pg, base, indices); +} + +svfloat64_t test_svldnt1_gather_s64index_f64(svbool_t pg, const float64_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_s64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2f64( [[PG]], double* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_s64index_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, s64, index, _f64)(pg, base, indices); +} + +svint64_t test_svldnt1_gather_u64index_s64(svbool_t pg, const int64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64index_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, index, _s64)(pg, base, indices); +} + +svuint64_t test_svldnt1_gather_u64index_u64(svbool_t pg, const uint64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i64( [[PG]], i64* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64index_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, index, _u64)(pg, base, indices); +} + +svfloat64_t test_svldnt1_gather_u64index_f64(svbool_t pg, const float64_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1_gather_u64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2f64( [[PG]], double* %base, %indices) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64index_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather_, u64, index, _f64)(pg, base, indices); +} + +svint32_t test_svldnt1_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_index_s32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldnt1_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_index_s64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldnt1_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_index_u32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldnt1_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_index_u64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _index_u64, )(pg, bases, index); +} + +svfloat32_t test_svldnt1_gather_u32base_index_f32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u32base_index_f32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4f32.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_f32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u32base_index_f32'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u32base, _index_f32, )(pg, bases, index); +} + +svfloat64_t test_svldnt1_gather_u64base_index_f64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1_gather_u64base_index_f64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2f64.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret [[LOAD]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1_gather_index_f64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1_gather_u64base_index_f64'}} + return SVE_ACLE_FUNC(svldnt1_gather, _u64base, _index_f64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sb.c new file mode 100644 index 000000000000..cd87d4491bc2 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sb.c @@ -0,0 +1,167 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint32_t test_svldnt1sb_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1sb_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32base_s32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldnt1sb_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sb_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldnt1sb_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1sb_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32base_u32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldnt1sb_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sb_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1sb_gather_s64offset_s64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sb_gather_s64offset_u64(svbool_t pg, const int8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1sb_gather_u32offset_s32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32offset_s32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldnt1sb_gather_u64offset_s64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldnt1sb_gather_u32offset_u32(svbool_t pg, const int8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32offset_u32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sb_gather_u64offset_u64(svbool_t pg, const int8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sb_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1sb_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sb_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldnt1sb_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sb_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldnt1sb_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sb_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldnt1sb_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sb_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sb_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sb_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sb_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sh.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sh.c new file mode 100644 index 000000000000..a595f70a9572 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sh.c @@ -0,0 +1,259 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint32_t test_svldnt1sh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_s32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldnt1sh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldnt1sh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_u32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldnt1sh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1sh_gather_s64offset_s64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sh_gather_s64offset_u64(svbool_t pg, const int16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1sh_gather_u32offset_s32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32offset_s32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldnt1sh_gather_u64offset_s64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldnt1sh_gather_u32offset_u32(svbool_t pg, const int16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32offset_u32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sh_gather_u64offset_u64(svbool_t pg, const int16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sh_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1sh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldnt1sh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldnt1sh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldnt1sh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldnt1sh_gather_s64index_s64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1sh_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_s64index_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1sh_gather_s64index_u64(svbool_t pg, const int16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1sh_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_s64index_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1sh_gather_u64index_s64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1sh_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64index_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1sh_gather_u64index_u64(svbool_t pg, const int16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1sh_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64index_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldnt1sh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_index_s32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldnt1sh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_index_s64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldnt1sh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sh_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u32base_index_u32'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldnt1sh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sh_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sh_gather_u64base_index_u64'}} + return SVE_ACLE_FUNC(svldnt1sh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sw.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sw.c new file mode 100644 index 000000000000..921861e4bcff --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1sw.c @@ -0,0 +1,169 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint64_t test_svldnt1sw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svldnt1sw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1sw_gather_s64offset_s64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sw_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sw_gather_s64offset_u64(svbool_t pg, const int32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1sw_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldnt1sw_gather_u64offset_s64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sw_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1sw_gather_u64offset_u64(svbool_t pg, const int32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1sw_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldnt1sw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svldnt1sw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldnt1sw_gather_s64index_s64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1sw_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_s64index_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1sw_gather_s64index_u64(svbool_t pg, const int32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1sw_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_s64index_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1sw_gather_u64index_s64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1sw_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64index_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1sw_gather_u64index_u64(svbool_t pg, const int32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1sw_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64index_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1sw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_index_s64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svldnt1sw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1sw_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[SEXT:%.*]] = sext [[LOAD]] to + // CHECK: ret [[SEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1sw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1sw_gather_u64base_index_u64'}} + return SVE_ACLE_FUNC(svldnt1sw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1ub.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1ub.c new file mode 100644 index 000000000000..05fbfebb9a97 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1ub.c @@ -0,0 +1,167 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint32_t test_svldnt1ub_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1ub_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32base_s32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldnt1ub_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1ub_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldnt1ub_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1ub_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32base_u32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldnt1ub_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1ub_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1ub_gather_s64offset_s64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1ub_gather_s64offset_u64(svbool_t pg, const uint8_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1ub_gather_u32offset_s32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32offset_s32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldnt1ub_gather_u64offset_s64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldnt1ub_gather_u32offset_u32(svbool_t pg, const uint8_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32offset_u32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldnt1ub_gather_u64offset_u64(svbool_t pg, const uint8_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1ub_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i8( [[PG]], i8* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1ub_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1ub_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldnt1ub_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1ub_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldnt1ub_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1ub_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i8.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldnt1ub_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1ub_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i8.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1ub_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1ub_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1ub_gather, _u64base, _offset_u64, )(pg, bases, offset); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uh.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uh.c new file mode 100644 index 000000000000..5627060b878b --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uh.c @@ -0,0 +1,259 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint32_t test_svldnt1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_s32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _s32, )(pg, bases); +} + +svint64_t test_svldnt1uh_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _s64, )(pg, bases); +} + +svuint32_t test_svldnt1uh_gather_u32base_u32(svbool_t pg, svuint32_t bases) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_u32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _u32, )(pg, bases); +} + +svuint64_t test_svldnt1uh_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1uh_gather_s64offset_s64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1uh_gather_s64offset_u64(svbool_t pg, const uint16_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1uh_gather_u32offset_s32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32offset_s32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u32, offset_s32, )(pg, base, offsets); +} + +svint64_t test_svldnt1uh_gather_u64offset_s64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint32_t test_svldnt1uh_gather_u32offset_u32(svbool_t pg, const uint16_t *base, svuint32_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32offset_u32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u32, offset_u32, )(pg, base, offsets); +} + +svuint64_t test_svldnt1uh_gather_u64offset_u64(svbool_t pg, const uint16_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1uh_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i16( [[PG]], i16* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint32_t test_svldnt1uh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _offset_s32, )(pg, bases, offset); +} + +svint64_t test_svldnt1uh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint32_t test_svldnt1uh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _offset_u32, )(pg, bases, offset); +} + +svuint64_t test_svldnt1uh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldnt1uh_gather_s64index_s64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1uh_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64index_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1uh_gather_s64index_u64(svbool_t pg, const uint16_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1uh_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64index_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1uh_gather_u64index_s64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1uh_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64index_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1uh_gather_u64index_u64(svbool_t pg, const uint16_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1uh_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16( [[PG]], i16* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64index_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, index_u64, )(pg, base, indices); +} + +svint32_t test_svldnt1uh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_index_s32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _index_s32, )(pg, bases, index); +} + +svint64_t test_svldnt1uh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_index_s64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint32_t test_svldnt1uh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uh_gather_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u32'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_index_u32'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _index_u32, )(pg, bases, index); +} + +svuint64_t test_svldnt1uh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uh_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_index_u64'}} + return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uw.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uw.c new file mode 100644 index 000000000000..e64ec26be8de --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uw.c @@ -0,0 +1,169 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +svint64_t test_svldnt1uw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _s64, )(pg, bases); +} + +svuint64_t test_svldnt1uw_gather_u64base_u64(svbool_t pg, svuint64_t bases) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 0) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _u64, )(pg, bases); +} + +svint64_t test_svldnt1uw_gather_s64offset_s64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1uw_gather_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_s64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, s64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1uw_gather_s64offset_u64(svbool_t pg, const uint32_t *base, svint64_t offsets) { + // CHECK-LABEL: test_svldnt1uw_gather_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_s64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, s64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldnt1uw_gather_u64offset_s64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1uw_gather_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, u64, offset_s64, )(pg, base, offsets); +} + +svuint64_t test_svldnt1uw_gather_u64offset_u64(svbool_t pg, const uint32_t *base, svuint64_t offsets) { + // CHECK-LABEL: test_svldnt1uw_gather_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.nxv2i32( [[PG]], i32* %base, %offsets) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, u64, offset_u64, )(pg, base, offsets); +} + +svint64_t test_svldnt1uw_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _offset_s64, )(pg, bases, offset); +} + +svuint64_t test_svldnt1uw_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 %offset) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_offset_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _offset_u64, )(pg, bases, offset); +} + +svint64_t test_svldnt1uw_gather_s64index_s64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1uw_gather_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_s64index_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, s64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1uw_gather_s64index_u64(svbool_t pg, const uint32_t *base, svint64_t indices) { + // CHECK-LABEL: test_svldnt1uw_gather_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_s64index_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, s64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1uw_gather_u64index_s64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1uw_gather_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64index_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, u64, index_s64, )(pg, base, indices); +} + +svuint64_t test_svldnt1uw_gather_u64index_u64(svbool_t pg, const uint32_t *base, svuint64_t indices) { + // CHECK-LABEL: test_svldnt1uw_gather_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.index.nxv2i32( [[PG]], i32* %base, %indices) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64index_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather_, u64, index_u64, )(pg, base, indices); +} + +svint64_t test_svldnt1uw_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_s64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_index_s64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _index_s64, )(pg, bases, index); +} + +svuint64_t test_svldnt1uw_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) { + // CHECK-LABEL: test_svldnt1uw_gather_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: [[LOAD:%.*]] = call @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i32.nxv2i64( [[PG]], %bases, i64 [[SHL]]) + // CHECK: [[ZEXT:%.*]] = zext [[LOAD]] to + // CHECK: ret [[ZEXT]] + // overload-warning@+2 {{implicit declaration of function 'svldnt1uw_gather_index_u64'}} + // expected-warning@+1 {{implicit declaration of function 'svldnt1uw_gather_u64base_index_u64'}} + return SVE_ACLE_FUNC(svldnt1uw_gather, _u64base, _index_u64, )(pg, bases, index); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c new file mode 100644 index 000000000000..e088836648c1 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1.c @@ -0,0 +1,349 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +void test_svstnt1_scatter_u32base_s32(svbool_t pg, svuint32_t bases, svint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_s32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, , _s32)(pg, bases, data); +} + +void test_svstnt1_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, , _s64)(pg, bases, data); +} + +void test_svstnt1_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_u32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, , _u32)(pg, bases, data); +} + +void test_svstnt1_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, , _u64)(pg, bases, data); +} + +void test_svstnt1_scatter_u32base_f32(svbool_t pg, svuint32_t bases, svfloat32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_f32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, , _f32)(pg, bases, data); +} + +void test_svstnt1_scatter_u64base_f64(svbool_t pg, svuint64_t bases, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64( %data, [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, , _f64)(pg, bases, data); +} + +void test_svstnt1_scatter_s64offset_s64(svbool_t pg, int64_t *base, svint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( %data, [[PG]], i64* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_s64offset_u64(svbool_t pg, uint64_t *base, svint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( %data, [[PG]], i64* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_s64offset_f64(svbool_t pg, float64_t *base, svint64_t offsets, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2f64( %data, [[PG]], double* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64offset_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, offset, _f64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u32offset_s32(svbool_t pg, int32_t *base, svuint32_t offsets, svint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32( %data, [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32offset_s32'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u32, offset, _s32)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u64offset_s64(svbool_t pg, int64_t *base, svuint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( %data, [[PG]], i64* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u32offset_u32(svbool_t pg, uint32_t *base, svuint32_t offsets, svuint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i32( %data, [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32offset_u32'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u32, offset, _u32)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u64offset_u64(svbool_t pg, uint64_t *base, svuint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i64( %data, [[PG]], i64* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u32offset_f32(svbool_t pg, float32_t *base, svuint32_t offsets, svfloat32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4f32( %data, [[PG]], float* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32offset_f32'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u32, offset, _f32)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u64offset_f64(svbool_t pg, float64_t *base, svuint64_t offsets, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2f64( %data, [[PG]], double* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64offset_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, offset, _f64)(pg, base, offsets, data); +} + +void test_svstnt1_scatter_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset, svint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_offset_s32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _offset, _s32)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_offset_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _offset, _s64)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset, svuint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_offset_u32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _offset, _u32)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_offset_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _offset, _u64)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_u32base_offset_f32(svbool_t pg, svuint32_t bases, int64_t offset, svfloat32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_offset_f32 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_offset_f32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _offset, _f32)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_u64base_offset_f64(svbool_t pg, svuint64_t bases, int64_t offset, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_offset_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64( %data, [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_offset_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _offset, _f64)(pg, bases, offset, data); +} + +void test_svstnt1_scatter_s64index_s64(svbool_t pg, int64_t *base, svint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( %data, [[PG]], i64* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64index_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_s64index_u64(svbool_t pg, uint64_t *base, svint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( %data, [[PG]], i64* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64index_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_s64index_f64(svbool_t pg, float64_t *base, svint64_t indices, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_s64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64( %data, [[PG]], double* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_s64index_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, s64, index, _f64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_u64index_s64(svbool_t pg, int64_t *base, svuint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64index_s64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( %data, [[PG]], i64* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64index_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_u64index_u64(svbool_t pg, uint64_t *base, svuint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64index_u64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64( %data, [[PG]], i64* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64index_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_u64index_f64(svbool_t pg, float64_t *base, svuint64_t indices, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64index_f64 + // CHECK: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64( %data, [[PG]], double* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64index_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter_, u64, index, _f64)(pg, base, indices, data); +} + +void test_svstnt1_scatter_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index, svint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_index_s32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_index_s32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _index, _s32)(pg, bases, index, data); +} + +void test_svstnt1_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index, svint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_index_s64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_index_s64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _index, _s64)(pg, bases, index, data); +} + +void test_svstnt1_scatter_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index, svuint32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_index_u32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i32.nxv4i32( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_index_u32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _index, _u32)(pg, bases, index, data); +} + +void test_svstnt1_scatter_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index, svuint64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_index_u64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i64.nxv2i64( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_index_u64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _index, _u64)(pg, bases, index, data); +} + +void test_svstnt1_scatter_u32base_index_f32(svbool_t pg, svuint32_t bases, int64_t index, svfloat32_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u32base_index_f32 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4f32.nxv4i32( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u32base_index_f32'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u32base, _index, _f32)(pg, bases, index, data); +} + +void test_svstnt1_scatter_u64base_index_f64(svbool_t pg, svuint64_t bases, int64_t index, svfloat64_t data) { + // CHECK-LABEL: test_svstnt1_scatter_u64base_index_f64 + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 3 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2f64.nxv2i64( %data, [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1_scatter_u64base_index_f64'}} + return SVE_ACLE_FUNC(svstnt1_scatter, _u64base, _index, _f64)(pg, bases, index, data); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c new file mode 100644 index 000000000000..d94d6b4f34e3 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1b.c @@ -0,0 +1,167 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +void test_svstnt1b_scatter_u32base_s32(svbool_t pg, svuint32_t bases, svint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32base_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32base_s32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u32base, , _s32)(pg, bases, data); +} + +void test_svstnt1b_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64base_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64base_s64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u64base, , _s64)(pg, bases, data); +} + +void test_svstnt1b_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32base_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32base_u32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u32base, , _u32)(pg, bases, data); +} + +void test_svstnt1b_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64base_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64base_u64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u64base, , _u64)(pg, bases, data); +} + +void test_svstnt1b_scatter_s64offset_s64(svbool_t pg, int8_t *base, svint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_s64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_s64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, s64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_s64offset_u64(svbool_t pg, uint8_t *base, svint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_s64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_s64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, s64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_u32offset_s32(svbool_t pg, int8_t *base, svuint32_t offsets, svint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32offset_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32offset_s32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, u32, offset, _s32)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_u64offset_s64(svbool_t pg, int8_t *base, svuint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, u64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_u32offset_u32(svbool_t pg, uint8_t *base, svuint32_t offsets, svuint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32offset_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32offset_u32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, u32, offset, _u32)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_u64offset_u64(svbool_t pg, uint8_t *base, svuint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i8( [[TRUNC]], [[PG]], i8* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter_, u64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1b_scatter_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset, svint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32base_offset_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u32base, _offset, _s32)(pg, bases, offset, data); +} + +void test_svstnt1b_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset, svint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64base_offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u64base, _offset, _s64)(pg, bases, offset, data); +} + +void test_svstnt1b_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset, svuint32_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u32base_offset_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i8.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u32base, _offset, _u32)(pg, bases, offset, data); +} + +void test_svstnt1b_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset, svuint64_t data) { + // CHECK-LABEL: test_svstnt1b_scatter_u64base_offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i8.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1b_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1b_scatter_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svstnt1b_scatter, _u64base, _offset, _u64)(pg, bases, offset, data); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c new file mode 100644 index 000000000000..f457ada228f3 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1h.c @@ -0,0 +1,259 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +void test_svstnt1h_scatter_u32base_s32(svbool_t pg, svuint32_t bases, svint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_s32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, , _s32)(pg, bases, data); +} + +void test_svstnt1h_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, , _s64)(pg, bases, data); +} + +void test_svstnt1h_scatter_u32base_u32(svbool_t pg, svuint32_t bases, svuint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_u32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, , _u32)(pg, bases, data); +} + +void test_svstnt1h_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, , _u64)(pg, bases, data); +} + +void test_svstnt1h_scatter_s64offset_s64(svbool_t pg, int16_t *base, svint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_s64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_s64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, s64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_s64offset_u64(svbool_t pg, uint16_t *base, svint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_s64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_s64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, s64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_u32offset_s32(svbool_t pg, int16_t *base, svuint32_t offsets, svint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32offset_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32offset_s32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u32, offset, _s32)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_u64offset_s64(svbool_t pg, int16_t *base, svuint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_u32offset_u32(svbool_t pg, uint16_t *base, svuint32_t offsets, svuint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32offset_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.uxtw.nxv4i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32offset_u32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u32, offset, _u32)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_u64offset_u64(svbool_t pg, uint16_t *base, svuint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1h_scatter_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset, svint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_offset_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_offset_s32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, _offset, _s32)(pg, bases, offset, data); +} + +void test_svstnt1h_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, _offset, _s64)(pg, bases, offset, data); +} + +void test_svstnt1h_scatter_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset, svuint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_offset_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_offset_u32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, _offset, _u32)(pg, bases, offset, data); +} + +void test_svstnt1h_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, _offset, _u64)(pg, bases, offset, data); +} + +void test_svstnt1h_scatter_s64index_s64(svbool_t pg, int16_t *base, svint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_s64index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_s64index_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, s64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1h_scatter_s64index_u64(svbool_t pg, uint16_t *base, svint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_s64index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_s64index_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, s64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1h_scatter_u64index_s64(svbool_t pg, int16_t *base, svuint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64index_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1h_scatter_u64index_u64(svbool_t pg, uint16_t *base, svuint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16( [[TRUNC]], [[PG]], i16* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64index_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter_, u64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1h_scatter_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index, svint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_index_s32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_index_s32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, _index, _s32)(pg, bases, index, data); +} + +void test_svstnt1h_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index, svint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_index_s64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, _index, _s64)(pg, bases, index, data); +} + +void test_svstnt1h_scatter_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index, svuint32_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u32base_index_u32 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv4i16.nxv4i32( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u32base_index_u32'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u32base, _index, _u32)(pg, bases, index, data); +} + +void test_svstnt1h_scatter_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index, svuint64_t data) { + // CHECK-LABEL: test_svstnt1h_scatter_u64base_index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i16.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1h_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1h_scatter_u64base_index_u64'}} + return SVE_ACLE_FUNC(svstnt1h_scatter, _u64base, _index, _u64)(pg, bases, index, data); +} diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c new file mode 100644 index 000000000000..98f1ecd54407 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_stnt1w.c @@ -0,0 +1,169 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4 +#endif + +void test_svstnt1w_scatter_u64base_s64(svbool_t pg, svuint64_t bases, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc [[DATA:%.*]] to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, , _s64)(pg, bases, data); +} + +void test_svstnt1w_scatter_u64base_u64(svbool_t pg, svuint64_t bases, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 0) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, , _u64)(pg, bases, data); +} + +void test_svstnt1w_scatter_s64offset_s64(svbool_t pg, int32_t *base, svint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_s64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_s64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, s64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1w_scatter_s64offset_u64(svbool_t pg, uint32_t *base, svint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_s64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_s64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, s64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1w_scatter_u64offset_s64(svbool_t pg, int32_t *base, svuint64_t offsets, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64offset_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, u64, offset, _s64)(pg, base, offsets, data); +} + +void test_svstnt1w_scatter_u64offset_u64(svbool_t pg, uint32_t *base, svuint64_t offsets, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %offsets) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64offset_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, u64, offset, _u64)(pg, base, offsets, data); +} + +void test_svstnt1w_scatter_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_offset_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_offset_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, _offset, _s64)(pg, bases, offset, data); +} + +void test_svstnt1w_scatter_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_offset_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 %offset) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_offset'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_offset_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, _offset, _u64)(pg, bases, offset, data); +} + +void test_svstnt1w_scatter_s64index_s64(svbool_t pg, int32_t *base, svint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_s64index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_s64index_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, s64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1w_scatter_s64index_u64(svbool_t pg, uint32_t *base, svint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_s64index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_s64index_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, s64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1w_scatter_u64index_s64(svbool_t pg, int32_t *base, svuint64_t indices, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64index_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, u64, index, _s64)(pg, base, indices, data); +} + +void test_svstnt1w_scatter_u64index_u64(svbool_t pg, uint32_t *base, svuint64_t indices, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32( [[TRUNC]], [[PG]], i32* %base, %indices) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64index_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter_, u64, index, _u64)(pg, base, indices, data); +} + +void test_svstnt1w_scatter_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index, svint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_index_s64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_index_s64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, _index, _s64)(pg, bases, index, data); +} + +void test_svstnt1w_scatter_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index, svuint64_t data) { + // CHECK-LABEL: test_svstnt1w_scatter_u64base_index_u64 + // CHECK-DAG: [[TRUNC:%.*]] = trunc %data to + // CHECK-DAG: [[PG:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 2 + // CHECK: call void @llvm.aarch64.sve.stnt1.scatter.scalar.offset.nxv2i32.nxv2i64( [[TRUNC]], [[PG]], %bases, i64 [[SHL]]) + // CHECK: ret void + // overload-warning@+2 {{implicit declaration of function 'svstnt1w_scatter_index'}} + // expected-warning@+1 {{implicit declaration of function 'svstnt1w_scatter_u64base_index_u64'}} + return SVE_ACLE_FUNC(svstnt1w_scatter, _u64base, _index, _u64)(pg, bases, index, data); +} diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index 1e01f611bfa2..a32345e6a9d5 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -481,6 +481,11 @@ void SVEType::applyModifier(char Mod) { Signed = false; Float = false; break; + case 'x': + Predicate = false; + Signed = true; + Float = false; + break; case 'i': Predicate = false; Float = false; -- GitLab From 8c61114c53dcd6139a4a750925b91ed9bcf4178c Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Fri, 17 Apr 2020 10:29:15 -0400 Subject: [PATCH 072/910] [libc++/abi/unwind] Rename Lit features for no exceptions to 'no-exceptions' Instead of having different names for the same Lit feature accross code bases, use the same name everywhere. This NFC commit is in preparation for a refactor where all three projects will be using the same Lit feature detection logic, and hence it won't be convenient to use different names for the feature. Differential Revision: https://reviews.llvm.org/D78370 --- libcxx/test/libcxx/algorithms/debug_less.pass.cpp | 2 +- .../test/libcxx/containers/associative/map/at.abort.pass.cpp | 2 +- .../libcxx/containers/associative/map/at.const.abort.pass.cpp | 2 +- .../libcxx/containers/sequences/vector/asan_throw.pass.cpp | 2 +- .../test/libcxx/containers/unord/unord.map/at.abort.pass.cpp | 2 +- .../libcxx/containers/unord/unord.map/at.const.abort.pass.cpp | 2 +- .../iostreams.base/ios/iostate.flags/clear.abort.pass.cpp | 2 +- libcxx/test/libcxx/localization/locales/locale.abort.pass.cpp | 2 +- .../libcxx/localization/locales/locale.category.abort.pass.cpp | 2 +- .../test/libcxx/localization/locales/use_facet.abort.pass.cpp | 2 +- libcxx/test/libcxx/strings/iterators.exceptions.pass.cpp | 2 +- .../deque/deque.modifiers/push_back_exception_safety.pass.cpp | 2 +- .../deque/deque.modifiers/push_front_exception_safety.pass.cpp | 2 +- .../forwardlist.modifiers/push_front_exception_safety.pass.cpp | 2 +- .../list/list.modifiers/push_back_exception_safety.pass.cpp | 2 +- .../list/list.modifiers/push_front_exception_safety.pass.cpp | 2 +- .../support.exception/except.nested/rethrow_if_nested.pass.cpp | 2 +- .../support.exception/except.nested/rethrow_nested.pass.cpp | 2 +- .../support.exception/except.nested/throw_with_nested.pass.cpp | 2 +- .../support.exception/propagation/current_exception.pass.cpp | 2 +- .../support.exception/propagation/make_exception_ptr.pass.cpp | 2 +- .../support.exception/propagation/rethrow_exception.pass.cpp | 2 +- .../support.exception/uncaught/uncaught_exception.pass.cpp | 2 +- .../support.exception/uncaught/uncaught_exceptions.pass.cpp | 3 +-- libcxx/test/std/re/re.alg/re.alg.match/exponential.pass.cpp | 2 +- libcxx/test/std/re/re.alg/re.alg.replace/exponential.pass.cpp | 2 +- libcxx/test/std/re/re.alg/re.alg.search/exponential.pass.cpp | 2 +- libcxx/test/std/re/re.grammar/excessive_brace_count.pass.cpp | 2 +- libcxx/test/std/re/re.grammar/excessive_brace_min_max.pass.cpp | 2 +- .../std/re/re.regex/re.regex.construct/bad_backref.pass.cpp | 2 +- .../test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp | 2 +- .../std/re/re.regex/re.regex.construct/bad_escape.pass.cpp | 2 +- .../test/std/re/re.regex/re.regex.construct/bad_range.pass.cpp | 2 +- .../std/re/re.regex/re.regex.construct/bad_repeat.pass.cpp | 2 +- .../std/strings/basic.string/string.capacity/max_size.pass.cpp | 2 +- .../basic.string/string.capacity/over_max_size.pass.cpp | 2 +- .../std/thread/futures/futures.promise/set_exception.pass.cpp | 2 +- .../futures.promise/set_exception_at_thread_exit.pass.cpp | 2 +- .../std/thread/futures/futures.promise/set_rvalue.pass.cpp | 2 +- .../std/thread/futures/futures.promise/set_value_void.pass.cpp | 2 +- .../std/thread/futures/futures.shared_future/dtor.pass.cpp | 2 +- .../std/thread/futures/futures.unique_future/dtor.pass.cpp | 2 +- .../thread.condition.condvarany/wait_terminates.sh.cpp | 2 +- .../test/std/utilities/any/any.class/any.assign/copy.pass.cpp | 2 +- .../test/std/utilities/any/any.class/any.assign/move.pass.cpp | 2 +- .../test/std/utilities/any/any.class/any.assign/value.pass.cpp | 2 +- libcxx/test/std/utilities/any/any.class/any.cons/copy.pass.cpp | 2 +- .../utilities/any/any.class/any.cons/in_place_type.pass.cpp | 2 +- libcxx/test/std/utilities/any/any.class/any.cons/move.pass.cpp | 2 +- .../test/std/utilities/any/any.class/any.cons/value.pass.cpp | 2 +- .../std/utilities/any/any.class/any.modifiers/emplace.pass.cpp | 2 +- .../std/utilities/any/any.class/any.modifiers/reset.pass.cpp | 2 +- .../std/utilities/any/any.class/any.modifiers/swap.pass.cpp | 2 +- .../any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp | 2 +- .../any/any.nonmembers/any.cast/any_cast_reference.pass.cpp | 2 +- libcxx/test/std/utilities/any/any.nonmembers/make_any.pass.cpp | 2 +- libcxx/test/std/utilities/any/any.nonmembers/swap.pass.cpp | 2 +- .../default.allocator/allocator.members/allocate.size.pass.cpp | 2 +- .../nullptr_t_deleter_allocator_throw.pass.cpp | 2 +- .../nullptr_t_deleter_throw.pass.cpp | 2 +- .../pointer_deleter_allocator_throw.pass.cpp | 2 +- .../util.smartptr.shared.const/pointer_deleter_throw.pass.cpp | 2 +- .../util.smartptr.shared.const/pointer_throw.pass.cpp | 2 +- .../optional/optional.object/optional.object.ctor/U.pass.cpp | 2 +- .../optional.object/optional.object.ctor/const_T.pass.cpp | 2 +- .../optional.object/optional.object.ctor/move.pass.cpp | 2 +- .../optional.object/optional.object.ctor/rvalue_T.pass.cpp | 2 +- .../optional.object/optional.object.observe/value.pass.cpp | 2 +- .../optional.object.observe/value_const.pass.cpp | 2 +- .../optional.object.observe/value_const_rvalue.pass.cpp | 2 +- .../optional.object.observe/value_rvalue.pass.cpp | 2 +- .../utilities/optional/optional.specalg/make_optional.pass.cpp | 2 +- .../test/std/utilities/variant/variant.get/get_index.pass.cpp | 2 +- .../test/std/utilities/variant/variant.get/get_type.pass.cpp | 2 +- .../variant/variant.variant/variant.assign/T.pass.cpp | 2 +- .../variant/variant.variant/variant.assign/copy.pass.cpp | 2 +- .../variant/variant.variant/variant.assign/move.pass.cpp | 2 +- .../utilities/variant/variant.variant/variant.ctor/T.pass.cpp | 2 +- .../variant/variant.variant/variant.ctor/copy.pass.cpp | 2 +- .../variant/variant.variant/variant.ctor/default.pass.cpp | 2 +- .../variant.variant/variant.ctor/in_place_index_args.pass.cpp | 2 +- .../variant.ctor/in_place_index_init_list_args.pass.cpp | 2 +- .../variant.variant/variant.ctor/in_place_type_args.pass.cpp | 2 +- .../variant.ctor/in_place_type_init_list_args.pass.cpp | 2 +- .../variant/variant.variant/variant.ctor/move.pass.cpp | 2 +- .../variant.variant/variant.mod/emplace_index_args.pass.cpp | 2 +- .../variant.mod/emplace_index_init_list_args.pass.cpp | 2 +- .../variant.variant/variant.mod/emplace_type_args.pass.cpp | 2 +- .../variant.mod/emplace_type_init_list_args.pass.cpp | 2 +- .../variant/variant.variant/variant.swap/swap.pass.cpp | 2 +- libcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp | 2 +- .../test.support/test_macros_header_exceptions.pass.cpp | 2 +- libcxx/utils/libcxx/test/config.py | 2 +- libcxxabi/test/backtrace_test.pass.cpp | 2 +- libcxxabi/test/catch_array_01.pass.cpp | 2 +- libcxxabi/test/catch_array_02.pass.cpp | 2 +- libcxxabi/test/catch_class_01.pass.cpp | 2 +- libcxxabi/test/catch_class_02.pass.cpp | 2 +- libcxxabi/test/catch_class_03.pass.cpp | 2 +- libcxxabi/test/catch_class_04.pass.cpp | 2 +- libcxxabi/test/catch_const_pointer_nullptr.pass.cpp | 2 +- libcxxabi/test/catch_function_01.pass.cpp | 2 +- libcxxabi/test/catch_function_02.pass.cpp | 2 +- libcxxabi/test/catch_function_03.pass.cpp | 2 +- libcxxabi/test/catch_in_noexcept.pass.cpp | 3 ++- libcxxabi/test/catch_member_data_pointer_01.pass.cpp | 2 +- libcxxabi/test/catch_member_function_pointer_01.pass.cpp | 2 +- libcxxabi/test/catch_member_function_pointer_02.pass.cpp | 2 +- libcxxabi/test/catch_member_pointer_nullptr.pass.cpp | 2 +- libcxxabi/test/catch_multi_level_pointer.pass.cpp | 2 +- libcxxabi/test/catch_pointer_nullptr.pass.cpp | 3 ++- libcxxabi/test/catch_pointer_reference.pass.cpp | 2 +- libcxxabi/test/catch_ptr.pass.cpp | 2 +- libcxxabi/test/catch_ptr_02.pass.cpp | 2 +- libcxxabi/test/catch_reference_nullptr.pass.cpp | 3 ++- libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp | 2 +- libcxxabi/test/exception_object_alignment.2.pass.cpp | 2 +- libcxxabi/test/exception_object_alignment.pass.cpp | 2 +- libcxxabi/test/guard_threaded_test.pass.cpp | 3 ++- libcxxabi/test/incomplete_type.sh.cpp | 2 +- libcxxabi/test/inherited_exception.pass.cpp | 2 +- libcxxabi/test/libcxxabi/test/config.py | 2 +- .../test/native/arm-linux-eabi/ttype-encoding-00.pass.sh.s | 2 +- .../test/native/arm-linux-eabi/ttype-encoding-90.pass.sh.s | 2 +- libcxxabi/test/noexception1.pass.cpp | 2 +- libcxxabi/test/noexception2.pass.cpp | 2 +- libcxxabi/test/noexception3.pass.cpp | 2 +- libcxxabi/test/noexception4.pass.cpp | 2 +- libcxxabi/test/test_aux_runtime.pass.cpp | 2 +- libcxxabi/test/test_aux_runtime_op_array_new.pass.cpp | 2 +- libcxxabi/test/test_exception_address_alignment.pass.cpp | 2 +- libcxxabi/test/test_vector2.pass.cpp | 2 +- libcxxabi/test/test_vector3.pass.cpp | 2 +- libcxxabi/test/uncaught_exception.pass.cpp | 2 +- libcxxabi/test/uncaught_exceptions.pass.cpp | 2 +- libcxxabi/test/unwind_01.pass.cpp | 2 +- libcxxabi/test/unwind_02.pass.cpp | 2 +- libcxxabi/test/unwind_03.pass.cpp | 2 +- libcxxabi/test/unwind_04.pass.cpp | 2 +- libcxxabi/test/unwind_05.pass.cpp | 2 +- libcxxabi/test/unwind_06.pass.cpp | 2 +- libunwind/test/libunwind/test/config.py | 2 +- 142 files changed, 146 insertions(+), 143 deletions(-) diff --git a/libcxx/test/libcxx/algorithms/debug_less.pass.cpp b/libcxx/test/libcxx/algorithms/debug_less.pass.cpp index 6a05b8db67a8..6dd56955001d 100644 --- a/libcxx/test/libcxx/algorithms/debug_less.pass.cpp +++ b/libcxx/test/libcxx/algorithms/debug_less.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // diff --git a/libcxx/test/libcxx/containers/associative/map/at.abort.pass.cpp b/libcxx/test/libcxx/containers/associative/map/at.abort.pass.cpp index d4edbd752d20..36aa644abb59 100644 --- a/libcxx/test/libcxx/containers/associative/map/at.abort.pass.cpp +++ b/libcxx/test/libcxx/containers/associative/map/at.abort.pass.cpp @@ -15,7 +15,7 @@ // Make sure we abort() when exceptions are disabled and we fetch a key that // is not in the map. -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxx/test/libcxx/containers/associative/map/at.const.abort.pass.cpp b/libcxx/test/libcxx/containers/associative/map/at.const.abort.pass.cpp index 6860e3431498..f3dcca888f2b 100644 --- a/libcxx/test/libcxx/containers/associative/map/at.const.abort.pass.cpp +++ b/libcxx/test/libcxx/containers/associative/map/at.const.abort.pass.cpp @@ -15,7 +15,7 @@ // Make sure we abort() when exceptions are disabled and we fetch a key that // is not in the map. -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxx/test/libcxx/containers/sequences/vector/asan_throw.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector/asan_throw.pass.cpp index 235a3ffae14e..71d4f33366f3 100644 --- a/libcxx/test/libcxx/containers/sequences/vector/asan_throw.pass.cpp +++ b/libcxx/test/libcxx/containers/sequences/vector/asan_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // Test asan vector annotations with a class that throws in a CTOR. #include diff --git a/libcxx/test/libcxx/containers/unord/unord.map/at.abort.pass.cpp b/libcxx/test/libcxx/containers/unord/unord.map/at.abort.pass.cpp index 364d24e17295..fe2fb8cdffde 100644 --- a/libcxx/test/libcxx/containers/unord/unord.map/at.abort.pass.cpp +++ b/libcxx/test/libcxx/containers/unord/unord.map/at.abort.pass.cpp @@ -15,7 +15,7 @@ // Make sure we abort() when exceptions are disabled and we fetch a key that // is not in the map. -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions // UNSUPPORTED: c++98, c++03 #include diff --git a/libcxx/test/libcxx/containers/unord/unord.map/at.const.abort.pass.cpp b/libcxx/test/libcxx/containers/unord/unord.map/at.const.abort.pass.cpp index cc4cf2b37dc9..649ef7b98983 100644 --- a/libcxx/test/libcxx/containers/unord/unord.map/at.const.abort.pass.cpp +++ b/libcxx/test/libcxx/containers/unord/unord.map/at.const.abort.pass.cpp @@ -15,7 +15,7 @@ // Make sure we abort() when exceptions are disabled and we fetch a key that // is not in the map. -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions // UNSUPPORTED: c++98, c++03 #include diff --git a/libcxx/test/libcxx/input.output/iostreams.base/ios/iostate.flags/clear.abort.pass.cpp b/libcxx/test/libcxx/input.output/iostreams.base/ios/iostate.flags/clear.abort.pass.cpp index a302398feb7f..8f0f5a6d78b1 100644 --- a/libcxx/test/libcxx/input.output/iostreams.base/ios/iostate.flags/clear.abort.pass.cpp +++ b/libcxx/test/libcxx/input.output/iostreams.base/ios/iostate.flags/clear.abort.pass.cpp @@ -15,7 +15,7 @@ // Make sure that we abort() when exceptions are disabled and the exception // flag is set for the iostate we pass to clear(). -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxx/test/libcxx/localization/locales/locale.abort.pass.cpp b/libcxx/test/libcxx/localization/locales/locale.abort.pass.cpp index cff67c0573ae..9a47eb8f13c6 100644 --- a/libcxx/test/libcxx/localization/locales/locale.abort.pass.cpp +++ b/libcxx/test/libcxx/localization/locales/locale.abort.pass.cpp @@ -12,7 +12,7 @@ // explicit locale( const char* std_name ); -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions // Make sure we abort() when we construct a locale with a null name and // exceptions are disabled. diff --git a/libcxx/test/libcxx/localization/locales/locale.category.abort.pass.cpp b/libcxx/test/libcxx/localization/locales/locale.category.abort.pass.cpp index 60e5696dd546..9b321e6b1fd3 100644 --- a/libcxx/test/libcxx/localization/locales/locale.category.abort.pass.cpp +++ b/libcxx/test/libcxx/localization/locales/locale.category.abort.pass.cpp @@ -12,7 +12,7 @@ // locale(const locale& other, const char* std_name, category cat); -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions // Make sure we abort() when we construct a locale with a null name and // exceptions are disabled. diff --git a/libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp b/libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp index 0145e005ba04..9b4755a819cb 100644 --- a/libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp +++ b/libcxx/test/libcxx/localization/locales/use_facet.abort.pass.cpp @@ -10,7 +10,7 @@ // template const Facet& use_facet(const locale& loc); -// REQUIRES: libcpp-no-exceptions +// REQUIRES: no-exceptions // Make sure we abort() when we pass a facet not associated to the locale to // use_facet() and exceptions are disabled. diff --git a/libcxx/test/libcxx/strings/iterators.exceptions.pass.cpp b/libcxx/test/libcxx/strings/iterators.exceptions.pass.cpp index 471e6bea560d..d281cb206554 100644 --- a/libcxx/test/libcxx/strings/iterators.exceptions.pass.cpp +++ b/libcxx/test/libcxx/strings/iterators.exceptions.pass.cpp @@ -27,7 +27,7 @@ #ifndef TEST_HAS_NO_EXCEPTIONS static const bool expected = false; #else -// Under libcpp-no-exceptions all noexcept expressions are trivially true, so +// Under -fno-exceptions all noexcept expressions are trivially true, so // any check for a noexcept returning false must actually check for it being // true. static const bool expected = true; diff --git a/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_back_exception_safety.pass.cpp b/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_back_exception_safety.pass.cpp index 376f042e53b7..b24fd0753770 100644 --- a/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_back_exception_safety.pass.cpp +++ b/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_back_exception_safety.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void push_back(const value_type& x); diff --git a/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_front_exception_safety.pass.cpp b/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_front_exception_safety.pass.cpp index c43839780d2b..990f41f48726 100644 --- a/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_front_exception_safety.pass.cpp +++ b/libcxx/test/std/containers/sequences/deque/deque.modifiers/push_front_exception_safety.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void push_front(const value_type& x); diff --git a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.modifiers/push_front_exception_safety.pass.cpp b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.modifiers/push_front_exception_safety.pass.cpp index a1590abfea7b..1154447b04a9 100644 --- a/libcxx/test/std/containers/sequences/forwardlist/forwardlist.modifiers/push_front_exception_safety.pass.cpp +++ b/libcxx/test/std/containers/sequences/forwardlist/forwardlist.modifiers/push_front_exception_safety.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void push_front(const value_type& x); diff --git a/libcxx/test/std/containers/sequences/list/list.modifiers/push_back_exception_safety.pass.cpp b/libcxx/test/std/containers/sequences/list/list.modifiers/push_back_exception_safety.pass.cpp index e4595ef25127..8faf97a7dc4f 100644 --- a/libcxx/test/std/containers/sequences/list/list.modifiers/push_back_exception_safety.pass.cpp +++ b/libcxx/test/std/containers/sequences/list/list.modifiers/push_back_exception_safety.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void push_back(const value_type& x); diff --git a/libcxx/test/std/containers/sequences/list/list.modifiers/push_front_exception_safety.pass.cpp b/libcxx/test/std/containers/sequences/list/list.modifiers/push_front_exception_safety.pass.cpp index ebc9ac7f44be..aadeaaf13512 100644 --- a/libcxx/test/std/containers/sequences/list/list.modifiers/push_front_exception_safety.pass.cpp +++ b/libcxx/test/std/containers/sequences/list/list.modifiers/push_front_exception_safety.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void push_front(const value_type& x); diff --git a/libcxx/test/std/language.support/support.exception/except.nested/rethrow_if_nested.pass.cpp b/libcxx/test/std/language.support/support.exception/except.nested/rethrow_if_nested.pass.cpp index 01ef7ade7c2b..6c1ecf3a1fe9 100644 --- a/libcxx/test/std/language.support/support.exception/except.nested/rethrow_if_nested.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/except.nested/rethrow_if_nested.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // This test fails due to a stack overflow // XFAIL: LIBCXX-WINDOWS-FIXME diff --git a/libcxx/test/std/language.support/support.exception/except.nested/rethrow_nested.pass.cpp b/libcxx/test/std/language.support/support.exception/except.nested/rethrow_nested.pass.cpp index a3bf862f3f1c..1d9ff1e96c3a 100644 --- a/libcxx/test/std/language.support/support.exception/except.nested/rethrow_nested.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/except.nested/rethrow_nested.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // class nested_exception; diff --git a/libcxx/test/std/language.support/support.exception/except.nested/throw_with_nested.pass.cpp b/libcxx/test/std/language.support/support.exception/except.nested/throw_with_nested.pass.cpp index b63053c3304f..6a17d7a0ac0d 100644 --- a/libcxx/test/std/language.support/support.exception/except.nested/throw_with_nested.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/except.nested/throw_with_nested.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // class nested_exception; diff --git a/libcxx/test/std/language.support/support.exception/propagation/current_exception.pass.cpp b/libcxx/test/std/language.support/support.exception/propagation/current_exception.pass.cpp index de924016c4fc..8bad7f16f783 100644 --- a/libcxx/test/std/language.support/support.exception/propagation/current_exception.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/propagation/current_exception.pass.cpp @@ -10,7 +10,7 @@ // which copy the exception each time the exception_ptr is copied. // XFAIL: LIBCXX-WINDOWS-FIXME -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // exception_ptr current_exception(); diff --git a/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp b/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp index 8d7f6d0ead58..e97b15adc50a 100644 --- a/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/propagation/make_exception_ptr.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template exception_ptr make_exception_ptr(E e); diff --git a/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp b/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp index 49c30c3be10d..d109f98fbc21 100644 --- a/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/propagation/rethrow_exception.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // void rethrow_exception [[noreturn]] (exception_ptr p); diff --git a/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exception.pass.cpp b/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exception.pass.cpp index 004d525521d0..e368ce177b31 100644 --- a/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exception.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exception.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // test uncaught_exception #include diff --git a/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp b/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp index 6726706923ec..b7b5be774746 100644 --- a/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp +++ b/libcxx/test/std/language.support/support.exception/uncaught/uncaught_exceptions.pass.cpp @@ -6,8 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions -// XFAIL: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // std::uncaught_exceptions() was introduced in the dylib on Mac OS 10.12 // XFAIL: with_system_cxx_lib=macosx10.11 diff --git a/libcxx/test/std/re/re.alg/re.alg.match/exponential.pass.cpp b/libcxx/test/std/re/re.alg/re.alg.match/exponential.pass.cpp index a1ba80f26811..738bd25adc80 100644 --- a/libcxx/test/std/re/re.alg/re.alg.match/exponential.pass.cpp +++ b/libcxx/test/std/re/re.alg/re.alg.match/exponential.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: c++98, c++03 // template diff --git a/libcxx/test/std/re/re.alg/re.alg.replace/exponential.pass.cpp b/libcxx/test/std/re/re.alg/re.alg.replace/exponential.pass.cpp index 868c3d8350b3..316759fd895d 100644 --- a/libcxx/test/std/re/re.alg/re.alg.replace/exponential.pass.cpp +++ b/libcxx/test/std/re/re.alg/re.alg.replace/exponential.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // template diff --git a/libcxx/test/std/re/re.alg/re.alg.search/exponential.pass.cpp b/libcxx/test/std/re/re.alg/re.alg.search/exponential.pass.cpp index a9eb2b2b94e6..6825cb74806a 100644 --- a/libcxx/test/std/re/re.alg/re.alg.search/exponential.pass.cpp +++ b/libcxx/test/std/re/re.alg/re.alg.search/exponential.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: c++98, c++03 // template diff --git a/libcxx/test/std/re/re.grammar/excessive_brace_count.pass.cpp b/libcxx/test/std/re/re.grammar/excessive_brace_count.pass.cpp index a5f28d2eec0d..8b6f7add4993 100644 --- a/libcxx/test/std/re/re.grammar/excessive_brace_count.pass.cpp +++ b/libcxx/test/std/re/re.grammar/excessive_brace_count.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: c++98, c++03 // the "n" in `a{n}` should be within the numeric limits. diff --git a/libcxx/test/std/re/re.grammar/excessive_brace_min_max.pass.cpp b/libcxx/test/std/re/re.grammar/excessive_brace_min_max.pass.cpp index 09bedc5bd8e2..3954b256168e 100644 --- a/libcxx/test/std/re/re.grammar/excessive_brace_min_max.pass.cpp +++ b/libcxx/test/std/re/re.grammar/excessive_brace_min_max.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: c++98, c++03 // the "n" and "m" in `a{n,m}` should be within the numeric limits. diff --git a/libcxx/test/std/re/re.regex/re.regex.construct/bad_backref.pass.cpp b/libcxx/test/std/re/re.regex/re.regex.construct/bad_backref.pass.cpp index 08a14442e4e3..1021ebf84f4a 100644 --- a/libcxx/test/std/re/re.regex/re.regex.construct/bad_backref.pass.cpp +++ b/libcxx/test/std/re/re.regex/re.regex.construct/bad_backref.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template > class basic_regex; diff --git a/libcxx/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp b/libcxx/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp index 5752d5cd681c..31f6e9a711ba 100644 --- a/libcxx/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp +++ b/libcxx/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template > class basic_regex; diff --git a/libcxx/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp b/libcxx/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp index 041d55bdf88d..abb854e44f69 100644 --- a/libcxx/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp +++ b/libcxx/test/std/re/re.regex/re.regex.construct/bad_escape.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template > class basic_regex; diff --git a/libcxx/test/std/re/re.regex/re.regex.construct/bad_range.pass.cpp b/libcxx/test/std/re/re.regex/re.regex.construct/bad_range.pass.cpp index 590c10f94dff..023bc0ee79f4 100644 --- a/libcxx/test/std/re/re.regex/re.regex.construct/bad_range.pass.cpp +++ b/libcxx/test/std/re/re.regex/re.regex.construct/bad_range.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template > class basic_regex; diff --git a/libcxx/test/std/re/re.regex/re.regex.construct/bad_repeat.pass.cpp b/libcxx/test/std/re/re.regex/re.regex.construct/bad_repeat.pass.cpp index 1af8b5ba651d..b600ef70e176 100644 --- a/libcxx/test/std/re/re.regex/re.regex.construct/bad_repeat.pass.cpp +++ b/libcxx/test/std/re/re.regex/re.regex.construct/bad_repeat.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template > class basic_regex; diff --git a/libcxx/test/std/strings/basic.string/string.capacity/max_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/max_size.pass.cpp index 32f0be2775a1..d5bc1d50ca54 100644 --- a/libcxx/test/std/strings/basic.string/string.capacity/max_size.pass.cpp +++ b/libcxx/test/std/strings/basic.string/string.capacity/max_size.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // size_type max_size() const; diff --git a/libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp index df7c8731f249..9271f3ce283e 100644 --- a/libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp +++ b/libcxx/test/std/strings/basic.string/string.capacity/over_max_size.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // XFAIL: with_system_cxx_lib=macosx10.11 // XFAIL: with_system_cxx_lib=macosx10.10 // XFAIL: with_system_cxx_lib=macosx10.9 diff --git a/libcxx/test/std/thread/futures/futures.promise/set_exception.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_exception.pass.cpp index b634858d22db..bfd137416dc8 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_exception.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_exception.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // UNSUPPORTED: c++98, c++03 diff --git a/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp index dede79674031..4cd6fcc2022e 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // UNSUPPORTED: c++98, c++03 diff --git a/libcxx/test/std/thread/futures/futures.promise/set_rvalue.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_rvalue.pass.cpp index e5f7d53c8b24..d35b8613a622 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_rvalue.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_rvalue.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03 -// UNSUPPORTED: libcpp-has-no-threads, libcpp-no-exceptions +// UNSUPPORTED: libcpp-has-no-threads, no-exceptions // diff --git a/libcxx/test/std/thread/futures/futures.promise/set_value_void.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_value_void.pass.cpp index 16f1022b10c4..d3904f43cae9 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_value_void.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_value_void.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // UNSUPPORTED: c++98, c++03 diff --git a/libcxx/test/std/thread/futures/futures.shared_future/dtor.pass.cpp b/libcxx/test/std/thread/futures/futures.shared_future/dtor.pass.cpp index 6eef6150403e..f06c937be366 100644 --- a/libcxx/test/std/thread/futures/futures.shared_future/dtor.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.shared_future/dtor.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // UNSUPPORTED: c++98, c++03 diff --git a/libcxx/test/std/thread/futures/futures.unique_future/dtor.pass.cpp b/libcxx/test/std/thread/futures/futures.unique_future/dtor.pass.cpp index 2f09ffa02da5..0dd23c18c826 100644 --- a/libcxx/test/std/thread/futures/futures.unique_future/dtor.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.unique_future/dtor.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // UNSUPPORTED: c++98, c++03 diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp index 0ee02919f221..2d6e962f6dce 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: libcpp-has-no-threads // diff --git a/libcxx/test/std/utilities/any/any.class/any.assign/copy.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.assign/copy.pass.cpp index 7f44afec7fde..d56346e6d6e2 100644 --- a/libcxx/test/std/utilities/any/any.class/any.assign/copy.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.assign/copy.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.assign/move.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.assign/move.pass.cpp index 165cc0096034..db000ae4a689 100644 --- a/libcxx/test/std/utilities/any/any.class/any.assign/move.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.assign/move.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.assign/value.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.assign/value.pass.cpp index 5ac9b7985d5c..01bb7ecd2f94 100644 --- a/libcxx/test/std/utilities/any/any.class/any.assign/value.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.assign/value.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.cons/copy.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.cons/copy.pass.cpp index de2990189285..cfe4fc2ce4e9 100644 --- a/libcxx/test/std/utilities/any/any.class/any.cons/copy.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.cons/copy.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.cons/in_place_type.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.cons/in_place_type.pass.cpp index 329322d2d676..231f3d656403 100644 --- a/libcxx/test/std/utilities/any/any.class/any.cons/in_place_type.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.cons/in_place_type.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.cons/move.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.cons/move.pass.cpp index ac88e0f78df7..c6b520e9318d 100644 --- a/libcxx/test/std/utilities/any/any.class/any.cons/move.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.cons/move.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp index ecd3bd7616bd..4f46b0bec540 100644 --- a/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.modifiers/emplace.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.modifiers/emplace.pass.cpp index e2b232b08191..c7a75a059c95 100644 --- a/libcxx/test/std/utilities/any/any.class/any.modifiers/emplace.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.modifiers/emplace.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.modifiers/reset.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.modifiers/reset.pass.cpp index fd4dee2f2f33..b8ea8e89908f 100644 --- a/libcxx/test/std/utilities/any/any.class/any.modifiers/reset.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.modifiers/reset.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.class/any.modifiers/swap.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.modifiers/swap.pass.cpp index 9c85d3f6cf79..5889249fa40b 100644 --- a/libcxx/test/std/utilities/any/any.class/any.modifiers/swap.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.modifiers/swap.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp b/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp index d2cf58696f88..c507de3a32a4 100644 --- a/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp +++ b/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_pointer.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp b/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp index faaca948a612..8e5afaabea6d 100644 --- a/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp +++ b/libcxx/test/std/utilities/any/any.nonmembers/any.cast/any_cast_reference.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.nonmembers/make_any.pass.cpp b/libcxx/test/std/utilities/any/any.nonmembers/make_any.pass.cpp index 5e319efdab08..c0de5f1fa49f 100644 --- a/libcxx/test/std/utilities/any/any.nonmembers/make_any.pass.cpp +++ b/libcxx/test/std/utilities/any/any.nonmembers/make_any.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/any/any.nonmembers/swap.pass.cpp b/libcxx/test/std/utilities/any/any.nonmembers/swap.pass.cpp index 1e982235f4a2..5d3e8a457657 100644 --- a/libcxx/test/std/utilities/any/any.nonmembers/swap.pass.cpp +++ b/libcxx/test/std/utilities/any/any.nonmembers/swap.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_any_cast && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_any_cast && !no-exceptions // diff --git a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp index 7eb2a8a9bb61..48419174b661 100644 --- a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp +++ b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.size.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // allocator: diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator_throw.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator_throw.pass.cpp index 51eccc59b369..ce9c3e5875eb 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator_throw.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_allocator_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template shared_ptr(nullptr_t, D d, A a); diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_throw.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_throw.pass.cpp index 795717fbf234..8b028ccc8bee 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_throw.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/nullptr_t_deleter_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: sanitizer-new-delete // diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator_throw.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator_throw.pass.cpp index e39bda017a64..240fd358e063 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator_throw.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_allocator_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // // template shared_ptr(Y* p, D d, A a); diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_throw.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_throw.pass.cpp index 826862f66c74..d5577bf9b84f 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_throw.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_deleter_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: sanitizer-new-delete // diff --git a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_throw.pass.cpp b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_throw.pass.cpp index 6506890aa353..6a675e2f198d 100644 --- a/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_throw.pass.cpp +++ b/libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/pointer_throw.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: sanitizer-new-delete // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp index ce0b6e5878fa..3bf42378a199 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/U.pass.cpp @@ -8,7 +8,7 @@ // // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp index 018abd990336..c2fc54af504e 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/const_T.pass.cpp @@ -8,7 +8,7 @@ // // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp index fc2c46123f25..32923153477c 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/move.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp index 3d9e942af396..9f66f9d0d97d 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/rvalue_T.pass.cpp @@ -8,7 +8,7 @@ // // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value.pass.cpp index a37d0f34e65f..d8339a8fa24f 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const.pass.cpp index 4533208d6b39..72192f2ed49b 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const_rvalue.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const_rvalue.pass.cpp index 9719a1ebda7e..3ab8fb6700b5 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const_rvalue.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_const_rvalue.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_rvalue.pass.cpp b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_rvalue.pass.cpp index 215db7f1b9a1..2b3ccc8d23ff 100644 --- a/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_rvalue.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.object/optional.object.observe/value_rvalue.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 // -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // constexpr T& optional::value() &&; diff --git a/libcxx/test/std/utilities/optional/optional.specalg/make_optional.pass.cpp b/libcxx/test/std/utilities/optional/optional.specalg/make_optional.pass.cpp index f93913e5bd1c..477fa1d89f6f 100644 --- a/libcxx/test/std/utilities/optional/optional.specalg/make_optional.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.specalg/make_optional.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_optional_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_optional_access && !no-exceptions // // diff --git a/libcxx/test/std/utilities/variant/variant.get/get_index.pass.cpp b/libcxx/test/std/utilities/variant/variant.get/get_index.pass.cpp index 16e2f209ce8b..3706a5cf486c 100644 --- a/libcxx/test/std/utilities/variant/variant.get/get_index.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.get/get_index.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.get/get_type.pass.cpp b/libcxx/test/std/utilities/variant/variant.get/get_type.pass.cpp index 333f3d910383..d0a04aa88d40 100644 --- a/libcxx/test/std/utilities/variant/variant.get/get_type.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.get/get_type.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp index 3483298eda7a..125fe36792fa 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp index 4159020fbf55..e13e7b5a1864 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp index 1620a0239e9d..d76cfd4dcc12 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp index 0824761b0923..d86b2dac47ff 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp index 4cd210d3ddd7..701e79533609 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp index a26abf57ccef..0aa5169683f6 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_args.pass.cpp index f404c0ba726b..cd3ca7b3ef1a 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_init_list_args.pass.cpp index eb8c7daa2fad..d091ca706322 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_index_init_list_args.pass.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_args.pass.cpp index 9716d05f6786..4f056d77fe15 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_init_list_args.pass.cpp index 75baf15143a0..307df41baa53 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/in_place_type_init_list_args.pass.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp index d06b638e6904..a7ea9c29f924 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp index 47823b32e7f8..dc5279d5abe6 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp index 266045103232..14ee7a2900bf 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp index 8e68823d24ac..56cf444301ef 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp index 5910e50aef06..2a3b985148af 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp index 2c95dfeb35cc..cc8c8884d453 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // diff --git a/libcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp b/libcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp index 5a57164a2b60..2cc2766f59bd 100644 --- a/libcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.visit/visit.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++98, c++03, c++11, c++14 -// XFAIL: dylib-has-no-bad_variant_access && !libcpp-no-exceptions +// XFAIL: dylib-has-no-bad_variant_access && !no-exceptions // // template diff --git a/libcxx/test/support/test.support/test_macros_header_exceptions.pass.cpp b/libcxx/test/support/test.support/test_macros_header_exceptions.pass.cpp index ccdf257dceb4..eb474d6d25c0 100644 --- a/libcxx/test/support/test.support/test_macros_header_exceptions.pass.cpp +++ b/libcxx/test/support/test.support/test_macros_header_exceptions.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcpp-no-exceptions +// UNSUPPORTED: no-exceptions // "support/test_macros.hpp" diff --git a/libcxx/utils/libcxx/test/config.py b/libcxx/utils/libcxx/test/config.py index 6fbe2ba29fee..225dadb5f02d 100644 --- a/libcxx/utils/libcxx/test/config.py +++ b/libcxx/utils/libcxx/test/config.py @@ -650,7 +650,7 @@ class Configuration(object): def configure_compile_flags_exceptions(self): enable_exceptions = self.get_lit_bool('enable_exceptions', True) if not enable_exceptions: - self.config.available_features.add('libcpp-no-exceptions') + self.config.available_features.add('no-exceptions') self.cxx.compile_flags += ['-fno-exceptions'] def configure_compile_flags_rtti(self): diff --git a/libcxxabi/test/backtrace_test.pass.cpp b/libcxxabi/test/backtrace_test.pass.cpp index b6ed9b208ec8..38125f8cf6e9 100644 --- a/libcxxabi/test/backtrace_test.pass.cpp +++ b/libcxxabi/test/backtrace_test.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_array_01.pass.cpp b/libcxxabi/test/catch_array_01.pass.cpp index 03288e7da47a..f8bd4b1ae18b 100644 --- a/libcxxabi/test/catch_array_01.pass.cpp +++ b/libcxxabi/test/catch_array_01.pass.cpp @@ -11,7 +11,7 @@ // GCC incorrectly allows array types to be caught by reference. // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69372 // XFAIL: gcc -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_array_02.pass.cpp b/libcxxabi/test/catch_array_02.pass.cpp index f6228a08a56e..69cd8d50df54 100644 --- a/libcxxabi/test/catch_array_02.pass.cpp +++ b/libcxxabi/test/catch_array_02.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // Can you have a catch clause of array type that catches anything? -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_class_01.pass.cpp b/libcxxabi/test/catch_class_01.pass.cpp index 0a7b5eafbda6..274584083d68 100644 --- a/libcxxabi/test/catch_class_01.pass.cpp +++ b/libcxxabi/test/catch_class_01.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_class_02.pass.cpp b/libcxxabi/test/catch_class_02.pass.cpp index c41572135abd..f78b581581a0 100644 --- a/libcxxabi/test/catch_class_02.pass.cpp +++ b/libcxxabi/test/catch_class_02.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_class_03.pass.cpp b/libcxxabi/test/catch_class_03.pass.cpp index cbc3c32245de..450c13c688a0 100644 --- a/libcxxabi/test/catch_class_03.pass.cpp +++ b/libcxxabi/test/catch_class_03.pass.cpp @@ -12,7 +12,7 @@ check against. */ -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_class_04.pass.cpp b/libcxxabi/test/catch_class_04.pass.cpp index c439f795fd16..a9656ec35fb6 100644 --- a/libcxxabi/test/catch_class_04.pass.cpp +++ b/libcxxabi/test/catch_class_04.pass.cpp @@ -12,7 +12,7 @@ check against. It also checks that virtual bases work properly */ -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_const_pointer_nullptr.pass.cpp b/libcxxabi/test/catch_const_pointer_nullptr.pass.cpp index 44caef594ec5..b910545c909f 100644 --- a/libcxxabi/test/catch_const_pointer_nullptr.pass.cpp +++ b/libcxxabi/test/catch_const_pointer_nullptr.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_function_01.pass.cpp b/libcxxabi/test/catch_function_01.pass.cpp index bf962a994b47..ca52c9e7b1ef 100644 --- a/libcxxabi/test/catch_function_01.pass.cpp +++ b/libcxxabi/test/catch_function_01.pass.cpp @@ -11,7 +11,7 @@ // GCC incorrectly allows function pointer to be caught by reference. // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69372 // XFAIL: gcc -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_function_02.pass.cpp b/libcxxabi/test/catch_function_02.pass.cpp index f746d92d26db..195771121883 100644 --- a/libcxxabi/test/catch_function_02.pass.cpp +++ b/libcxxabi/test/catch_function_02.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // Can you have a catch clause of array type that catches anything? -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_function_03.pass.cpp b/libcxxabi/test/catch_function_03.pass.cpp index dbc72c722c1e..217500e700ec 100644 --- a/libcxxabi/test/catch_function_03.pass.cpp +++ b/libcxxabi/test/catch_function_03.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // Can a noexcept function pointer be caught by a non-noexcept catch clause? -// UNSUPPORTED: libcxxabi-no-exceptions, libcxxabi-no-noexcept-function-type +// UNSUPPORTED: no-exceptions, libcxxabi-no-noexcept-function-type #include diff --git a/libcxxabi/test/catch_in_noexcept.pass.cpp b/libcxxabi/test/catch_in_noexcept.pass.cpp index 94af4dfb3d7e..8f0ade78e6d6 100644 --- a/libcxxabi/test/catch_in_noexcept.pass.cpp +++ b/libcxxabi/test/catch_in_noexcept.pass.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: c++98, c++03, libcxxabi-no-exceptions +// UNSUPPORTED: c++98, c++03 +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_member_data_pointer_01.pass.cpp b/libcxxabi/test/catch_member_data_pointer_01.pass.cpp index 6536515a30be..765395968373 100644 --- a/libcxxabi/test/catch_member_data_pointer_01.pass.cpp +++ b/libcxxabi/test/catch_member_data_pointer_01.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_member_function_pointer_01.pass.cpp b/libcxxabi/test/catch_member_function_pointer_01.pass.cpp index 3dc21dfc563c..f1d4e8d795b1 100644 --- a/libcxxabi/test/catch_member_function_pointer_01.pass.cpp +++ b/libcxxabi/test/catch_member_function_pointer_01.pass.cpp @@ -9,7 +9,7 @@ // GCC incorrectly allows PMF type "void (T::*)()" to be caught as "void (T::*)() const" // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69375 // XFAIL: gcc -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include struct A diff --git a/libcxxabi/test/catch_member_function_pointer_02.pass.cpp b/libcxxabi/test/catch_member_function_pointer_02.pass.cpp index 41356e5daa7c..c38a9306c41c 100644 --- a/libcxxabi/test/catch_member_function_pointer_02.pass.cpp +++ b/libcxxabi/test/catch_member_function_pointer_02.pass.cpp @@ -8,7 +8,7 @@ // Can a noexcept member function pointer be caught by a non-noexcept catch // clause? -// UNSUPPORTED: libcxxabi-no-exceptions, libcxxabi-no-noexcept-function-type +// UNSUPPORTED: no-exceptions, libcxxabi-no-noexcept-function-type // GCC 7 and 8 support noexcept function types but this test still fails. // This is likely a bug in their implementation. Investigation needed. diff --git a/libcxxabi/test/catch_member_pointer_nullptr.pass.cpp b/libcxxabi/test/catch_member_pointer_nullptr.pass.cpp index a6e746876920..54d4fd2af7da 100644 --- a/libcxxabi/test/catch_member_pointer_nullptr.pass.cpp +++ b/libcxxabi/test/catch_member_pointer_nullptr.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_multi_level_pointer.pass.cpp b/libcxxabi/test/catch_multi_level_pointer.pass.cpp index fcd6ecd247cb..be5a1105d5f5 100644 --- a/libcxxabi/test/catch_multi_level_pointer.pass.cpp +++ b/libcxxabi/test/catch_multi_level_pointer.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_pointer_nullptr.pass.cpp b/libcxxabi/test/catch_pointer_nullptr.pass.cpp index bd1db8cb48d8..c093d52cc66a 100644 --- a/libcxxabi/test/catch_pointer_nullptr.pass.cpp +++ b/libcxxabi/test/catch_pointer_nullptr.pass.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: c++98, c++03, libcxxabi-no-exceptions +// UNSUPPORTED: c++98, c++03 +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_pointer_reference.pass.cpp b/libcxxabi/test/catch_pointer_reference.pass.cpp index eff950f1ee13..6ea0cae5d669 100644 --- a/libcxxabi/test/catch_pointer_reference.pass.cpp +++ b/libcxxabi/test/catch_pointer_reference.pass.cpp @@ -24,7 +24,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_ptr.pass.cpp b/libcxxabi/test/catch_ptr.pass.cpp index 0255b7fd48c6..b2d8999120a6 100644 --- a/libcxxabi/test/catch_ptr.pass.cpp +++ b/libcxxabi/test/catch_ptr.pass.cpp @@ -12,7 +12,7 @@ check against. It also checks that virtual bases work properly */ -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/catch_ptr_02.pass.cpp b/libcxxabi/test/catch_ptr_02.pass.cpp index 9c24e11df54e..d20076d22a6e 100644 --- a/libcxxabi/test/catch_ptr_02.pass.cpp +++ b/libcxxabi/test/catch_ptr_02.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/catch_reference_nullptr.pass.cpp b/libcxxabi/test/catch_reference_nullptr.pass.cpp index 0d7ac96e2f4c..a15eb3c719a6 100644 --- a/libcxxabi/test/catch_reference_nullptr.pass.cpp +++ b/libcxxabi/test/catch_reference_nullptr.pass.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: c++98, c++03, libcxxabi-no-exceptions +// UNSUPPORTED: c++98, c++03, +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp b/libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp index 67b060e5de3e..84ba978f9dc1 100644 --- a/libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp +++ b/libcxxabi/test/cxa_vec_new_overflow_PR41395.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include "cxxabi.h" #include diff --git a/libcxxabi/test/exception_object_alignment.2.pass.cpp b/libcxxabi/test/exception_object_alignment.2.pass.cpp index 33f0f9e5825a..b35e72862991 100644 --- a/libcxxabi/test/exception_object_alignment.2.pass.cpp +++ b/libcxxabi/test/exception_object_alignment.2.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // This test checks that the compiler does not make incorrect assumptions // about the alignment of the exception (only in that specific case, of diff --git a/libcxxabi/test/exception_object_alignment.pass.cpp b/libcxxabi/test/exception_object_alignment.pass.cpp index a22523d7ac96..df9f37b2e133 100644 --- a/libcxxabi/test/exception_object_alignment.pass.cpp +++ b/libcxxabi/test/exception_object_alignment.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // Check that the pointer __cxa_allocate_exception returns is aligned to the // default alignment for the target architecture. diff --git a/libcxxabi/test/guard_threaded_test.pass.cpp b/libcxxabi/test/guard_threaded_test.pass.cpp index 32c66f4c0cca..89221f105f71 100644 --- a/libcxxabi/test/guard_threaded_test.pass.cpp +++ b/libcxxabi/test/guard_threaded_test.pass.cpp @@ -7,7 +7,8 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03 -// UNSUPPORTED: libcxxabi-no-threads, libcxxabi-no-exceptions +// UNSUPPORTED: libcxxabi-no-threads +// UNSUPPORTED: no-exceptions #define TESTING_CXA_GUARD #include "../src/cxa_guard_impl.h" diff --git a/libcxxabi/test/incomplete_type.sh.cpp b/libcxxabi/test/incomplete_type.sh.cpp index a762d2f9c60e..999c172dd5b5 100644 --- a/libcxxabi/test/incomplete_type.sh.cpp +++ b/libcxxabi/test/incomplete_type.sh.cpp @@ -13,7 +13,7 @@ // incomplete flags set, equality can be tested by comparing the type_info // addresses. -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // NOTE: Link libc++abi explicitly and before libc++ so that libc++ doesn't drag // in the system libc++abi installation on OS X. (DYLD_LIBRARY_PATH is ignored diff --git a/libcxxabi/test/inherited_exception.pass.cpp b/libcxxabi/test/inherited_exception.pass.cpp index 784637621697..ac92ab4dc6c2 100644 --- a/libcxxabi/test/inherited_exception.pass.cpp +++ b/libcxxabi/test/inherited_exception.pass.cpp @@ -24,7 +24,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // Clang emits warnings about exceptions of type 'Child' being caught by // an earlier handler of type 'Base'. Congrats clang, you've just diff --git a/libcxxabi/test/libcxxabi/test/config.py b/libcxxabi/test/libcxxabi/test/config.py index 5f652c2f00c0..fe76d193e79e 100644 --- a/libcxxabi/test/libcxxabi/test/config.py +++ b/libcxxabi/test/libcxxabi/test/config.py @@ -39,7 +39,7 @@ class Configuration(LibcxxConfiguration): def configure_features(self): super(Configuration, self).configure_features() if not self.get_lit_bool('enable_exceptions', True): - self.config.available_features.add('libcxxabi-no-exceptions') + self.config.available_features.add('no-exceptions') if not self.has_cpp_feature('noexcept_function_type', 201510): self.config.available_features.add('libcxxabi-no-noexcept-function-type') if not self.get_lit_bool('llvm_unwinder', False): diff --git a/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-00.pass.sh.s b/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-00.pass.sh.s index 49166dad846c..f8a80e8e1824 100644 --- a/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-00.pass.sh.s +++ b/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-00.pass.sh.s @@ -1,6 +1,6 @@ @ RUN: %{cxx} %{flags} %{link_flags} %s -o %t.exe @ RUN: %t.exe -@ UNSUPPORTED: libcxxabi-no-exceptions +@ UNSUPPORTED: no-exceptions @ PURPOSE: Check that 0x00 is a valid value for ttype encoding. LLVM and @ GCC 4.6 are generating 0x00 as ttype encoding. libc++abi should provide diff --git a/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-90.pass.sh.s b/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-90.pass.sh.s index 40139bbd87bc..0d8bdee9b85e 100644 --- a/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-90.pass.sh.s +++ b/libcxxabi/test/native/arm-linux-eabi/ttype-encoding-90.pass.sh.s @@ -1,6 +1,6 @@ @ RUN: %{cxx} %{flags} %{link_flags} %s -o %t.exe @ RUN: %t.exe -@ UNSUPPORTED: libcxxabi-no-exceptions +@ UNSUPPORTED: no-exceptions @ PURPOSE: Check that 0x90 is a valid value for ttype encoding. diff --git a/libcxxabi/test/noexception1.pass.cpp b/libcxxabi/test/noexception1.pass.cpp index b3471dd23fe9..129bc93d58f4 100644 --- a/libcxxabi/test/noexception1.pass.cpp +++ b/libcxxabi/test/noexception1.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03 -// REQUIRES: libcxxabi-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxxabi/test/noexception2.pass.cpp b/libcxxabi/test/noexception2.pass.cpp index b377d9ec6b58..f2851ebba4de 100644 --- a/libcxxabi/test/noexception2.pass.cpp +++ b/libcxxabi/test/noexception2.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03 -// REQUIRES: libcxxabi-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxxabi/test/noexception3.pass.cpp b/libcxxabi/test/noexception3.pass.cpp index 42d02a61569f..005dba032861 100644 --- a/libcxxabi/test/noexception3.pass.cpp +++ b/libcxxabi/test/noexception3.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++98, c++03 -// REQUIRES: libcxxabi-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxxabi/test/noexception4.pass.cpp b/libcxxabi/test/noexception4.pass.cpp index 00c71621f45f..a1349ee91876 100644 --- a/libcxxabi/test/noexception4.pass.cpp +++ b/libcxxabi/test/noexception4.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// REQUIRES: libcxxabi-no-exceptions +// REQUIRES: no-exceptions #include #include diff --git a/libcxxabi/test/test_aux_runtime.pass.cpp b/libcxxabi/test/test_aux_runtime.pass.cpp index 4f0c1748f96a..585fd7dcbc67 100644 --- a/libcxxabi/test/test_aux_runtime.pass.cpp +++ b/libcxxabi/test/test_aux_runtime.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/test_aux_runtime_op_array_new.pass.cpp b/libcxxabi/test/test_aux_runtime_op_array_new.pass.cpp index 3e77d99b0621..928e32459223 100644 --- a/libcxxabi/test/test_aux_runtime_op_array_new.pass.cpp +++ b/libcxxabi/test/test_aux_runtime_op_array_new.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/test_exception_address_alignment.pass.cpp b/libcxxabi/test/test_exception_address_alignment.pass.cpp index 16a896fe2f02..c0dab000574e 100644 --- a/libcxxabi/test/test_exception_address_alignment.pass.cpp +++ b/libcxxabi/test/test_exception_address_alignment.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // UNSUPPORTED: c++98, c++03 // The system unwind.h on OS X provides an incorrectly aligned _Unwind_Exception diff --git a/libcxxabi/test/test_vector2.pass.cpp b/libcxxabi/test/test_vector2.pass.cpp index f923aa4ff215..21b5e860e143 100644 --- a/libcxxabi/test/test_vector2.pass.cpp +++ b/libcxxabi/test/test_vector2.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include "cxxabi.h" diff --git a/libcxxabi/test/test_vector3.pass.cpp b/libcxxabi/test/test_vector3.pass.cpp index 4068b7fc9dfe..9b7e671d26c0 100644 --- a/libcxxabi/test/test_vector3.pass.cpp +++ b/libcxxabi/test/test_vector3.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include "cxxabi.h" diff --git a/libcxxabi/test/uncaught_exception.pass.cpp b/libcxxabi/test/uncaught_exception.pass.cpp index 626f4cba1154..6a04c7179512 100644 --- a/libcxxabi/test/uncaught_exception.pass.cpp +++ b/libcxxabi/test/uncaught_exception.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // This tests that libc++abi still provides __cxa_uncaught_exception() for // ABI compatibility, even though the Standard doesn't require it to. diff --git a/libcxxabi/test/uncaught_exceptions.pass.cpp b/libcxxabi/test/uncaught_exceptions.pass.cpp index f4b2d3651002..3474e0c3c514 100644 --- a/libcxxabi/test/uncaught_exceptions.pass.cpp +++ b/libcxxabi/test/uncaught_exceptions.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libcxxabi/test/unwind_01.pass.cpp b/libcxxabi/test/unwind_01.pass.cpp index 97e10eb56f21..f71596127bf2 100644 --- a/libcxxabi/test/unwind_01.pass.cpp +++ b/libcxxabi/test/unwind_01.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include diff --git a/libcxxabi/test/unwind_02.pass.cpp b/libcxxabi/test/unwind_02.pass.cpp index e7a8479f9b63..99a481746b6a 100644 --- a/libcxxabi/test/unwind_02.pass.cpp +++ b/libcxxabi/test/unwind_02.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // REQUIRES: c++98 || c++03 || c++11 || c++14 #include diff --git a/libcxxabi/test/unwind_03.pass.cpp b/libcxxabi/test/unwind_03.pass.cpp index 38962c6c3f86..5016a5fc2a6a 100644 --- a/libcxxabi/test/unwind_03.pass.cpp +++ b/libcxxabi/test/unwind_03.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // REQUIRES: c++98 || c++03 || c++11 || c++14 #include diff --git a/libcxxabi/test/unwind_04.pass.cpp b/libcxxabi/test/unwind_04.pass.cpp index 45669c354b3f..7e10e8a9e216 100644 --- a/libcxxabi/test/unwind_04.pass.cpp +++ b/libcxxabi/test/unwind_04.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // REQUIRES: c++98 || c++03 || c++11 || c++14 #include diff --git a/libcxxabi/test/unwind_05.pass.cpp b/libcxxabi/test/unwind_05.pass.cpp index efd724a83a6d..8c6db8898485 100644 --- a/libcxxabi/test/unwind_05.pass.cpp +++ b/libcxxabi/test/unwind_05.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions // REQUIRES: c++98 || c++03 || c++11 || c++14 #include diff --git a/libcxxabi/test/unwind_06.pass.cpp b/libcxxabi/test/unwind_06.pass.cpp index a305d3d03fa2..1bcb89c1cab0 100644 --- a/libcxxabi/test/unwind_06.pass.cpp +++ b/libcxxabi/test/unwind_06.pass.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// UNSUPPORTED: libcxxabi-no-exceptions +// UNSUPPORTED: no-exceptions #include #include diff --git a/libunwind/test/libunwind/test/config.py b/libunwind/test/libunwind/test/config.py index 41ca3f9b4a44..36501f230272 100644 --- a/libunwind/test/libunwind/test/config.py +++ b/libunwind/test/libunwind/test/config.py @@ -36,7 +36,7 @@ class Configuration(LibcxxConfiguration): def configure_features(self): super(Configuration, self).configure_features() if not self.get_lit_bool('enable_exceptions', True): - self.config.available_features.add('libcxxabi-no-exceptions') + self.config.available_features.add('no-exceptions') if self.get_lit_bool('arm_ehabi', False): self.config.available_features.add('libunwind-arm-ehabi') -- GitLab From bffd45bab199cbe6021927ca4ab56e944eff5381 Mon Sep 17 00:00:00 2001 From: Sebastian Neubauer Date: Wed, 22 Apr 2020 14:01:38 +0200 Subject: [PATCH 073/910] [NFC][AMDGPU] Fix cmake when LLVM is a subproject CMAKE_SOURCE_DIR is not the right directory if llvm is included in another cmake project. PROJECT_SOURCE_DIR is always the same and should be used instead. --- llvm/unittests/Target/AMDGPU/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/Target/AMDGPU/CMakeLists.txt b/llvm/unittests/Target/AMDGPU/CMakeLists.txt index ba6b92f378a6..7b4548a0b678 100644 --- a/llvm/unittests/Target/AMDGPU/CMakeLists.txt +++ b/llvm/unittests/Target/AMDGPU/CMakeLists.txt @@ -1,6 +1,6 @@ include_directories( - ${CMAKE_SOURCE_DIR}/lib/Target/AMDGPU - ${CMAKE_BINARY_DIR}/lib/Target/AMDGPU + ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU + ${PROJECT_BINARY_DIR}/lib/Target/AMDGPU ) set(LLVM_LINK_COMPONENTS -- GitLab From 48ac4e6938351b19a15a5666349693cec91968b5 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 22 Apr 2020 12:40:45 +0100 Subject: [PATCH 074/910] [ARM] MVE FMA loop tests. NFC --- llvm/test/CodeGen/Thumb2/mve-fma-loops.ll | 869 ++++++++++++++++++++++ 1 file changed, 869 insertions(+) create mode 100644 llvm/test/CodeGen/Thumb2/mve-fma-loops.ll diff --git a/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll new file mode 100644 index 000000000000..9438a0d39033 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll @@ -0,0 +1,869 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false %s -o - | FileCheck %s + +define arm_aapcs_vfpcc void @fmas1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmas1: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB0_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: adr r4, .LCPI0_0 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: sub.w r12, r3, #1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: vdup.32 q2, r12 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB0_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vmov q5, q0 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r1], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r0], #16 +; CHECK-NEXT: vfma.f32 q5, q4, q3 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q5, [r2], #16 +; CHECK-NEXT: le lr, .LBB0_2 +; CHECK-NEXT: .LBB0_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop {r4, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI0_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %wide.masked.load12, <4 x float> %broadcast.splat14) + %6 = getelementptr inbounds float, float* %z, i32 %index + %7 = bitcast float* %6 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %8 = icmp eq i32 %index.next, %n.vec + br i1 %8, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fmas2(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmas2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: .LBB1_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vldrw.u32 q1, [r1], #16 +; CHECK-NEXT: vfmas.f32 q1, q0, r12 +; CHECK-NEXT: vstrw.32 q1, [r2], #16 +; CHECK-NEXT: letp lr, .LBB1_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fmul fast <4 x float> %wide.masked.load12, %wide.masked.load + %6 = fadd fast <4 x float> %5, %broadcast.splat14 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fma1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fma1: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB2_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: adr r4, .LCPI2_0 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: sub.w r12, r3, #1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: vdup.32 q2, r12 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB2_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r0], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r1], #16 +; CHECK-NEXT: vfma.f32 q4, q3, q0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q4, [r2], #16 +; CHECK-NEXT: le lr, .LBB2_2 +; CHECK-NEXT: .LBB2_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: pop {r4, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI2_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %broadcast.splat14, <4 x float> %wide.masked.load12) + %6 = getelementptr inbounds float, float* %z, i32 %index + %7 = bitcast float* %6 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %8 = icmp eq i32 %index.next, %n.vec + br i1 %8, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fma2(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fma2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: .LBB3_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vldrw.u32 q1, [r1], #16 +; CHECK-NEXT: vfma.f32 q1, q0, r12 +; CHECK-NEXT: vstrw.32 q1, [r2], #16 +; CHECK-NEXT: letp lr, .LBB3_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert12 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat13 = shufflevector <4 x float> %broadcast.splatinsert12, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = fmul fast <4 x float> %wide.masked.load, %broadcast.splat13 + %4 = getelementptr inbounds float, float* %y, i32 %index + %5 = bitcast float* %4 to <4 x float>* + %wide.masked.load14 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %5, i32 4, <4 x i1> %1, <4 x float> undef) + %6 = fadd fast <4 x float> %3, %wide.masked.load14 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fmss1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmss1: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, r5, r7, lr} +; CHECK-NEXT: push {r4, r5, r7, lr} +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB4_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: adr r4, .LCPI4_0 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: subs r5, r3, #1 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: vdup.32 q2, r5 +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: eor r3, r12, #-2147483648 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: .LBB4_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vmov q5, q0 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r1], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r0], #16 +; CHECK-NEXT: vfma.f32 q5, q4, q3 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q5, [r2], #16 +; CHECK-NEXT: le lr, .LBB4_2 +; CHECK-NEXT: .LBB4_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI4_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %fneg = fneg fast float %a + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %fneg, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %wide.masked.load12, <4 x float> %broadcast.splat14) + %6 = getelementptr inbounds float, float* %z, i32 %index + %7 = bitcast float* %6 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %8 = icmp eq i32 %index.next, %n.vec + br i1 %8, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fmss2(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmss2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vdup.32 q0, r12 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: vneg.f32 q0, q0 +; CHECK-NEXT: .LBB5_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vmov q3, q0 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vfma.f32 q3, q2, q1 +; CHECK-NEXT: vstrw.32 q3, [r2], #16 +; CHECK-NEXT: letp lr, .LBB5_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fmul fast <4 x float> %wide.masked.load12, %wide.masked.load + %6 = fsub fast <4 x float> %5, %broadcast.splat14 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fmss3(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmss3: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB6_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: adr r4, .LCPI6_0 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: sub.w r12, r3, #1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: vdup.32 q2, r12 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB6_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vmov q5, q0 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r1], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r0], #16 +; CHECK-NEXT: vfms.f32 q5, q4, q3 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q5, [r2], #16 +; CHECK-NEXT: le lr, .LBB6_2 +; CHECK-NEXT: .LBB6_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop {r4, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI6_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fneg fast <4 x float> %wide.masked.load12 + %6 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %5, <4 x float> %broadcast.splat14) + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fmss4(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fmss4: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vdup.32 q0, r12 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: .LBB7_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vmov q3, q0 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vfms.f32 q3, q2, q1 +; CHECK-NEXT: vstrw.32 q3, [r2], #16 +; CHECK-NEXT: letp lr, .LBB7_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fmul fast <4 x float> %wide.masked.load12, %wide.masked.load + %6 = fsub fast <4 x float> %broadcast.splat14, %5 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fms1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fms1: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, r5, r7, lr} +; CHECK-NEXT: push {r4, r5, r7, lr} +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB8_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: adr r4, .LCPI8_0 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: subs r5, r3, #1 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: vdup.32 q2, r5 +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: eor r3, r12, #-2147483648 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: .LBB8_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r0], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r1], #16 +; CHECK-NEXT: vfma.f32 q4, q3, q0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q4, [r2], #16 +; CHECK-NEXT: le lr, .LBB8_2 +; CHECK-NEXT: .LBB8_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI8_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %fneg = fneg fast float %a + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %fneg, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %broadcast.splat14, <4 x float> %wide.masked.load12) + %6 = getelementptr inbounds float, float* %z, i32 %index + %7 = bitcast float* %6 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %5, <4 x float>* %7, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %8 = icmp eq i32 %index.next, %n.vec + br i1 %8, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fms2(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fms2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: vdup.32 q0, r12 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: .LBB9_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vfms.f32 q2, q1, q0 +; CHECK-NEXT: vstrw.32 q2, [r2], #16 +; CHECK-NEXT: letp lr, .LBB9_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fmul fast <4 x float> %wide.masked.load, %broadcast.splat14 + %6 = fsub fast <4 x float> %wide.masked.load12, %5 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fms3(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fms3: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: blt .LBB10_3 +; CHECK-NEXT: @ %bb.1: @ %vector.ph +; CHECK-NEXT: add.w r12, r3, #3 +; CHECK-NEXT: adr r4, .LCPI10_0 +; CHECK-NEXT: bic r12, r12, #3 +; CHECK-NEXT: mov.w lr, #1 +; CHECK-NEXT: sub.w r12, r12, #4 +; CHECK-NEXT: vldrw.u32 q1, [r4] +; CHECK-NEXT: add.w lr, lr, r12, lsr #2 +; CHECK-NEXT: sub.w r12, r3, #1 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: vdup.32 q2, r12 +; CHECK-NEXT: vdup.32 q0, r3 +; CHECK-NEXT: movs r3, #0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB10_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vdup.32 q3, r3 +; CHECK-NEXT: adds r3, #4 +; CHECK-NEXT: vorr q3, q3, q1 +; CHECK-NEXT: vptt.u32 cs, q2, q3 +; CHECK-NEXT: vldrwt.u32 q3, [r1], #16 +; CHECK-NEXT: vldrwt.u32 q4, [r0], #16 +; CHECK-NEXT: vneg.f32 q3, q3 +; CHECK-NEXT: vfma.f32 q3, q4, q0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vstrwt.32 q3, [r2], #16 +; CHECK-NEXT: le lr, .LBB10_2 +; CHECK-NEXT: .LBB10_3: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: pop {r4, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI10_0: +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 2 @ 0x2 +; CHECK-NEXT: .long 3 @ 0x3 +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert13 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat14 = shufflevector <4 x float> %broadcast.splatinsert13, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = getelementptr inbounds float, float* %y, i32 %index + %4 = bitcast float* %3 to <4 x float>* + %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %4, i32 4, <4 x i1> %1, <4 x float> undef) + %5 = fneg fast <4 x float> %wide.masked.load12 + %6 = call fast <4 x float> @llvm.fma.v4f32(<4 x float> %wide.masked.load, <4 x float> %broadcast.splat14, <4 x float> %5) + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +define arm_aapcs_vfpcc void @fms4(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { +; CHECK-LABEL: fms4: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: cmp r3, #1 +; CHECK-NEXT: it lt +; CHECK-NEXT: poplt {r7, pc} +; CHECK-NEXT: vmov r12, s0 +; CHECK-NEXT: dlstp.32 lr, r3 +; CHECK-NEXT: .LBB11_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q0, [r1], #16 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vneg.f32 q0, q0 +; CHECK-NEXT: vfma.f32 q0, q1, r12 +; CHECK-NEXT: vstrw.32 q0, [r2], #16 +; CHECK-NEXT: letp lr, .LBB11_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + %cmp8 = icmp sgt i32 %n, 0 + br i1 %cmp8, label %vector.ph, label %for.cond.cleanup + +vector.ph: ; preds = %entry + %n.rnd.up = add i32 %n, 3 + %n.vec = and i32 %n.rnd.up, -4 + %trip.count.minus.1 = add i32 %n, -1 + %broadcast.splatinsert10 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 + %broadcast.splat11 = shufflevector <4 x i32> %broadcast.splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer + %broadcast.splatinsert12 = insertelement <4 x float> undef, float %a, i32 0 + %broadcast.splat13 = shufflevector <4 x float> %broadcast.splatinsert12, <4 x float> undef, <4 x i32> zeroinitializer + br label %vector.body + +vector.body: ; preds = %vector.body, %vector.ph + %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] + %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 + %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer + %induction = or <4 x i32> %broadcast.splat, + %0 = getelementptr inbounds float, float* %x, i32 %index + %1 = icmp ule <4 x i32> %induction, %broadcast.splat11 + %2 = bitcast float* %0 to <4 x float>* + %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %2, i32 4, <4 x i1> %1, <4 x float> undef) + %3 = fmul fast <4 x float> %wide.masked.load, %broadcast.splat13 + %4 = getelementptr inbounds float, float* %y, i32 %index + %5 = bitcast float* %4 to <4 x float>* + %wide.masked.load14 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %5, i32 4, <4 x i1> %1, <4 x float> undef) + %6 = fsub fast <4 x float> %3, %wide.masked.load14 + %7 = getelementptr inbounds float, float* %z, i32 %index + %8 = bitcast float* %7 to <4 x float>* + call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %6, <4 x float>* %8, i32 4, <4 x i1> %1) + %index.next = add i32 %index, 4 + %9 = icmp eq i32 %index.next, %n.vec + br i1 %9, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) +declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) +declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) -- GitLab From 6f19f0fb9a2f247cd37eee98474d9c441298463d Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 22 Apr 2020 08:42:44 -0400 Subject: [PATCH 075/910] [InstCombine] add tests for min/max FP intrinsics with FMF (PR45478); NFC https://bugs.llvm.org/show_bug.cgi?id=45478 --- llvm/test/Transforms/InstCombine/maximum.ll | 58 +++++++++++++++------ llvm/test/Transforms/InstCombine/maxnum.ll | 26 +++++++-- llvm/test/Transforms/InstCombine/minimum.ll | 24 ++++++++- llvm/test/Transforms/InstCombine/minnum.ll | 26 +++++++-- 4 files changed, 110 insertions(+), 24 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/maximum.ll b/llvm/test/Transforms/InstCombine/maximum.ll index 2439f7cd5f50..770f42edcdd4 100644 --- a/llvm/test/Transforms/InstCombine/maximum.ll +++ b/llvm/test/Transforms/InstCombine/maximum.ll @@ -147,8 +147,9 @@ define float @maximum_f32_val_nan(float %x) { define float @maximum_f32_1_maximum_val_p0(float %x) { ; CHECK-LABEL: @maximum_f32_1_maximum_val_p0( -; CHECK-NEXT: [[RES:%.*]] = call float @llvm.maximum.f32(float %x, float 1.000000e+00) -; CHECK-NEXT: ret float [[RES]] +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; %y = call float @llvm.maximum.f32(float %x, float 0.0) %z = call float @llvm.maximum.f32(float %y, float 1.0) ret float %z @@ -156,26 +157,49 @@ define float @maximum_f32_1_maximum_val_p0(float %x) { define float @maximum_f32_1_maximum_p0_val_fast(float %x) { ; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fast( -; CHECK-NEXT: [[RES:%.*]] = call fast float @llvm.maximum.f32(float %x, float 1.000000e+00) -; CHECK-NEXT: ret float [[RES]] +; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; %y = call float @llvm.maximum.f32(float 0.0, float %x) %z = call fast float @llvm.maximum.f32(float %y, float 1.0) ret float %z } -define float @maximum_f32_1_maximum_p0_val_nnan_ninf(float %x) { -; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_nnan_ninf( -; CHECK-NEXT: [[RES:%.*]] = call nnan ninf float @llvm.maximum.f32(float %x, float 1.000000e+00) -; CHECK-NEXT: ret float [[RES]] - %y = call float @llvm.maximum.f32(float 0.0, float %x) - %z = call nnan ninf float @llvm.maximum.f32(float %y, float 1.0) +define float @maximum_f32_1_maximum_p0_val_fmf1(float %x) { +; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf1( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf arcp float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call arcp nnan float @llvm.maximum.f32(float 0.0, float %x) + %z = call arcp nnan ninf float @llvm.maximum.f32(float %y, float 1.0) + ret float %z +} + +define float @maximum_f32_1_maximum_p0_val_fmf2(float %x) { +; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf2( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call arcp nnan ninf float @llvm.maximum.f32(float 0.0, float %x) + %z = call nnan float @llvm.maximum.f32(float %y, float 1.0) + ret float %z +} + +define float @maximum_f32_1_maximum_p0_val_fmf3(float %x) { +; CHECK-LABEL: @maximum_f32_1_maximum_p0_val_fmf3( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf arcp float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nnan ninf float @llvm.maximum.f32(float 0.0, float %x) + %z = call arcp nnan ninf float @llvm.maximum.f32(float %y, float 1.0) ret float %z } define float @maximum_f32_p0_maximum_val_n0(float %x) { ; CHECK-LABEL: @maximum_f32_p0_maximum_val_n0( -; CHECK-NEXT: [[RES:%.*]] = call float @llvm.maximum.f32(float %x, float 0.000000e+00) -; CHECK-NEXT: ret float [[RES]] +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 0.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; %y = call float @llvm.maximum.f32(float %x, float -0.0) %z = call float @llvm.maximum.f32(float %y, float 0.0) ret float %z @@ -183,8 +207,9 @@ define float @maximum_f32_p0_maximum_val_n0(float %x) { define float @maximum_f32_1_maximum_p0_val(float %x) { ; CHECK-LABEL: @maximum_f32_1_maximum_p0_val( -; CHECK-NEXT: [[RES:%.*]] = call float @llvm.maximum.f32(float %x, float 1.000000e+00) -; CHECK-NEXT: ret float [[RES]] +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maximum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; %y = call float @llvm.maximum.f32(float 0.0, float %x) %z = call float @llvm.maximum.f32(float %y, float 1.0) ret float %z @@ -192,8 +217,9 @@ define float @maximum_f32_1_maximum_p0_val(float %x) { define <2 x float> @maximum_f32_1_maximum_val_p0_val_v2f32(<2 x float> %x) { ; CHECK-LABEL: @maximum_f32_1_maximum_val_p0_val_v2f32( -; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.maximum.v2f32(<2 x float> %x, <2 x float> ) -; CHECK-NEXT: ret <2 x float> [[RES]] +; CHECK-NEXT: [[TMP1:%.*]] = call <2 x float> @llvm.maximum.v2f32(<2 x float> [[X:%.*]], <2 x float> ) +; CHECK-NEXT: ret <2 x float> [[TMP1]] +; %y = call <2 x float> @llvm.maximum.v2f32(<2 x float> %x, <2 x float> zeroinitializer) %z = call <2 x float> @llvm.maximum.v2f32(<2 x float> %y, <2 x float>) ret <2 x float> %z diff --git a/llvm/test/Transforms/InstCombine/maxnum.ll b/llvm/test/Transforms/InstCombine/maxnum.ll index df3c75c7e53f..f68651a5fdc3 100644 --- a/llvm/test/Transforms/InstCombine/maxnum.ll +++ b/llvm/test/Transforms/InstCombine/maxnum.ll @@ -165,16 +165,36 @@ define float @maxnum_f32_1_maxnum_p0_val_fast(float %x) { ret float %z } -define float @maxnum_f32_1_maxnum_p0_val_nnan_ninf(float %x) { -; CHECK-LABEL: @maxnum_f32_1_maxnum_p0_val_nnan_ninf( +define float @minnum_f32_1_maxnum_p0_val_fmf1(float %x) { +; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf1( ; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00) ; CHECK-NEXT: ret float [[TMP1]] ; - %y = call float @llvm.maxnum.f32(float 0.0, float %x) + %y = call nnan float @llvm.maxnum.f32(float 0.0, float %x) %z = call nnan ninf float @llvm.maxnum.f32(float %y, float 1.0) ret float %z } +define float @minnum_f32_1_maxnum_p0_val_fmf2(float %x) { +; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf2( +; CHECK-NEXT: [[TMP1:%.*]] = call ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nnan ninf float @llvm.maxnum.f32(float 0.0, float %x) + %z = call ninf float @llvm.maxnum.f32(float %y, float 1.0) + ret float %z +} + +define float @minnum_f32_1_maxnum_p0_val_fmf3(float %x) { +; CHECK-LABEL: @minnum_f32_1_maxnum_p0_val_fmf3( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.maxnum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call ninf nnan float @llvm.maxnum.f32(float 0.0, float %x) + %z = call ninf nnan float @llvm.maxnum.f32(float %y, float 1.0) + ret float %z +} + define float @maxnum_f32_p0_maxnum_val_n0(float %x) { ; CHECK-LABEL: @maxnum_f32_p0_maxnum_val_n0( ; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float 0.000000e+00) diff --git a/llvm/test/Transforms/InstCombine/minimum.ll b/llvm/test/Transforms/InstCombine/minimum.ll index a8b6aefe52c4..39bf5e7fefe5 100644 --- a/llvm/test/Transforms/InstCombine/minimum.ll +++ b/llvm/test/Transforms/InstCombine/minimum.ll @@ -167,8 +167,8 @@ define float @minimum_f32_1_minimum_p0_val_fast(float %x) { ret float %z } -define float @minimum_f32_1_minimum_p0_val_nnan_ninf(float %x) { -; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_nnan_ninf( +define float @minimum_f32_1_minimum_p0_val_fmf1(float %x) { +; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf1( ; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00) ; CHECK-NEXT: ret float [[TMP1]] ; @@ -177,6 +177,26 @@ define float @minimum_f32_1_minimum_p0_val_nnan_ninf(float %x) { ret float %z } +define float @minimum_f32_1_minimum_p0_val_fmf2(float %x) { +; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf2( +; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nnan ninf float @llvm.minimum.f32(float 0.0, float %x) + %z = call float @llvm.minimum.f32(float %y, float 1.0) + ret float %z +} + +define float @minimum_f32_1_minimum_p0_val_fmf3(float %x) { +; CHECK-LABEL: @minimum_f32_1_minimum_p0_val_fmf3( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.minimum.f32(float [[X:%.*]], float 0.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nnan ninf float @llvm.minimum.f32(float 0.0, float %x) + %z = call nnan ninf float @llvm.minimum.f32(float %y, float 1.0) + ret float %z +} + define float @minimum_f32_p0_minimum_val_n0(float %x) { ; CHECK-LABEL: @minimum_f32_p0_minimum_val_n0( ; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minimum.f32(float [[X:%.*]], float -0.000000e+00) diff --git a/llvm/test/Transforms/InstCombine/minnum.ll b/llvm/test/Transforms/InstCombine/minnum.ll index 1c3e5a803c0d..bd078a2ae6cb 100644 --- a/llvm/test/Transforms/InstCombine/minnum.ll +++ b/llvm/test/Transforms/InstCombine/minnum.ll @@ -167,16 +167,36 @@ define float @minnum_f32_1_minnum_p0_val_fast(float %x) { ret float %z } -define float @minnum_f32_1_minnum_p0_val_nnan_ninf(float %x) { -; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_nnan_ninf( +define float @minnum_f32_1_minnum_p0_val_fmf1(float %x) { +; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf1( ; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00) ; CHECK-NEXT: ret float [[TMP1]] ; - %y = call float @llvm.minnum.f32(float 0.0, float %x) + %y = call nsz nnan float @llvm.minnum.f32(float 0.0, float %x) %z = call nnan ninf float @llvm.minnum.f32(float %y, float 1.0) ret float %z } +define float @minnum_f32_1_minnum_p0_val_fmf2(float %x) { +; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf2( +; CHECK-NEXT: [[TMP1:%.*]] = call ninf nsz float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nnan ninf float @llvm.minnum.f32(float 0.0, float %x) + %z = call nsz ninf float @llvm.minnum.f32(float %y, float 1.0) + ret float %z +} + +define float @minnum_f32_1_minnum_p0_val_fmf3(float %x) { +; CHECK-LABEL: @minnum_f32_1_minnum_p0_val_fmf3( +; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf nsz float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00) +; CHECK-NEXT: ret float [[TMP1]] +; + %y = call nsz ninf nnan float @llvm.minnum.f32(float 0.0, float %x) + %z = call nsz ninf nnan float @llvm.minnum.f32(float %y, float 1.0) + ret float %z +} + define float @minnum_f32_p0_minnum_val_n0(float %x) { ; CHECK-LABEL: @minnum_f32_p0_minnum_val_n0( ; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 0.000000e+00) -- GitLab From 09ba6f9e694cacc9310967ae149b849ecfc72fa5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 12:40:39 +0100 Subject: [PATCH 076/910] X86TargetMachine.h - remove unused X86RegisterBankInfo forward declaration. NFC. --- llvm/lib/Target/X86/X86TargetMachine.h | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 757ce8bc5c72..7ed1756f98e7 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -24,7 +24,6 @@ namespace llvm { class StringRef; class X86Subtarget; -class X86RegisterBankInfo; class TargetTransformInfo; class X86TargetMachine final : public LLVMTargetMachine { -- GitLab From 6f2d64696d6f8bce18b9b5e84be734a2d3d07302 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 12:41:50 +0100 Subject: [PATCH 077/910] [AsmParser] Remove unused forward declarations. NFC. --- llvm/lib/AsmParser/LLLexer.h | 1 - llvm/lib/AsmParser/LLParser.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/llvm/lib/AsmParser/LLLexer.h b/llvm/lib/AsmParser/LLLexer.h index 4d3a2920e937..9d93447d78ae 100644 --- a/llvm/lib/AsmParser/LLLexer.h +++ b/llvm/lib/AsmParser/LLLexer.h @@ -20,7 +20,6 @@ #include namespace llvm { - class MemoryBuffer; class Type; class SMDiagnostic; class LLVMContext; diff --git a/llvm/lib/AsmParser/LLParser.h b/llvm/lib/AsmParser/LLParser.h index d85341395440..e4ff97bab6f6 100644 --- a/llvm/lib/AsmParser/LLParser.h +++ b/llvm/lib/AsmParser/LLParser.h @@ -27,7 +27,6 @@ namespace llvm { class Module; - class OpaqueType; class Function; class Value; class BasicBlock; @@ -38,7 +37,6 @@ namespace llvm { class MDString; class MDNode; struct SlotMapping; - class StructType; /// ValID - Represents a reference of a definition of some sort with no type. /// There are several cases where we have to parse the value but where the -- GitLab From 7c7b77a341b3f554be46031a8ed6fbd48ce3e83f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 12:43:58 +0100 Subject: [PATCH 078/910] MetadataLoader.h - remove unused MDNode forward declaration. NFC. --- llvm/lib/Bitcode/Reader/MetadataLoader.h | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.h b/llvm/lib/Bitcode/Reader/MetadataLoader.h index fe2b20273249..43508f183704 100644 --- a/llvm/lib/Bitcode/Reader/MetadataLoader.h +++ b/llvm/lib/Bitcode/Reader/MetadataLoader.h @@ -27,7 +27,6 @@ class Error; class Function; class Instruction; class Metadata; -class MDNode; class Module; class Type; -- GitLab From c3730ad8fcf5ee2ccf3b409faa09ac482b5235de Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 13:44:58 +0100 Subject: [PATCH 079/910] [AsmPrinter] Remove unused forward declarations. NFC. --- llvm/lib/CodeGen/AsmPrinter/DIEHash.h | 1 - llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h | 1 - llvm/lib/CodeGen/AsmPrinter/WinException.h | 2 -- 3 files changed, 4 deletions(-) diff --git a/llvm/lib/CodeGen/AsmPrinter/DIEHash.h b/llvm/lib/CodeGen/AsmPrinter/DIEHash.h index 2e49514c98be..1a69f6772873 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DIEHash.h +++ b/llvm/lib/CodeGen/AsmPrinter/DIEHash.h @@ -20,7 +20,6 @@ namespace llvm { class AsmPrinter; -class CompileUnit; /// An object containing the capability of hashing and adding hash /// attributes onto a DIE. diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h index 46c52a1faf4b..34f3a34ed336 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h @@ -27,7 +27,6 @@ namespace llvm { -class MachineLocation; class MachineOperand; class ConstantInt; class ConstantFP; diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.h b/llvm/lib/CodeGen/AsmPrinter/WinException.h index dc5036302131..8bd5d1bc6d2a 100644 --- a/llvm/lib/CodeGen/AsmPrinter/WinException.h +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.h @@ -16,12 +16,10 @@ #include "EHStreamer.h" namespace llvm { -class Function; class GlobalValue; class MachineFunction; class MCExpr; class MCSection; -class Value; struct WinEHFuncInfo; class LLVM_LIBRARY_VISIBILITY WinException : public EHStreamer { -- GitLab From 4eca1c06a4a9183fcf7bb230d894617caf3cf3be Mon Sep 17 00:00:00 2001 From: Pavel Iliin Date: Wed, 22 Apr 2020 12:34:36 +0100 Subject: [PATCH 080/910] [AArch64][FIX] f16 indexed patterns encoding restrictions. --- .../aarch64-v8.2a-neon-intrinsics-constrained.c | 4 ++-- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c index b72bd3f977dd..6058e6f92832 100644 --- a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c +++ b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c @@ -121,7 +121,7 @@ float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) { // COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> // UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]]) // CONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]], metadata !"round.tonearest", metadata !"fpexcept.strict") -// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h +// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}] // COMMONIR: ret <4 x half> [[FMLA]] float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) { return vfma_laneq_f16(a, b, c, 7); @@ -239,7 +239,7 @@ float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) { // COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> // UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]]) // CONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]], metadata !"round.tonearest", metadata !"fpexcept.strict") -// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h +// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}] // COMMONIR: ret <4 x half> [[FMLA]] float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) { return vfms_laneq_f16(a, b, c, 7); diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 061e2a0ec619..29422fa650e6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -8068,29 +8068,29 @@ multiclass SIMDFPIndexedTiedPatterns { let Predicates = [HasNEON, HasFullFP16] in { // Patterns for f16: DUPLANE, DUP scalar and vector_extract. def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), - (AArch64duplane16 (v8f16 V128:$Rm), + (AArch64duplane16 (v8f16 V128_lo:$Rm), VectorIndexH:$idx))), (!cast(INST # "v8i16_indexed") - V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexH:$idx)>; + V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>; def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (AArch64dup (f16 FPR16Op:$Rm)))), (!cast(INST # "v8i16_indexed") V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>; def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), - (AArch64duplane16 (v8f16 V128:$Rm), - VectorIndexS:$idx))), + (AArch64duplane16 (v8f16 V128_lo:$Rm), + VectorIndexH:$idx))), (!cast(INST # "v4i16_indexed") - V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; + V64:$Rd, V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>; def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (AArch64dup (f16 FPR16Op:$Rm)))), (!cast(INST # "v4i16_indexed") V64:$Rd, V64:$Rn, (SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>; def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn), - (vector_extract (v8f16 V128:$Rm), VectorIndexH:$idx))), + (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))), (!cast(INST # "v1i16_indexed") FPR16:$Rd, FPR16:$Rn, - V128:$Rm, VectorIndexH:$idx)>; + V128_lo:$Rm, VectorIndexH:$idx)>; } // Predicates = [HasNEON, HasFullFP16] // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar. -- GitLab From 892af45c8697849666ea26e20492603b11533866 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 22 Apr 2020 13:30:22 +0100 Subject: [PATCH 081/910] [ARM] Distribute MVE post-increments This adds some extra processing into the Pre-RA ARM load/store optimizer to detect and merge MVE loads/stores and adds of the same base. This we don't always turn into a post-inc during ISel, and due to the nature of it being a graph we don't always know an order to use for the nodes, not knowing which nodes to make post-inc and which to use the new post-inc of. After ISel, we have an order that we can use to post-inc the following instructions. So this looks for a loads/store with a starting offset of 0, and an add/sub from the same base, plus a number of other loads/stores. We then do some checks and convert the zero offset load/store into a postinc variant. Any loads/stores after it have the offset subtracted from their immediates. For example: LDR #4 LDR #4 LDR #0 LDR_POSTINC #16 LDR #8 LDR #-8 LDR #12 LDR #-4 ADD #16 It only handles MVE loads/stores at the moment. Normal loads/store will be added in a followup patch, they just have some extra details to ensure that we keep generating LDRD/LDM successfully. Differential Revision: https://reviews.llvm.org/D77813 --- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 43 ++++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 241 +++++++++++++++++- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 17 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 1 + .../CodeGen/Thumb2/mve-float32regloops.ll | 150 ++++++----- llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll | 24 +- .../CodeGen/Thumb2/mve-postinc-distribute.ll | 62 ++--- .../CodeGen/Thumb2/mve-postinc-distribute.mir | 133 ++++------ llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 36 +-- llvm/test/CodeGen/Thumb2/mve-vld2-post.ll | 6 +- llvm/test/CodeGen/Thumb2/mve-vld4-post.ll | 12 +- llvm/test/CodeGen/Thumb2/mve-vldst4.ll | 12 +- llvm/test/CodeGen/Thumb2/mve-vst2-post.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-vst4-post.ll | 20 +- 14 files changed, 482 insertions(+), 279 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 173b57c62a2f..98e6b4ca6bd0 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -788,6 +788,49 @@ bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize = false); +// Return the immediate if this is ADDri or SUBri, scaled as appropriate. +// Returns 0 for unknown instructions. +inline int getAddSubImmediate(MachineInstr &MI) { + int Scale = 1; + unsigned ImmOp; + switch (MI.getOpcode()) { + case ARM::t2ADDri: + ImmOp = 2; + break; + case ARM::t2SUBri: + case ARM::t2SUBri12: + ImmOp = 2; + Scale = -1; + break; + case ARM::tSUBi3: + case ARM::tSUBi8: + ImmOp = 3; + Scale = -1; + break; + default: + return 0; + } + return Scale * MI.getOperand(ImmOp).getImm(); +} + +// Given a memory access Opcode, check that the give Imm would be a valid Offset +// for this instruction using its addressing mode. +inline bool isLegalAddressImm(unsigned Opcode, int Imm, + const TargetInstrInfo *TII) { + const MCInstrDesc &Desc = TII->get(Opcode); + unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); + switch (AddrMode) { + case ARMII::AddrModeT2_i7: + return std::abs(Imm) < (((1 << 7) * 1) - 1); + case ARMII::AddrModeT2_i7s2: + return std::abs(Imm) < (((1 << 7) * 2) - 1) && Imm % 2 == 0; + case ARMII::AddrModeT2_i7s4: + return std::abs(Imm) < (((1 << 7) * 4) - 1) && Imm % 4 == 0; + default: + llvm_unreachable("Unhandled Addressing mode"); + } +} + } // end namespace llvm #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 852e3d7cbca3..d38da836eb8c 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -32,6 +32,7 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" @@ -50,6 +51,7 @@ #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/Type.h" +#include "llvm/InitializePasses.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/Pass.h" #include "llvm/Support/Allocator.h" @@ -1383,6 +1385,38 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc, case ARM::t2STRi8: case ARM::t2STRi12: return ARM::t2STR_POST; + + case ARM::MVE_VLDRBS16: + return ARM::MVE_VLDRBS16_post; + case ARM::MVE_VLDRBS32: + return ARM::MVE_VLDRBS32_post; + case ARM::MVE_VLDRBU16: + return ARM::MVE_VLDRBU16_post; + case ARM::MVE_VLDRBU32: + return ARM::MVE_VLDRBU32_post; + case ARM::MVE_VLDRHS32: + return ARM::MVE_VLDRHS32_post; + case ARM::MVE_VLDRHU32: + return ARM::MVE_VLDRHU32_post; + case ARM::MVE_VLDRBU8: + return ARM::MVE_VLDRBU8_post; + case ARM::MVE_VLDRHU16: + return ARM::MVE_VLDRHU16_post; + case ARM::MVE_VLDRWU32: + return ARM::MVE_VLDRWU32_post; + case ARM::MVE_VSTRB16: + return ARM::MVE_VSTRB16_post; + case ARM::MVE_VSTRB32: + return ARM::MVE_VSTRB32_post; + case ARM::MVE_VSTRH32: + return ARM::MVE_VSTRH32_post; + case ARM::MVE_VSTRBU8: + return ARM::MVE_VSTRBU8_post; + case ARM::MVE_VSTRHU16: + return ARM::MVE_VSTRHU16_post; + case ARM::MVE_VSTRWU32: + return ARM::MVE_VSTRWU32_post; + default: llvm_unreachable("Unhandled opcode!"); } } @@ -2046,6 +2080,7 @@ namespace { const TargetRegisterInfo *TRI; const ARMSubtarget *STI; MachineRegisterInfo *MRI; + MachineDominatorTree *DT; MachineFunction *MF; ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {} @@ -2058,6 +2093,8 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -2071,14 +2108,19 @@ namespace { unsigned Base, bool isLd, DenseMap &MI2LocMap); bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB); + bool DistributeIncrements(); + bool DistributeIncrements(Register Base); }; } // end anonymous namespace char ARMPreAllocLoadStoreOpt::ID = 0; -INITIALIZE_PASS(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", - ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) +INITIALIZE_PASS_BEGIN(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", + ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", + ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) // Limit the number of instructions to be rescheduled. // FIXME: tune this limit, and/or come up with some better heuristics. @@ -2094,10 +2136,11 @@ bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); MRI = &Fn.getRegInfo(); + DT = &getAnalysis(); MF = &Fn; AA = &getAnalysis().getAAResults(); - bool Modified = false; + bool Modified = DistributeIncrements(); for (MachineBasicBlock &MFI : Fn) Modified |= RescheduleLoadStoreInstrs(&MFI); @@ -2475,6 +2518,198 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) { return RetVal; } +// Get the Base register operand index from the memory access MachineInst if we +// should attempt to distribute postinc on it. Return -1 if not of a valid +// instruction type. If it returns an index, it is assumed that instruction is a +// r+i indexing mode, and getBaseOperandIndex() + 1 is the Offset index. +static int getBaseOperandIndex(MachineInstr &MI) { + switch (MI.getOpcode()) { + case ARM::MVE_VLDRBS16: + case ARM::MVE_VLDRBS32: + case ARM::MVE_VLDRBU16: + case ARM::MVE_VLDRBU32: + case ARM::MVE_VLDRHS32: + case ARM::MVE_VLDRHU32: + case ARM::MVE_VLDRBU8: + case ARM::MVE_VLDRHU16: + case ARM::MVE_VLDRWU32: + case ARM::MVE_VSTRB16: + case ARM::MVE_VSTRB32: + case ARM::MVE_VSTRH32: + case ARM::MVE_VSTRBU8: + case ARM::MVE_VSTRHU16: + case ARM::MVE_VSTRWU32: + return 1; + } + return -1; +} + +static MachineInstr *createPostIncLoadStore(MachineInstr *MI, int Offset, + Register NewReg, + const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI) { + MachineFunction *MF = MI->getMF(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + + unsigned NewOpcode = getPostIndexedLoadStoreOpcode( + MI->getOpcode(), Offset > 0 ? ARM_AM::add : ARM_AM::sub); + + const MCInstrDesc &MCID = TII->get(NewOpcode); + // Constrain the def register class + const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); + MRI.constrainRegClass(NewReg, TRC); + // And do the same for the base operand + TRC = TII->getRegClass(MCID, 2, TRI, *MF); + MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); + + return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID) + .addReg(NewReg, RegState::Define) + .add(MI->getOperand(0)) + .add(MI->getOperand(1)) + .addImm(Offset) + .add(MI->getOperand(3)) + .add(MI->getOperand(4)) + .cloneMemRefs(*MI); +} + +// Given a Base Register, optimise the load/store uses to attempt to create more +// post-inc accesses. We do this by taking zero offset loads/stores with an add, +// and convert them to a postinc load/store of the same type. Any subsequent +// accesses will be adjusted to use and account for the post-inc value. +// For example: +// LDR #0 LDR_POSTINC #16 +// LDR #4 LDR #-12 +// LDR #8 LDR #-8 +// LDR #12 LDR #-4 +// ADD #16 +bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) { + // We are looking for: + // One zero offset load/store that can become postinc + MachineInstr *BaseAccess = nullptr; + // An increment that can be folded in + MachineInstr *Increment = nullptr; + // Other accesses after BaseAccess that will need to be updated to use the + // postinc value + SmallPtrSet OtherAccesses; + for (auto &Use : MRI->use_nodbg_instructions(Base)) { + if (!Increment && getAddSubImmediate(Use) != 0) { + Increment = &Use; + continue; + } + + int BaseOp = getBaseOperandIndex(Use); + if (BaseOp == -1) + return false; + + if (!Use.getOperand(BaseOp).isReg() || + Use.getOperand(BaseOp).getReg() != Base) + return false; + if (Use.getOperand(BaseOp + 1).getImm() == 0) + BaseAccess = &Use; + else + OtherAccesses.insert(&Use); + } + + if (!BaseAccess || !Increment || + BaseAccess->getParent() != Increment->getParent()) + return false; + Register PredReg; + if (Increment->definesRegister(ARM::CPSR) || + getInstrPredicate(*Increment, PredReg) != ARMCC::AL) + return false; + + LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on VirtualReg " + << Base.virtRegIndex() << "\n"); + + // Make sure that Increment has no uses before BaseAccess. + for (MachineInstr &Use : + MRI->use_nodbg_instructions(Increment->getOperand(0).getReg())) { + if (!DT->dominates(BaseAccess, &Use) || &Use == BaseAccess) { + LLVM_DEBUG(dbgs() << " BaseAccess doesn't dominate use of increment\n"); + return false; + } + } + + // Make sure that Increment can be folded into Base + int IncrementOffset = getAddSubImmediate(*Increment); + unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode( + BaseAccess->getOpcode(), IncrementOffset > 0 ? ARM_AM::add : ARM_AM::sub); + if (!isLegalAddressImm(NewPostIncOpcode, IncrementOffset, TII)) { + LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on postinc\n"); + return false; + } + + // And make sure that the negative value of increment can be added to all + // other offsets after the BaseAccess. We rely on either + // dominates(BaseAccess, OtherAccess) or dominates(OtherAccess, BaseAccess) + // to keep things simple. + SmallPtrSet SuccessorAccesses; + for (auto *Use : OtherAccesses) { + if (DT->dominates(BaseAccess, Use)) { + SuccessorAccesses.insert(Use); + unsigned BaseOp = getBaseOperandIndex(*Use); + if (!isLegalAddressImm( + Use->getOpcode(), + Use->getOperand(BaseOp + 1).getImm() - IncrementOffset, TII)) { + LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on use\n"); + return false; + } + } else if (!DT->dominates(Use, BaseAccess)) { + LLVM_DEBUG( + dbgs() << " Unknown dominance relation between Base and Use\n"); + return false; + } + } + + // Replace BaseAccess with a post inc + LLVM_DEBUG(dbgs() << "Changing: "; BaseAccess->dump()); + LLVM_DEBUG(dbgs() << " And : "; Increment->dump()); + Register NewBaseReg = Increment->getOperand(0).getReg(); + MachineInstr *BaseAccessPost = + createPostIncLoadStore(BaseAccess, IncrementOffset, NewBaseReg, TII, TRI); + BaseAccess->eraseFromParent(); + Increment->eraseFromParent(); + LLVM_DEBUG(dbgs() << " To : "; BaseAccessPost->dump()); + + for (auto *Use : SuccessorAccesses) { + LLVM_DEBUG(dbgs() << "Changing: "; Use->dump()); + unsigned BaseOp = getBaseOperandIndex(*Use); + Use->getOperand(BaseOp).setReg(NewBaseReg); + int OldOffset = Use->getOperand(BaseOp + 1).getImm(); + Use->getOperand(BaseOp + 1).setImm(OldOffset - IncrementOffset); + LLVM_DEBUG(dbgs() << " To : "; Use->dump()); + } + + // Remove the kill flag from all uses of NewBaseReg, in case any old uses + // remain. + for (MachineOperand &Op : MRI->use_nodbg_operands(NewBaseReg)) + Op.setIsKill(false); + return true; +} + +bool ARMPreAllocLoadStoreOpt::DistributeIncrements() { + bool Changed = false; + SmallSetVector Visited; + for (auto &MBB : *MF) { + for (auto &MI : MBB) { + int BaseOp = getBaseOperandIndex(MI); + if (BaseOp == -1 || !MI.getOperand(BaseOp).isReg()) + continue; + + Register Base = MI.getOperand(BaseOp).getReg(); + if (!Base.isVirtual() || Visited.count(Base)) + continue; + + Visited.insert(Base); + } + } + + for (auto Base : Visited) + Changed |= DistributeIncrements(Base); + + return Changed; +} + /// Returns an instance of the load / store optimization pass. FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) { if (PreAlloc) diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index 4ccf62759f5a..44ddb4e2f801 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -463,21 +463,8 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { // that the predication will be equivalent. For this we need: // NumElements = NumElements - VectorWidth. The sub will be a sub immediate // and we can also allow register copies within the chain too. - auto IsValidSub = [](MachineInstr *MI, unsigned ExpectedVecWidth) { - unsigned ImmOpIdx = 0; - switch (MI->getOpcode()) { - default: - llvm_unreachable("unhandled sub opcode"); - case ARM::tSUBi3: - case ARM::tSUBi8: - ImmOpIdx = 3; - break; - case ARM::t2SUBri: - case ARM::t2SUBri12: - ImmOpIdx = 2; - break; - } - return MI->getOperand(ImmOpIdx).getImm() == ExpectedVecWidth; + auto IsValidSub = [](MachineInstr *MI, int ExpectedVecWidth) { + return -getAddSubImmediate(*MI) == ExpectedVecWidth; }; MBB = VCTP->getParent(); diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index f37b0863f8d7..60e9932e95f6 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -94,6 +94,7 @@ ; CHECK-NEXT: Remove dead machine instructions ; CHECK-NEXT: MVE VPT Optimisation Pass ; CHECK-NEXT: ARM MLA / MLS expansion pass +; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: ARM pre- register allocation load / store optimization pass ; CHECK-NEXT: ARM A15 S->D optimizer ; CHECK-NEXT: Detect Dead Lanes diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll index f6d1d9ab8839..e86d3606f27f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll @@ -1057,8 +1057,8 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, float* noc ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} -; CHECK-NEXT: .pad #40 -; CHECK-NEXT: sub sp, #40 +; CHECK-NEXT: .pad #32 +; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: cmp r3, #8 ; CHECK-NEXT: blo.w .LBB16_12 ; CHECK-NEXT: @ %bb.1: @ %if.then @@ -1066,130 +1066,124 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, float* noc ; CHECK-NEXT: cmp.w r7, r3, lsr #2 ; CHECK-NEXT: beq.w .LBB16_12 ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph -; CHECK-NEXT: ldrh r4, [r0] -; CHECK-NEXT: movs r5, #1 -; CHECK-NEXT: ldrd r6, r12, [r0, #4] -; CHECK-NEXT: lsrs r3, r3, #2 -; CHECK-NEXT: sub.w r0, r4, #8 +; CHECK-NEXT: ldrh r5, [r0] +; CHECK-NEXT: lsr.w r9, r3, #2 +; CHECK-NEXT: ldrd r8, r12, [r0, #4] +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: sub.w r0, r5, #8 ; CHECK-NEXT: add.w r7, r0, r0, lsr #29 ; CHECK-NEXT: and r0, r0, #7 -; CHECK-NEXT: asr.w lr, r7, #3 -; CHECK-NEXT: cmp.w lr, #1 +; CHECK-NEXT: asrs r6, r7, #3 +; CHECK-NEXT: cmp r6, #1 ; CHECK-NEXT: it gt -; CHECK-NEXT: asrgt r5, r7, #3 -; CHECK-NEXT: add.w r7, r6, r4, lsl #2 +; CHECK-NEXT: asrgt r3, r7, #3 +; CHECK-NEXT: add.w r7, r8, r5, lsl #2 ; CHECK-NEXT: sub.w r11, r7, #4 -; CHECK-NEXT: rsbs r7, r4, #0 -; CHECK-NEXT: str r7, [sp, #16] @ 4-byte Spill -; CHECK-NEXT: add.w r7, r12, #32 -; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill +; CHECK-NEXT: str r3, [sp] @ 4-byte Spill +; CHECK-NEXT: rsbs r3, r5, #0 +; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill +; CHECK-NEXT: add.w r3, r12, #32 +; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: adds r0, #1 -; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill -; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill -; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill -; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill +; CHECK-NEXT: str r5, [sp, #16] @ 4-byte Spill +; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill +; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: b .LBB16_4 ; CHECK-NEXT: .LBB16_3: @ %while.end ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: ldrd r11, r3, [sp, #28] @ 8-byte Folded Reload +; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: subs.w r9, r9, #1 +; CHECK-NEXT: ldrd r11, r1, [sp, #24] @ 8-byte Folded Reload ; CHECK-NEXT: vstrb.8 q0, [r2], #16 -; CHECK-NEXT: ldr r1, [sp, #36] @ 4-byte Reload -; CHECK-NEXT: subs r3, #1 ; CHECK-NEXT: add.w r0, r8, r0, lsl #2 -; CHECK-NEXT: add.w r6, r0, #16 +; CHECK-NEXT: add.w r8, r0, #16 ; CHECK-NEXT: beq .LBB16_12 ; CHECK-NEXT: .LBB16_4: @ %while.body ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB16_6 Depth 2 ; CHECK-NEXT: @ Child Loop BB16_10 Depth 2 -; CHECK-NEXT: add.w lr, r12, #12 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16 -; CHECK-NEXT: ldm.w r12, {r0, r5, r7} -; CHECK-NEXT: ldm.w lr, {r4, r9, lr} -; CHECK-NEXT: ldrd r8, r10, [r12, #24] +; CHECK-NEXT: ldrd r0, r7, [r12] +; CHECK-NEXT: ldrd r4, r6, [r12, #8] +; CHECK-NEXT: ldrd r5, r3, [r12, #16] +; CHECK-NEXT: ldrd lr, r10, [r12, #24] ; CHECK-NEXT: vstrb.8 q0, [r11], #16 -; CHECK-NEXT: vldrw.u32 q0, [r6] -; CHECK-NEXT: vldrw.u32 q1, [r6, #4] -; CHECK-NEXT: vldrw.u32 q6, [r6, #8] -; CHECK-NEXT: vldrw.u32 q4, [r6, #12] +; CHECK-NEXT: vldrw.u32 q0, [r8], #32 +; CHECK-NEXT: vldrw.u32 q1, [r8, #-28] ; CHECK-NEXT: vmul.f32 q0, q0, r0 -; CHECK-NEXT: vldrw.u32 q5, [r6, #16] -; CHECK-NEXT: vfma.f32 q0, q1, r5 -; CHECK-NEXT: vldrw.u32 q2, [r6, #20] -; CHECK-NEXT: vfma.f32 q0, q6, r7 -; CHECK-NEXT: vldrw.u32 q3, [r6, #24] -; CHECK-NEXT: vfma.f32 q0, q4, r4 -; CHECK-NEXT: vldrw.u32 q1, [r6, #28] -; CHECK-NEXT: vfma.f32 q0, q5, r9 -; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload -; CHECK-NEXT: vfma.f32 q0, q2, lr -; CHECK-NEXT: add.w r5, r6, #32 -; CHECK-NEXT: vfma.f32 q0, q3, r8 -; CHECK-NEXT: cmp r0, #16 +; CHECK-NEXT: vldrw.u32 q6, [r8, #-24] +; CHECK-NEXT: vldrw.u32 q4, [r8, #-20] +; CHECK-NEXT: vfma.f32 q0, q1, r7 +; CHECK-NEXT: vldrw.u32 q5, [r8, #-16] +; CHECK-NEXT: vfma.f32 q0, q6, r4 +; CHECK-NEXT: vldrw.u32 q2, [r8, #-12] +; CHECK-NEXT: vfma.f32 q0, q4, r6 +; CHECK-NEXT: vldrw.u32 q3, [r8, #-8] +; CHECK-NEXT: vfma.f32 q0, q5, r5 +; CHECK-NEXT: vldrw.u32 q1, [r8, #-4] +; CHECK-NEXT: vfma.f32 q0, q2, r3 +; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload +; CHECK-NEXT: vfma.f32 q0, q3, lr +; CHECK-NEXT: strd r11, r1, [sp, #24] @ 8-byte Folded Spill ; CHECK-NEXT: vfma.f32 q0, q1, r10 -; CHECK-NEXT: str r1, [sp, #36] @ 4-byte Spill -; CHECK-NEXT: strd r11, r3, [sp, #28] @ 8-byte Folded Spill +; CHECK-NEXT: cmp r0, #16 ; CHECK-NEXT: blo .LBB16_7 ; CHECK-NEXT: @ %bb.5: @ %for.body.preheader ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr.w lr, [sp, #4] @ 4-byte Reload +; CHECK-NEXT: ldr.w lr, [sp] @ 4-byte Reload ; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: ldr r6, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: .LBB16_6: @ %for.body ; CHECK-NEXT: @ Parent Loop BB16_4 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: ldm.w r6, {r0, r3, r4, r7, r10, r11} -; CHECK-NEXT: vldrw.u32 q1, [r5] -; CHECK-NEXT: vldrw.u32 q6, [r5, #8] -; CHECK-NEXT: vldrw.u32 q4, [r5, #12] -; CHECK-NEXT: vldrw.u32 q5, [r5, #16] -; CHECK-NEXT: vldrw.u32 q2, [r5, #20] +; CHECK-NEXT: ldm.w r7, {r0, r3, r4, r5, r6, r10, r11} +; CHECK-NEXT: vldrw.u32 q1, [r8], #32 +; CHECK-NEXT: vldrw.u32 q6, [r8, #-24] +; CHECK-NEXT: vldrw.u32 q4, [r8, #-20] ; CHECK-NEXT: vfma.f32 q0, q1, r0 -; CHECK-NEXT: vldrw.u32 q1, [r5, #4] -; CHECK-NEXT: ldrd r1, r9, [r6, #24] -; CHECK-NEXT: vldrw.u32 q3, [r5, #24] +; CHECK-NEXT: vldrw.u32 q1, [r8, #-28] +; CHECK-NEXT: vldrw.u32 q5, [r8, #-16] +; CHECK-NEXT: vldrw.u32 q2, [r8, #-12] ; CHECK-NEXT: vfma.f32 q0, q1, r3 -; CHECK-NEXT: vldrw.u32 q1, [r5, #28] +; CHECK-NEXT: vldrw.u32 q3, [r8, #-8] ; CHECK-NEXT: vfma.f32 q0, q6, r4 -; CHECK-NEXT: add.w r8, r5, #32 -; CHECK-NEXT: vfma.f32 q0, q4, r7 -; CHECK-NEXT: adds r6, #32 -; CHECK-NEXT: vfma.f32 q0, q5, r10 -; CHECK-NEXT: vfma.f32 q0, q2, r11 -; CHECK-NEXT: mov r5, r8 -; CHECK-NEXT: vfma.f32 q0, q3, r1 -; CHECK-NEXT: vfma.f32 q0, q1, r9 +; CHECK-NEXT: ldr r1, [r7, #28] +; CHECK-NEXT: vfma.f32 q0, q4, r5 +; CHECK-NEXT: vldrw.u32 q1, [r8, #-4] +; CHECK-NEXT: vfma.f32 q0, q5, r6 +; CHECK-NEXT: adds r7, #32 +; CHECK-NEXT: vfma.f32 q0, q2, r10 +; CHECK-NEXT: vfma.f32 q0, q3, r11 +; CHECK-NEXT: vfma.f32 q0, q1, r1 ; CHECK-NEXT: le lr, .LBB16_6 ; CHECK-NEXT: b .LBB16_8 ; CHECK-NEXT: .LBB16_7: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr r6, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: mov r8, r5 +; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: .LBB16_8: @ %for.end ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload +; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: beq .LBB16_3 ; CHECK-NEXT: @ %bb.9: @ %while.body76.preheader ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: mov r0, r8 +; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload +; CHECK-NEXT: mov r4, r8 ; CHECK-NEXT: .LBB16_10: @ %while.body76 ; CHECK-NEXT: @ Parent Loop BB16_4 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: ldr r1, [r6], #4 -; CHECK-NEXT: vldrw.u32 q1, [r0], #4 -; CHECK-NEXT: subs r5, #1 +; CHECK-NEXT: ldr r1, [r7], #4 +; CHECK-NEXT: vldrw.u32 q1, [r4], #4 +; CHECK-NEXT: subs r0, #1 ; CHECK-NEXT: vfma.f32 q0, q1, r1 -; CHECK-NEXT: cmp r5, #1 +; CHECK-NEXT: cmp r0, #1 ; CHECK-NEXT: bgt .LBB16_10 ; CHECK-NEXT: @ %bb.11: @ %while.end.loopexit ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload +; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: add.w r8, r8, r0, lsl #2 ; CHECK-NEXT: b .LBB16_3 ; CHECK-NEXT: .LBB16_12: @ %if.end -; CHECK-NEXT: add sp, #40 +; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} diff --git a/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll b/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll index d84724a0b52e..3d0634c0ca85 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll @@ -992,8 +992,7 @@ define i8* @ldrwi32_align1(i8* %x, i8* %y) { ; ; CHECK-BE-LABEL: ldrwi32_align1: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: vldrb.u8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-BE-NEXT: vrev32.8 q0, q0 ; CHECK-BE-NEXT: vstrw.32 q0, [r1] ; CHECK-BE-NEXT: bx lr @@ -1015,8 +1014,7 @@ define i8* @ldrhi16_align1(i8* %x, i8* %y) { ; ; CHECK-BE-LABEL: ldrhi16_align1: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: vldrb.u8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-BE-NEXT: vrev16.8 q0, q0 ; CHECK-BE-NEXT: vstrh.16 q0, [r1] ; CHECK-BE-NEXT: bx lr @@ -1062,8 +1060,7 @@ define i8* @ldrf32_align1(i8* %x, i8* %y) { ; ; CHECK-BE-LABEL: ldrf32_align1: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: vldrb.u8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-BE-NEXT: vrev32.8 q0, q0 ; CHECK-BE-NEXT: vstrw.32 q0, [r1] ; CHECK-BE-NEXT: bx lr @@ -1085,8 +1082,7 @@ define i8* @ldrf16_align1(i8* %x, i8* %y) { ; ; CHECK-BE-LABEL: ldrf16_align1: ; CHECK-BE: @ %bb.0: @ %entry -; CHECK-BE-NEXT: vldrb.u8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vldrb.u8 q0, [r0], #3 ; CHECK-BE-NEXT: vrev16.8 q0, q0 ; CHECK-BE-NEXT: vstrh.16 q0, [r1] ; CHECK-BE-NEXT: bx lr @@ -1819,8 +1815,7 @@ define i8* @strwi32_align1(i8* %y, i8* %x) { ; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE-NEXT: vldrw.u32 q0, [r1] ; CHECK-BE-NEXT: vrev32.8 q0, q0 -; CHECK-BE-NEXT: vstrb.8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-BE-NEXT: bx lr entry: %z = getelementptr inbounds i8, i8* %y, i32 3 @@ -1842,8 +1837,7 @@ define i8* @strhi16_align1(i8* %y, i8* %x) { ; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE-NEXT: vldrh.u16 q0, [r1] ; CHECK-BE-NEXT: vrev16.8 q0, q0 -; CHECK-BE-NEXT: vstrb.8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-BE-NEXT: bx lr entry: %z = getelementptr inbounds i8, i8* %y, i32 3 @@ -1889,8 +1883,7 @@ define i8* @strf32_align1(i8* %y, i8* %x) { ; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE-NEXT: vldrw.u32 q0, [r1] ; CHECK-BE-NEXT: vrev32.8 q0, q0 -; CHECK-BE-NEXT: vstrb.8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-BE-NEXT: bx lr entry: %z = getelementptr inbounds i8, i8* %y, i32 3 @@ -1912,8 +1905,7 @@ define i8* @strf16_align1(i8* %y, i8* %x) { ; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE-NEXT: vldrh.u16 q0, [r1] ; CHECK-BE-NEXT: vrev16.8 q0, q0 -; CHECK-BE-NEXT: vstrb.8 q0, [r0] -; CHECK-BE-NEXT: adds r0, #3 +; CHECK-BE-NEXT: vstrb.8 q0, [r0], #3 ; CHECK-BE-NEXT: bx lr entry: %z = getelementptr inbounds i8, i8* %y, i32 3 diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll index ba588166522b..5be3f722a0e4 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll @@ -17,10 +17,9 @@ define i32 @vaddv(i32* nocapture readonly %data, i32 %N) { ; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: .LBB0_2: @ %for.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrw.u32 q0, [r1] +; CHECK-NEXT: vldrw.u32 q0, [r1], #32 ; CHECK-NEXT: vaddva.s32 r0, q0 -; CHECK-NEXT: vldrw.u32 q0, [r1, #16] -; CHECK-NEXT: adds r1, #32 +; CHECK-NEXT: vldrw.u32 q0, [r1, #-16] ; CHECK-NEXT: vaddva.s32 r0, q0 ; CHECK-NEXT: le lr, .LBB0_2 ; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup @@ -68,40 +67,36 @@ define void @arm_cmplx_dot_prod_q15(i16* nocapture readonly %pSrcA, i16* nocaptu ; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: lsr.w lr, r7, #3 ; CHECK-NEXT: mov r7, r12 -; CHECK-NEXT: mov r9, r12 +; CHECK-NEXT: mov r11, r12 ; CHECK-NEXT: wls lr, lr, .LBB1_4 ; CHECK-NEXT: @ %bb.1: @ %while.body.preheader -; CHECK-NEXT: mov.w r9, #0 +; CHECK-NEXT: mov.w r11, #0 ; CHECK-NEXT: add.w r8, r0, lr, lsl #5 -; CHECK-NEXT: add.w r6, r0, #32 -; CHECK-NEXT: add.w r0, r1, #32 -; CHECK-NEXT: lsl.w r5, lr, #4 -; CHECK-NEXT: mov r4, r9 +; CHECK-NEXT: adds r0, #32 +; CHECK-NEXT: add.w r6, r1, #32 +; CHECK-NEXT: lsl.w r9, lr, #4 +; CHECK-NEXT: mov r4, r11 ; CHECK-NEXT: movs r7, #0 -; CHECK-NEXT: mov r12, r9 +; CHECK-NEXT: mov r12, r11 ; CHECK-NEXT: .LBB1_2: @ %while.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vldrh.u16 q2, [r0, #-16] -; CHECK-NEXT: vldrh.u16 q3, [r6, #-16] -; CHECK-NEXT: add.w r10, r6, #32 -; CHECK-NEXT: add.w r11, r0, #32 -; CHECK-NEXT: vmlaldavax.s16 r4, r9, q0, q1 +; CHECK-NEXT: vldrh.u16 q2, [r6, #-16] +; CHECK-NEXT: vldrh.u16 q3, [r0, #-16] +; CHECK-NEXT: vmlaldavax.s16 r4, r11, q0, q1 ; CHECK-NEXT: vmlsldava.s16 r12, r7, q0, q1 -; CHECK-NEXT: vldrh.u16 q0, [r6] -; CHECK-NEXT: vldrh.u16 q1, [r0] -; CHECK-NEXT: vmlaldavax.s16 r4, r9, q3, q2 +; CHECK-NEXT: vldrh.u16 q0, [r0], #32 +; CHECK-NEXT: vldrh.u16 q1, [r6], #32 +; CHECK-NEXT: vmlaldavax.s16 r4, r11, q3, q2 ; CHECK-NEXT: vmlsldava.s16 r12, r7, q3, q2 -; CHECK-NEXT: mov r6, r10 -; CHECK-NEXT: mov r0, r11 ; CHECK-NEXT: le lr, .LBB1_2 ; CHECK-NEXT: @ %bb.3: @ %while.cond.while.end_crit_edge -; CHECK-NEXT: add.w r1, r1, r5, lsl #1 +; CHECK-NEXT: add.w r1, r1, r9, lsl #1 ; CHECK-NEXT: mov r0, r8 ; CHECK-NEXT: .LBB1_4: @ %while.end -; CHECK-NEXT: vmlaldavax.s16 r4, r9, q0, q1 +; CHECK-NEXT: vmlaldavax.s16 r4, r11, q0, q1 ; CHECK-NEXT: vmlsldava.s16 r12, r7, q0, q1 ; CHECK-NEXT: mov r10, r4 -; CHECK-NEXT: mov r5, r9 +; CHECK-NEXT: mov r5, r11 ; CHECK-NEXT: lsrl r10, r5, #6 ; CHECK-NEXT: ldr.w r8, [sp, #36] ; CHECK-NEXT: mov r6, r12 @@ -113,20 +108,20 @@ define void @arm_cmplx_dot_prod_q15(i16* nocapture readonly %pSrcA, i16* nocaptu ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldrsh.w r5, [r0, #2] ; CHECK-NEXT: ldrsh.w r6, [r1] -; CHECK-NEXT: ldrsh.w r10, [r0] +; CHECK-NEXT: ldrsh.w r9, [r0] ; CHECK-NEXT: adds r0, #4 ; CHECK-NEXT: ldrsh.w r2, [r1, #2] ; CHECK-NEXT: adds r1, #4 -; CHECK-NEXT: smlalbb r4, r9, r6, r5 -; CHECK-NEXT: smlalbb r12, r7, r6, r10 +; CHECK-NEXT: smlalbb r4, r11, r6, r5 +; CHECK-NEXT: smlalbb r12, r7, r6, r9 ; CHECK-NEXT: muls r5, r2, r5 -; CHECK-NEXT: smlalbb r4, r9, r2, r10 +; CHECK-NEXT: smlalbb r4, r11, r2, r9 ; CHECK-NEXT: subs.w r12, r12, r5 ; CHECK-NEXT: sbc.w r7, r7, r5, asr #31 ; CHECK-NEXT: le lr, .LBB1_5 ; CHECK-NEXT: @ %bb.6: @ %while.end34.loopexit ; CHECK-NEXT: lsrl r12, r7, #6 -; CHECK-NEXT: lsrl r4, r9, #6 +; CHECK-NEXT: lsrl r4, r11, #6 ; CHECK-NEXT: mov r6, r12 ; CHECK-NEXT: mov r10, r4 ; CHECK-NEXT: .LBB1_7: @ %while.end34 @@ -301,14 +296,11 @@ define void @fma8(float* noalias nocapture readonly %A, float* noalias nocapture ; CHECK-NEXT: vldrw.u32 q2, [r6, #16] ; CHECK-NEXT: vldrw.u32 q3, [r6] ; CHECK-NEXT: vfma.f32 q2, q1, q0 -; CHECK-NEXT: vldrw.u32 q0, [r4] -; CHECK-NEXT: vldrw.u32 q1, [r5] -; CHECK-NEXT: vstrw.32 q2, [r6, #16] -; CHECK-NEXT: adds r4, #32 -; CHECK-NEXT: adds r5, #32 +; CHECK-NEXT: vldrw.u32 q0, [r4], #32 +; CHECK-NEXT: vldrw.u32 q1, [r5], #32 ; CHECK-NEXT: vfma.f32 q3, q1, q0 -; CHECK-NEXT: vstrw.32 q3, [r6] -; CHECK-NEXT: adds r6, #32 +; CHECK-NEXT: vstrw.32 q3, [r6], #32 +; CHECK-NEXT: vstrw.32 q2, [r6, #-16] ; CHECK-NEXT: le lr, .LBB2_4 ; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: cmp r12, r3 diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir index 3b157c4112a2..d69037a952eb 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir @@ -51,9 +51,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRWU32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) @@ -79,9 +78,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRHU16 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load 16, align 8) @@ -107,9 +105,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRBU8 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load 16, align 8) @@ -135,9 +132,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRBS32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[COPY]], 0, 0, $noreg :: (load 4, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg :: (load 4, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg :: (load 4, align 8) @@ -163,9 +159,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRBU32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[COPY]], 0, 0, $noreg :: (load 4, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg :: (load 4, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg :: (load 4, align 8) @@ -191,9 +186,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRHS32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[COPY]], 0, 0, $noreg :: (load 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg :: (load 8) + ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg :: (load 8, align 8) @@ -219,9 +213,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRHU32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[COPY]], 0, 0, $noreg :: (load 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg :: (load 8) + ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg :: (load 8, align 8) @@ -247,9 +240,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRBS16 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[COPY]], 0, 0, $noreg :: (load 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg :: (load 8) + ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg :: (load 8, align 8) @@ -275,9 +267,8 @@ body: | ; CHECK-LABEL: name: MVE_VLDRBU16 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[COPY]], 0, 0, $noreg :: (load 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg :: (load 8) + ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:tgpr = COPY $r0 %1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg :: (load 8, align 8) @@ -303,10 +294,9 @@ body: | ; CHECK-LABEL: name: MVE_VSTRWU32 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:gprnopc = COPY $r0 @@ -333,10 +323,9 @@ body: | ; CHECK-LABEL: name: MVE_VSTRHU16 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: MVE_VSTRHU16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:gprnopc = COPY $r0 @@ -363,10 +352,9 @@ body: | ; CHECK-LABEL: name: MVE_VSTRBU8 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 - ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: MVE_VSTRBU8 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:gprnopc = COPY $r0 @@ -394,9 +382,8 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: MVE_VSTRH32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 8) + ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:tgpr = COPY $r0 @@ -424,9 +411,8 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: MVE_VSTRB32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 4, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 4, align 8) + ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:tgpr = COPY $r0 @@ -454,9 +440,8 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store 8) + ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %1:mqpr = COPY $q0 %0:tgpr = COPY $r0 @@ -484,10 +469,9 @@ body: | ; CHECK-LABEL: name: ld0ld4 ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) @@ -516,9 +500,8 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) @@ -548,10 +531,9 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: [[MVE_VLDRWU32_2:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) @@ -582,10 +564,9 @@ body: | ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[MVE_VLDRWU32_2:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load 16, align 8) @@ -614,10 +595,9 @@ body: | ; CHECK-LABEL: name: addload ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg @@ -645,10 +625,9 @@ body: | ; CHECK-LABEL: name: sub ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: $r0 = COPY [[t2SUBri]] + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) + ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8) @@ -804,10 +783,9 @@ body: | ; CHECK-LABEL: name: addUseOK ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) + ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 @@ -872,10 +850,9 @@ body: | ; CHECK-LABEL: name: addUseKilled ; CHECK: liveins: $r0, $q0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8) - ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri killed [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8) + ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8) + ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg + ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8) ; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 %0:gprnopc = COPY $r0 diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll index 4ece7d5c0b35..d01ef0095a60 100644 --- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll @@ -1278,20 +1278,17 @@ define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16* ; CHECK-NEXT: vldrh.s32 q2, [r0, #8] ; CHECK-NEXT: vldrh.s32 q3, [r1, #8] ; CHECK-NEXT: vmul.i32 q2, q3, q2 -; CHECK-NEXT: vldrh.s32 q3, [r1] +; CHECK-NEXT: vldrh.s32 q3, [r1], #16 ; CHECK-NEXT: vshr.s32 q2, q2, #15 -; CHECK-NEXT: adds r1, #16 ; CHECK-NEXT: vmax.s32 q2, q2, q0 ; CHECK-NEXT: vmin.s32 q2, q2, q1 ; CHECK-NEXT: vstrh.32 q2, [r2, #8] -; CHECK-NEXT: vldrh.s32 q2, [r0] -; CHECK-NEXT: adds r0, #16 +; CHECK-NEXT: vldrh.s32 q2, [r0], #16 ; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vshr.s32 q2, q2, #15 ; CHECK-NEXT: vmax.s32 q2, q2, q0 ; CHECK-NEXT: vmin.s32 q2, q2, q1 -; CHECK-NEXT: vstrh.32 q2, [r2] -; CHECK-NEXT: adds r2, #16 +; CHECK-NEXT: vstrh.32 q2, [r2], #16 ; CHECK-NEXT: le lr, .LBB6_4 ; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: cmp r5, r3 @@ -2142,18 +2139,15 @@ define arm_aapcs_vfpcc void @usatmul_8_q15(i16* nocapture readonly %pSrcA, i16* ; CHECK-NEXT: vldrh.u32 q1, [r0, #8] ; CHECK-NEXT: vldrh.u32 q2, [r1, #8] ; CHECK-NEXT: vmul.i32 q1, q2, q1 -; CHECK-NEXT: vldrh.u32 q2, [r1] +; CHECK-NEXT: vldrh.u32 q2, [r1], #16 ; CHECK-NEXT: vshr.u32 q1, q1, #15 -; CHECK-NEXT: adds r1, #16 ; CHECK-NEXT: vmin.u32 q1, q1, q0 ; CHECK-NEXT: vstrh.32 q1, [r2, #8] -; CHECK-NEXT: vldrh.u32 q1, [r0] -; CHECK-NEXT: adds r0, #16 +; CHECK-NEXT: vldrh.u32 q1, [r0], #16 ; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vshr.u32 q1, q1, #15 ; CHECK-NEXT: vmin.u32 q1, q1, q0 -; CHECK-NEXT: vstrh.32 q1, [r2] -; CHECK-NEXT: adds r2, #16 +; CHECK-NEXT: vstrh.32 q1, [r2], #16 ; CHECK-NEXT: le lr, .LBB12_4 ; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: cmp r5, r3 @@ -2564,20 +2558,17 @@ define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no ; CHECK-NEXT: vldrb.s16 q2, [r0, #8] ; CHECK-NEXT: vldrb.s16 q3, [r1, #8] ; CHECK-NEXT: vmul.i16 q2, q3, q2 -; CHECK-NEXT: vldrb.s16 q3, [r1] +; CHECK-NEXT: vldrb.s16 q3, [r1], #16 ; CHECK-NEXT: vshr.s16 q2, q2, #7 -; CHECK-NEXT: adds r1, #16 ; CHECK-NEXT: vmax.s16 q2, q2, q0 ; CHECK-NEXT: vmin.s16 q2, q2, q1 ; CHECK-NEXT: vstrb.16 q2, [r2, #8] -; CHECK-NEXT: vldrb.s16 q2, [r0] -; CHECK-NEXT: adds r0, #16 +; CHECK-NEXT: vldrb.s16 q2, [r0], #16 ; CHECK-NEXT: vmul.i16 q2, q3, q2 ; CHECK-NEXT: vshr.s16 q2, q2, #7 ; CHECK-NEXT: vmax.s16 q2, q2, q0 ; CHECK-NEXT: vmin.s16 q2, q2, q1 -; CHECK-NEXT: vstrb.16 q2, [r2] -; CHECK-NEXT: adds r2, #16 +; CHECK-NEXT: vstrb.16 q2, [r2], #16 ; CHECK-NEXT: le lr, .LBB15_4 ; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: cmp r5, r3 @@ -3667,18 +3658,15 @@ define arm_aapcs_vfpcc void @usatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no ; CHECK-NEXT: vldrb.u16 q1, [r0, #8] ; CHECK-NEXT: vldrb.u16 q2, [r1, #8] ; CHECK-NEXT: vmul.i16 q1, q2, q1 -; CHECK-NEXT: vldrb.u16 q2, [r1] +; CHECK-NEXT: vldrb.u16 q2, [r1], #16 ; CHECK-NEXT: vshr.u16 q1, q1, #7 -; CHECK-NEXT: adds r1, #16 ; CHECK-NEXT: vmin.u16 q1, q1, q0 ; CHECK-NEXT: vstrb.16 q1, [r2, #8] -; CHECK-NEXT: vldrb.u16 q1, [r0] -; CHECK-NEXT: adds r0, #16 +; CHECK-NEXT: vldrb.u16 q1, [r0], #16 ; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vshr.u16 q1, q1, #7 ; CHECK-NEXT: vmin.u16 q1, q1, q0 -; CHECK-NEXT: vstrb.16 q1, [r2] -; CHECK-NEXT: adds r2, #16 +; CHECK-NEXT: vstrb.16 q1, [r2], #16 ; CHECK-NEXT: le lr, .LBB21_4 ; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: cmp r5, r3 diff --git a/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll index 5a283e46432e..11bf7b5900c7 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll @@ -68,9 +68,8 @@ define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) { ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr} -; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16] -; CHECK-NEXT: adds r0, #32 +; CHECK-NEXT: vldrw.u32 q0, [r0], #32 ; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s6, s10 @@ -151,8 +150,7 @@ define <4 x double> *@vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) { ; CHECK-LABEL: vld2_v2f64: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldrw.u32 q0, [r0, #16] -; CHECK-NEXT: vldrw.u32 q1, [r0] -; CHECK-NEXT: adds r0, #32 +; CHECK-NEXT: vldrw.u32 q1, [r0], #32 ; CHECK-NEXT: vadd.f64 d1, d0, d1 ; CHECK-NEXT: vadd.f64 d0, d2, d3 ; CHECK-NEXT: vstrw.32 q0, [r1] diff --git a/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll index 7261842cb4a5..7a9d20c5c952 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll @@ -108,12 +108,12 @@ define <8 x i64> *@vld4_v2i64(<8 x i64> *%src, <2 x i64> *%dst) { ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vldrw.u32 q3, [r0, #16] -; CHECK-NEXT: vldrw.u32 q5, [r0, #48] -; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32] +; CHECK-NEXT: vldrw.u32 q0, [r0], #64 +; CHECK-NEXT: vldrw.u32 q3, [r0, #-48] +; CHECK-NEXT: vldrw.u32 q5, [r0, #-16] +; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f64 d8, d7 -; CHECK-NEXT: adds r0, #64 ; CHECK-NEXT: vmov.f32 s17, s15 ; CHECK-NEXT: vmov.f32 s18, s22 ; CHECK-NEXT: vmov.f32 s14, s20 @@ -121,7 +121,6 @@ define <8 x i64> *@vld4_v2i64(<8 x i64> *%src, <2 x i64> *%dst) { ; CHECK-NEXT: vmov.f32 s15, s21 ; CHECK-NEXT: vmov r2, s18 ; CHECK-NEXT: vmov r3, s14 -; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vmov.f32 s2, s8 @@ -246,11 +245,10 @@ define <8 x double> *@vld4_v2f64(<8 x double> *%src, <2 x double> *%dst) { ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32] -; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vadd.f64 d0, d0, d1 ; CHECK-NEXT: vadd.f64 d1, d2, d3 ; CHECK-NEXT: vldrw.u32 q1, [r0, #16] -; CHECK-NEXT: adds r0, #64 +; CHECK-NEXT: vldrw.u32 q2, [r0], #64 ; CHECK-NEXT: vadd.f64 d2, d2, d3 ; CHECK-NEXT: vadd.f64 d3, d4, d5 ; CHECK-NEXT: vadd.f64 d1, d1, d0 diff --git a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll index 3ebf113a5c9f..a1b47029e4aa 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll @@ -29,8 +29,7 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vldrh.u16 q6, [r0, #32] ; CHECK-NEXT: vldrh.u16 q4, [r0, #48] -; CHECK-NEXT: vldrh.u16 q0, [r0] -; CHECK-NEXT: vldrh.u16 q7, [r0, #16] +; CHECK-NEXT: vldrh.u16 q0, [r0], #64 ; CHECK-NEXT: vmov r3, s24 ; CHECK-NEXT: vmovx.f16 s12, s16 ; CHECK-NEXT: vmov.16 q1[4], r3 @@ -39,6 +38,7 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n ; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vldrh.u16 q7, [r0, #-48] ; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov.16 q2[1], r3 @@ -48,7 +48,6 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n ; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vmov r2, s30 ; CHECK-NEXT: vmov.16 q2[3], r2 -; CHECK-NEXT: adds r0, #64 ; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vmov.f32 s11, s7 ; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload @@ -221,15 +220,14 @@ define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %n ; CHECK-NEXT: vmov.f32 s31, s11 ; CHECK-NEXT: vmov q2, q4 ; CHECK-NEXT: vmov.f32 s25, s21 -; CHECK-NEXT: vstrh.16 q7, [r1, #16] ; CHECK-NEXT: vmov.f32 s9, s5 -; CHECK-NEXT: vmov.f32 s27, s23 ; CHECK-NEXT: vmov.f32 s3, s15 -; CHECK-NEXT: vstrh.16 q6, [r1] ; CHECK-NEXT: vmov.f32 s11, s7 ; CHECK-NEXT: vstrh.16 q0, [r1, #32] +; CHECK-NEXT: vmov.f32 s27, s23 ; CHECK-NEXT: vstrh.16 q2, [r1, #48] -; CHECK-NEXT: adds r1, #64 +; CHECK-NEXT: vstrh.16 q6, [r1], #64 +; CHECK-NEXT: vstrh.16 q7, [r1, #-48] ; CHECK-NEXT: le lr, .LBB0_2 ; CHECK-NEXT: .LBB0_3: @ %while.end ; CHECK-NEXT: add sp, #104 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll index e461deab5276..e6bbf4d7e775 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll @@ -146,12 +146,12 @@ define <4 x double> *@vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) { ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16] -; CHECK-NEXT: add.w r0, r1, #32 ; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vmov.f64 d5, d0 ; CHECK-NEXT: vmov.f64 d0, d3 -; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1, #16] +; CHECK-NEXT: vstrw.32 q2, [r1], #32 +; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: bx lr entry: %s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll index 0378f84834b1..d8f674ac9c19 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll @@ -109,12 +109,10 @@ define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) { ; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vmov.f64 d4, d8 -; CHECK-NEXT: add.w r0, r1, #64 ; CHECK-NEXT: vmov.f32 s9, s17 ; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s11, s1 ; CHECK-NEXT: vmov.f32 s0, s18 -; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f64 d8, d6 ; CHECK-NEXT: vstrw.32 q0, [r1, #32] @@ -125,6 +123,8 @@ define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) { ; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vmov.f32 s5, s15 ; CHECK-NEXT: vstrw.32 q1, [r1, #48] +; CHECK-NEXT: vstrw.32 q2, [r1], #64 +; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: bx lr entry: @@ -218,18 +218,18 @@ define <8 x double> *@vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) { ; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32] -; CHECK-NEXT: vldrw.u32 q1, [r0, #48] -; CHECK-NEXT: vmov.f64 d4, d6 -; CHECK-NEXT: add.w r0, r1, #64 -; CHECK-NEXT: vmov.f64 d5, d0 +; CHECK-NEXT: vldrw.u32 q2, [r0, #48] +; CHECK-NEXT: vmov.f64 d2, d6 +; CHECK-NEXT: vmov.f64 d3, d0 ; CHECK-NEXT: vmov.f64 d0, d7 -; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vmov.f64 d6, d8 ; CHECK-NEXT: vstrw.32 q0, [r1, #32] -; CHECK-NEXT: vmov.f64 d7, d2 -; CHECK-NEXT: vmov.f64 d2, d9 +; CHECK-NEXT: vmov.f64 d7, d4 +; CHECK-NEXT: vmov.f64 d4, d9 ; CHECK-NEXT: vstrw.32 q3, [r1, #16] -; CHECK-NEXT: vstrw.32 q1, [r1, #48] +; CHECK-NEXT: vstrw.32 q2, [r1, #48] +; CHECK-NEXT: vstrw.32 q1, [r1], #64 +; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: bx lr entry: -- GitLab From 1f32e7367c3def75c5b7b1792ada23bc577bc893 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 22 Apr 2020 13:42:15 +0100 Subject: [PATCH 082/910] [AMDGPU] Fix test failures caused by dbdffe3ee9d. --- llvm/test/MC/AMDGPU/reg-syntax-err.s | 48 ++++++++++++++-------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/llvm/test/MC/AMDGPU/reg-syntax-err.s b/llvm/test/MC/AMDGPU/reg-syntax-err.s index 4376f5b896ff..8d58630ce888 100644 --- a/llvm/test/MC/AMDGPU/reg-syntax-err.s +++ b/llvm/test/MC/AMDGPU/reg-syntax-err.s @@ -1,73 +1,73 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI %s s_mov_b32 s1, s 1 -// NOVI: error: invalid operand for instruction +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s1, s[0 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[0:0 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s[0 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s[0:1] 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s0, 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s999 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[1:2] 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[0:2] 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s1, xnack_mask_lo 1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s s0 -// NOVI: error: invalid operand for instruction +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s1, s[0 s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[0:0 s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s[0 s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s[0:1] s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, [s0, s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s999 s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[1:2] s0 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[0:2] vcc_lo -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction s_mov_b32 s1, xnack_mask_lo s1 -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand exp mrt0 v1, v2, v3, v4000 off -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2] -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand v_add_f64 v[0:1], v[0:1], v[0x1:0xF00000002] -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand s_mov_b32 s1, s[0:-1] -// NOVI: error: failed parsing operand +// NOVI: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand -- GitLab From 41d52662d54b693c417cb0f6eb8a768672f58a8e Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 22 Apr 2020 13:58:35 +0100 Subject: [PATCH 083/910] [SveEmitter] Add support for _n form builtins The ACLE has builtins that take a scalar value that is to be expanded into a vector by the operation. While the ISA may have an instruction that takes an immediate or a scalar to represent this, the LLVM IR intrinsic may not, so Clang will have to splat the scalar value. This patch also adds the _n forms for svabd, svadd, svdiv, svdivr, svmax, svmin, svmul, svmulh, svub and svsubr. Reviewers: SjoerdMeijer, efriedma, rovka Reviewed By: SjoerdMeijer Tags: #clang Differential Revision: https://reviews.llvm.org/D77594 --- clang/include/clang/Basic/TargetBuiltins.h | 10 + clang/include/clang/Basic/arm_sve.td | 11 + clang/lib/CodeGen/CGBuiltin.cpp | 21 ++ clang/lib/CodeGen/CodeGenFunction.h | 2 +- .../aarch64-sve-intrinsics/acle_sve_abd.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_add.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_div.c | 124 +++++++++ .../aarch64-sve-intrinsics/acle_sve_divr.c | 124 +++++++++ .../aarch64-sve-intrinsics/acle_sve_max.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_min.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_mul.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_mulh.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_sub.c | 242 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_subr.c | 242 ++++++++++++++++++ clang/utils/TableGen/SveEmitter.cpp | 27 ++ 15 files changed, 2254 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 0533b1291664..d07b2d81988d 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -167,6 +167,7 @@ namespace clang { unsigned EltTypeShift; unsigned MemEltTypeShift; unsigned MergeTypeShift; + unsigned SplatOperandMaskShift; public: #define LLVM_GET_SVE_TYPEFLAGS @@ -201,6 +202,7 @@ namespace clang { EltTypeShift = llvm::countTrailingZeros(EltTypeMask); MemEltTypeShift = llvm::countTrailingZeros(MemEltTypeMask); MergeTypeShift = llvm::countTrailingZeros(MergeTypeMask); + SplatOperandMaskShift = llvm::countTrailingZeros(SplatOperandMask); } EltType getEltType() const { @@ -215,6 +217,14 @@ namespace clang { return (MergeType)((Flags & MergeTypeMask) >> MergeTypeShift); } + unsigned getSplatOperand() const { + return ((Flags & SplatOperandMask) >> SplatOperandMaskShift) - 1; + } + + bool hasSplatOperand() const { + return Flags & SplatOperandMask; + } + bool isLoad() const { return Flags & IsLoad; } bool isStore() const { return Flags & IsStore; } bool isGatherLoad() const { return Flags & IsGatherLoad; } diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 88ea0d59b394..cc579f773669 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -63,6 +63,7 @@ // d: default // c: const pointer type // P: predicate type +// a: scalar of element type (splat to vector type) // e: 1/2 width unsigned elements, 2x element count // h: 1/2 width elements, 2x element count // q: 1/4 width elements, 4x element count @@ -149,6 +150,12 @@ def FirstMergeTypeMask : FlagType<0x00000080>; // : : // : : def MergeTypeMask : FlagType<0x00000380>; +def FirstSplatOperand : FlagType<0x00000400>; +// : : +// These flags are used to specify which scalar operand +// needs to be duplicated/splatted into a vector. +// : : +def SplatOperandMask : FlagType<0x00001C00>; def IsLoad : FlagType<0x00002000>; def IsStore : FlagType<0x00004000>; def IsGatherLoad : FlagType<0x00008000>; @@ -473,6 +480,10 @@ multiclass SInstZPZZ def _M : SInst; def _X : SInst; def _Z : SInst; + + def _N_M : SInst; + def _N_X : SInst; + def _N_Z : SInst; } defm SVABD_S : SInstZPZZ<"svabd", "csil", "aarch64_sve_sabd">; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 57d57af74d18..3e24f0f53ab8 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7746,6 +7746,21 @@ Value *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E, return Builder.CreateCall(F, {Val, Predicate, BasePtr}); } +constexpr unsigned SVEBitsPerBlock = 128; + +static llvm::VectorType* getSVEVectorForElementType(llvm::Type *EltTy) { + unsigned NumElts = SVEBitsPerBlock / EltTy->getScalarSizeInBits(); + return llvm::VectorType::get(EltTy, { NumElts, true }); +} + +// Limit the usage of scalable llvm IR generated by the ACLE by using the +// sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat. +Value *CodeGenFunction::EmitSVEDupX(Value* Scalar) { + auto F = CGM.getIntrinsic(Intrinsic::aarch64_sve_dup_x, + getSVEVectorForElementType(Scalar->getType())); + return Builder.CreateCall(F, Scalar); +} + static void InsertExplicitZeroOperand(CGBuilderTy &Builder, llvm::Type *Ty, SmallVectorImpl &Ops) { auto *SplatZero = Constant::getNullValue(Ty); @@ -7816,6 +7831,12 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, } } + // Splat scalar operand to vector (intrinsics with _n infix) + if (TypeFlags.hasSplatOperand()) { + unsigned OpNo = TypeFlags.getSplatOperand(); + Ops[OpNo] = EmitSVEDupX(Ops[OpNo]); + } + // Predicated intrinsics with _z suffix need a select w/ zeroinitializer. if (TypeFlags.getMergeType() == SVETypeFlags::MergeZero) { llvm::Type *OpndTy = Ops[1]->getType(); diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 786117a1429e..6d9415d93c6f 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3909,8 +3909,8 @@ public: llvm::Type *SVEBuiltinMemEltTy(SVETypeFlags TypeFlags); llvm::Type *getEltType(SVETypeFlags TypeFlags); - llvm::VectorType *getSVEType(const SVETypeFlags &TypeFlags); + llvm::Value *EmitSVEDupX(llvm::Value *Scalar); llvm::Value *EmitSVEPredicateCast(llvm::Value *Pred, llvm::VectorType *VTy); llvm::Value *EmitSVEGatherLoad(SVETypeFlags TypeFlags, llvm::SmallVectorImpl &Ops, diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c index 31cacb585429..970dc2f23405 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c @@ -227,3 +227,245 @@ svuint64_t test_svabd_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svabd,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svabd_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svabd_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svabd_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svabd_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svabd_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svabd_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svabd_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svabd_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svabd_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svabd_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svabd_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svabd_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svabd_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svabd_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svabd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svabd_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svabd_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svabd_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svabd_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svabd_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svabd_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svabd_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svabd_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svabd_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svabd_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svabd_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svabd_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svabd_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svabd_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svabd_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svabd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svabd_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svabd_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svabd_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svabd_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svabd_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svabd_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svabd_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svabd_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svabd_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sabd.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svabd_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svabd_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svabd_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svabd_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svabd_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svabd_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svabd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svabd_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.uabd.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svabd,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c index 65a47163ff9d..2404b0a8c40e 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c @@ -227,3 +227,245 @@ svuint64_t test_svadd_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svadd,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svadd_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svadd_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svadd_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svadd_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svadd_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svadd_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svadd_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svadd_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svadd_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svadd_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svadd_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svadd_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svadd_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svadd_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svadd_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svadd_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svadd_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svadd_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svadd_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svadd_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svadd_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svadd_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svadd_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svadd_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svadd_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svadd_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svadd_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svadd_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svadd_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svadd_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svadd_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svadd_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svadd_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svadd_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svadd_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svadd_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svadd_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svadd_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svadd_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svadd_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svadd_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svadd_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svadd_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svadd_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svadd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svadd_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.add.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svadd,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c index b1786e6c1f7e..e199e8c12c19 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c @@ -121,3 +121,127 @@ svuint64_t test_svdiv_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svdiv,_u64,_x,)(pg, op1, op2); } + +svint32_t test_svdiv_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svdiv_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s64,_z,)(pg, op1, op2); +} + +svuint32_t test_svdiv_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svdiv_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u64,_z,)(pg, op1, op2); +} + +svint32_t test_svdiv_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svdiv_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s64,_m,)(pg, op1, op2); +} + +svuint32_t test_svdiv_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svdiv_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u64,_m,)(pg, op1, op2); +} + +svint32_t test_svdiv_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svdiv_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdiv.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_s64,_x,)(pg, op1, op2); +} + +svuint32_t test_svdiv_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svdiv_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdiv_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udiv.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdiv,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c index 6b67f0da4f6f..16a0b363bbd8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c @@ -121,3 +121,127 @@ svuint64_t test_svdivr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svdivr,_u64,_x,)(pg, op1, op2); } + +svint32_t test_svdivr_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svdivr_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s64,_z,)(pg, op1, op2); +} + +svuint32_t test_svdivr_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svdivr_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u64,_z,)(pg, op1, op2); +} + +svint32_t test_svdivr_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svdivr_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s64,_m,)(pg, op1, op2); +} + +svuint32_t test_svdivr_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svdivr_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u64,_m,)(pg, op1, op2); +} + +svint32_t test_svdivr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svdivr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sdivr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_s64,_x,)(pg, op1, op2); +} + +svuint32_t test_svdivr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svdivr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svdivr_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.udivr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svdivr,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c index c0591d7ebd8d..0c88d609bbe8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c @@ -227,3 +227,245 @@ svuint64_t test_svmax_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svmax,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svmax_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmax_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svmax_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmax_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svmax_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmax_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svmax_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmax_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svmax_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmax_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svmax_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmax_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svmax_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmax_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svmax_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmax_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svmax_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmax_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svmax_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmax_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svmax_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmax_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svmax_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmax_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svmax_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmax_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svmax_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmax_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svmax_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmax_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svmax_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmax_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svmax_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmax_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svmax_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmax_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svmax_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmax_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svmax_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmax_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smax.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svmax_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmax_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svmax_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmax_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svmax_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmax_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svmax_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmax_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umax.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmax,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c index ea225add73ba..3b237d9dc0d8 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c @@ -227,3 +227,245 @@ svuint64_t test_svmin_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svmin,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svmin_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmin_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svmin_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmin_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svmin_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmin_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svmin_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmin_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svmin_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmin_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svmin_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmin_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svmin_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmin_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svmin_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmin_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svmin_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmin_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svmin_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmin_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svmin_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmin_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svmin_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmin_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svmin_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmin_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svmin_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmin_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svmin_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmin_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svmin_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmin_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svmin_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmin_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svmin_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmin_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svmin_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmin_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svmin_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmin_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smin.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svmin_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmin_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svmin_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmin_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svmin_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmin_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svmin_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmin_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umin.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmin,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c index 52da1e0a92b3..b4a9f0cdfc9e 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c @@ -227,3 +227,245 @@ svuint64_t test_svmul_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svmul,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svmul_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmul_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svmul_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmul_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svmul_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmul_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svmul_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmul_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svmul_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmul_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svmul_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmul_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svmul_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmul_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svmul_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmul_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svmul_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmul_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svmul_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmul_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svmul_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmul_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svmul_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmul_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svmul_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmul_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svmul_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmul_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svmul_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmul_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svmul_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmul_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svmul_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmul_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svmul_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmul_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svmul_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmul_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svmul_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmul_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svmul_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmul_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svmul_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmul_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svmul_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmul_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svmul_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmul_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.mul.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmul,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c index 9821e425f00f..362839b8ef0f 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c @@ -227,3 +227,245 @@ svuint64_t test_svmulh_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svmulh,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svmulh_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svmulh_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svmulh_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svmulh_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svmulh_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svmulh_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svmulh_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svmulh_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svmulh_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svmulh_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svmulh_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svmulh_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svmulh_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svmulh_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svmulh_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svmulh_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svmulh_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svmulh_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svmulh_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svmulh_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.smulh.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svmulh_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svmulh_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svmulh_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svmulh_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svmulh_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.umulh.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svmulh,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c index f57247f6b0a0..63d6396eb4eb 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c @@ -227,3 +227,245 @@ svuint64_t test_svsub_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svsub,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svsub_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsub_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svsub_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsub_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svsub_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsub_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svsub_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsub_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svsub_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsub_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svsub_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsub_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svsub_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsub_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svsub_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsub_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svsub_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsub_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svsub_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsub_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svsub_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsub_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svsub_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsub_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svsub_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsub_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svsub_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsub_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svsub_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsub_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svsub_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsub_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svsub_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsub_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svsub_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsub_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svsub_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsub_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svsub_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsub_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svsub_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsub_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svsub_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsub_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svsub_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsub_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svsub_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsub_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.sub.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsub,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c index 4ed6cb39986d..6931ce309c28 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c @@ -227,3 +227,245 @@ svuint64_t test_svsubr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) // CHECK: ret %[[INTRINSIC]] return SVE_ACLE_FUNC(svsubr,_u64,_x,)(pg, op1, op2); } + +svint8_t test_svsubr_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s8,_z,)(pg, op1, op2); +} + +svint16_t test_svsubr_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s16,_z,)(pg, op1, op2); +} + +svint32_t test_svsubr_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s32,_z,)(pg, op1, op2); +} + +svint64_t test_svsubr_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s64,_z,)(pg, op1, op2); +} + +svuint8_t test_svsubr_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u8_z + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv16i8( %pg, %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u8,_z,)(pg, op1, op2); +} + +svuint16_t test_svsubr_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u16_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv8i16( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u16,_z,)(pg, op1, op2); +} + +svuint32_t test_svsubr_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u32_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv4i32( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u32,_z,)(pg, op1, op2); +} + +svuint64_t test_svsubr_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u64_z + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK-DAG: %[[SEL:.*]] = call @llvm.aarch64.sve.sel.nxv2i64( %[[PG]], %op1, zeroinitializer) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %[[SEL]], %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u64,_z,)(pg, op1, op2); +} + +svint8_t test_svsubr_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s8,_m,)(pg, op1, op2); +} + +svint16_t test_svsubr_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s16,_m,)(pg, op1, op2); +} + +svint32_t test_svsubr_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s32,_m,)(pg, op1, op2); +} + +svint64_t test_svsubr_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s64,_m,)(pg, op1, op2); +} + +svuint8_t test_svsubr_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u8_m + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u8,_m,)(pg, op1, op2); +} + +svuint16_t test_svsubr_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u16_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u16,_m,)(pg, op1, op2); +} + +svuint32_t test_svsubr_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u32_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u32,_m,)(pg, op1, op2); +} + +svuint64_t test_svsubr_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u64_m + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u64,_m,)(pg, op1, op2); +} + +svint8_t test_svsubr_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s8,_x,)(pg, op1, op2); +} + +svint16_t test_svsubr_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s16,_x,)(pg, op1, op2); +} + +svint32_t test_svsubr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s32,_x,)(pg, op1, op2); +} + +svint64_t test_svsubr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_s64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_s64,_x,)(pg, op1, op2); +} + +svuint8_t test_svsubr_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u8_x + // CHECK: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv16i8( %pg, %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u8,_x,)(pg, op1, op2); +} + +svuint16_t test_svsubr_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u16_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv8i16( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u16,_x,)(pg, op1, op2); +} + +svuint32_t test_svsubr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u32_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv4i32( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u32,_x,)(pg, op1, op2); +} + +svuint64_t test_svsubr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) +{ + // CHECK-LABEL: test_svsubr_n_u64_x + // CHECK-DAG: %[[PG:.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg) + // CHECK-DAG: %[[DUP:.*]] = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2) + // CHECK: %[[INTRINSIC:.*]] = call @llvm.aarch64.sve.subr.nxv2i64( %[[PG]], %op1, %[[DUP]]) + // CHECK: ret %[[INTRINSIC]] + return SVE_ACLE_FUNC(svsubr,_n_u64,_x,)(pg, op1, op2); +} diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index a32345e6a9d5..b51047f89db8 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -208,6 +208,21 @@ public: return BrOpen != std::string::npos && BrClose != std::string::npos; } + /// Return true if the intrinsic takes a splat operand. + bool hasSplat() const { + // These prototype modifiers are described in arm_sve.td. + return Proto.find_first_of("ajfrKLR") != std::string::npos; + } + + /// Return the parameter index of the splat operand. + unsigned getSplatIdx() const { + // These prototype modifiers are described in arm_sve.td. + auto Idx = Proto.find_first_of("ajfrKLR"); + assert(Idx != std::string::npos && Idx > 0 && + "Prototype has no splat operand"); + return Idx - 1; + } + /// Emits the intrinsic declaration to the ostream. void emitIntrinsic(raw_ostream &OS) const; @@ -278,6 +293,12 @@ public: return encodeFlag(MT, "MergeTypeMask"); } + // Returns the SVETypeFlags for the given splat operand. + unsigned encodeSplatOperand(unsigned SplatIdx) { + assert(SplatIdx < 7 && "SplatIdx out of encodable range"); + return encodeFlag(SplatIdx + 1, "SplatOperandMask"); + } + // Returns the SVETypeFlags value for the given SVEType. uint64_t encodeTypeFlags(const SVEType &T); @@ -476,6 +497,10 @@ void SVEType::applyModifier(char Mod) { Bitwidth = 16; ElementBitwidth = 1; break; + case 'a': + Bitwidth = ElementBitwidth; + NumVectors = 0; + break; case 'u': Predicate = false; Signed = false; @@ -631,6 +656,8 @@ Intrinsic::Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy, this->Flags |= Emitter.encodeTypeFlags(BaseType); this->Flags |= Emitter.encodeMemoryElementType(MemoryElementTy); this->Flags |= Emitter.encodeMergeType(MergeTy); + if (hasSplat()) + this->Flags |= Emitter.encodeSplatOperand(getSplatIdx()); } std::string Intrinsic::getBuiltinTypeStr() { -- GitLab From 8211cfb7c8bd1bedd5b3ed936d5b8f784c6bfd21 Mon Sep 17 00:00:00 2001 From: John Brawn Date: Wed, 22 Apr 2020 12:07:15 +0100 Subject: [PATCH 084/910] [ARM] Don't shrink STM if it would cause an unknown base register store If a 16-bit thumb STM with writeback stores the base register but it isn't the first register in the list, then an unknown value is stored. The load/store optimizer knows this and generates a 32-bit STM without writeback instead, but thumb2 size reduction converts it into a 16-bit STM. Fix this by having thumb2 size reduction notice such STMs and leave them as they are. Differential Revision: https://reviews.llvm.org/D78493 --- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 16 +++- llvm/test/CodeGen/Thumb/stm-deprecated.ll | 88 ++++++++++++++++++--- 2 files changed, 88 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index d3e22b75c3ee..ae661594bdc9 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -516,13 +516,23 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, isLdStMul = true; break; } - case ARM::t2STMIA: - // If the base register is killed, we don't care what its value is after the - // instruction, so we can use an updating STMIA. + case ARM::t2STMIA: { + // t2STMIA is reduced to tSTMIA_UPD which has writeback. We can only do this + // if the base register is killed, as then it doesn't matter what its value + // is after the instruction. if (!MI->getOperand(0).isKill()) return false; + // If the base register is in the register list and isn't the lowest + // numbered register (i.e. it's in operand 4 onwards) then with writeback + // the stored value is unknown, so we can't convert to tSTMIA_UPD. + Register BaseReg = MI->getOperand(0).getReg(); + for (unsigned i = 4; i < MI->getNumOperands(); ++i) + if (MI->getOperand(i).getReg() == BaseReg) + return false; + break; + } case ARM::t2LDMIA_RET: { Register BaseReg = MI->getOperand(1).getReg(); if (BaseReg != ARM::SP) diff --git a/llvm/test/CodeGen/Thumb/stm-deprecated.ll b/llvm/test/CodeGen/Thumb/stm-deprecated.ll index ffe2c0afd921..a3fd7562b9cf 100644 --- a/llvm/test/CodeGen/Thumb/stm-deprecated.ll +++ b/llvm/test/CodeGen/Thumb/stm-deprecated.ll @@ -1,19 +1,81 @@ -; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv5e-linux-gnueabi -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-T1 +; RUN: llc -mtriple=thumbv5e-linux-gnueabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-T1 +; RUN: llc -mtriple=thumbv7m -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-T2 +; RUN: llc -mtriple=thumbv7a -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-T2 -%0 = type { %0*, %0*, i32 } +%struct1 = type { %struct1*, %struct1*, i32 } +%struct2 = type { i32, i32, i32* } -@x1 = external global %0, align 4 -@x2 = external global %0, align 4 +@x1 = external global %struct1, align 4 +@x2 = external global %struct1, align 4 -; CHECK: str r0, [r1] -; CHECK-NEXT: str r1, [r1, #4] +declare void @fn1(i32, i32) +declare void @fn2(%struct2*) + +; CHECK-LABEL: test1: +; CHECK-T1: str r0, [r1] +; CHECK-T1-NEXT: str r1, [r1, #4] +; CHECK-T2: strd r0, r1, [r1] ; CHECK-NOT: stm +define void @test1(i32 %unused, %struct1* %x) { + %first = getelementptr inbounds %struct1, %struct1* %x, i32 0, i32 0 + %second = getelementptr inbounds %struct1, %struct1* %x, i32 0, i32 1 + store %struct1* @x1, %struct1** %first + store %struct1* %x, %struct1** %second + ret void +} + +; CHECK-LABEL: test2: +; CHECK-T1: str r0, [r2] +; CHECK-T1-NEXT: str r1, [r2, #4] +; CHECK-T1-NEXT: str r2, [r2, #8] +; CHECK-T2: stm.w r2, {r0, r1, r2} +; CHECK-NOT: stm r2!, {r0, r1, r2} +define i32 @test2(i32 %a, i32 %b, %struct2* %p) { +entry: + %p1 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 0 + %p2 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 1 + %p3 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 2 + store i32 %a, i32* %p1, align 4 + store i32 %b, i32* %p2, align 4 + store i32* %p1, i32** %p3, align 4 + call void @fn1(i32 %a, i32 %b) + ret i32 0 +} + +; CHECK-LABEL: test3: +; CHECK-T1: str r0, [r2] +; CHECK-T1-NEXT: str r1, [r2, #4] +; CHECK-T1-NEXT: str r2, [r2, #8] +; CHECK-T2: stm.w r2, {r0, r1, r2} +; CHECK-NOT: stm r2!, {r0, r1, r2} +define i32 @test3(i32 %a, i32 %b, %struct2* %p) { +entry: + %p1 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 0 + %p2 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 1 + %p3 = getelementptr inbounds %struct2, %struct2* %p, i32 0, i32 2 + store i32 %a, i32* %p1, align 4 + store i32 %b, i32* %p2, align 4 + store i32* %p1, i32** %p3, align 4 + %p4 = getelementptr inbounds %struct2, %struct2* %p, i32 1 + call void @fn2(%struct2* %p4) + ret i32 0 +} -define void @foo(i32 %unused, %0* %x) { - %first = getelementptr inbounds %0, %0* %x, i32 0, i32 0 - %second = getelementptr inbounds %0, %0* %x, i32 0, i32 1 - store %0* @x1, %0** %first - store %0* %x, %0** %second - unreachable +; FIXME: We should be using stm in both thumb1 and thumb2 +; CHECK-LABEL: test4: +; CHECK-T1: str r0, [r0] +; CHECK-T1-NEXT: str r1, [r0, #4] +; CHECK-T1-NEXT: str r2, [r0, #8] +; CHECK-T2: stm r0!, {r0, r1, r2} +define i32 @test4(%struct1* %p, %struct1* %q, i32 %a) { +entry: + %p1 = getelementptr inbounds %struct1, %struct1* %p, i32 0, i32 0 + %p2 = getelementptr inbounds %struct1, %struct1* %p, i32 0, i32 1 + %p3 = getelementptr inbounds %struct1, %struct1* %p, i32 0, i32 2 + store %struct1* %p, %struct1** %p1, align 4 + store %struct1* %q, %struct1** %p2, align 4 + store i32 %a, i32* %p3, align 4 + call void @fn1(i32 %a, i32 %a) + ret i32 0 } -- GitLab From bcca6ae3cd6d8b259d428767fed3b13eca3db67c Mon Sep 17 00:00:00 2001 From: jasonliu Date: Tue, 21 Apr 2020 21:52:08 +0000 Subject: [PATCH 085/910] [llvm-objdump][XCOFF] Print more symbol info in relocation Summary: Print more symbol info in relocation printing when --symbol-description is specified. Differential Revision: https://reviews.llvm.org/D78499 --- .../XCOFF/disassemble-symbol-description.test | 11 +++++++ .../tools/llvm-objdump/XCOFF/print-reloc.test | 18 +++++++++++ llvm/tools/llvm-objdump/XCOFFDump.cpp | 30 ++++++++++++++----- llvm/tools/llvm-objdump/XCOFFDump.h | 4 +-- llvm/tools/llvm-objdump/llvm-objdump.cpp | 13 ++++---- llvm/tools/llvm-objdump/llvm-objdump.h | 4 +++ 6 files changed, 63 insertions(+), 17 deletions(-) diff --git a/llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbol-description.test b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbol-description.test index 5fb74b61180e..c92772b8cbad 100644 --- a/llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbol-description.test +++ b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbol-description.test @@ -6,6 +6,9 @@ # RUN: llvm-objdump -D --symbol-description %p/Inputs/xcoff-section-headers.o | \ # RUN: FileCheck --check-prefixes=COMMON,DESC %s +# RUN: llvm-objdump -D -r --symbol-description %p/Inputs/xcoff-section-headers.o | \ +# RUN: FileCheck --check-prefixes=COMMON,DESC,RELOC %s + # xcoff-section-headers.o Compiled with IBM XL C/C++ for AIX, V16.1.0 # compiler command: xlc -qtls -o xcoff-section-headers.o -c test.c @@ -24,6 +27,7 @@ COMMON: Disassembly of section .text: PLAIN: 00000000 <.text>: DESC: 00000000 (idx: 4) .text: COMMON-NEXT: 0: 80 62 00 04 lwz 3, 4(2) +RELOC: 00000002: R_TOC (idx: 26) a[TC] COMMON-NEXT: 4: 80 63 00 00 lwz 3, 0(3) COMMON-NEXT: 8: 4e 80 00 20 blr COMMON-NEXT: c: 00 00 00 00 @@ -37,22 +41,29 @@ COMMON: Disassembly of section .data: PLAIN: 00000080 : DESC: 00000080 (idx: 22) func[TC]: COMMON-NEXT: 80: 00 00 00 94 +RELOC: 00000080: R_POS (idx: 20) func[DS] PLAIN: 00000084 : DESC: 00000084 (idx: 26) a[TC]: COMMON-NEXT: 84: 00 00 00 a4 +RELOC: 00000084: R_POS (idx: 24) a[RW] PLAIN: 00000088 : DESC: 00000088 (idx: 30) b[TC]: COMMON-NEXT: 88: 00 00 00 a0 +RELOC: 00000088: R_POS (idx: 28) b[RW] PLAIN: 0000008c : DESC: 0000008c (idx: 34) c[TC]: COMMON-NEXT: 8c: 00 00 00 08 +RELOC: 0000008c: R_TLS (idx: 32) c[UL] PLAIN: 00000090 : DESC: 00000090 (idx: 38) d[TC]: COMMON-NEXT: 90: 00 00 00 00 +RELOC: 00000090: R_TLS (idx: 36) d[TL] PLAIN: 00000094 : DESC: 00000094 (idx: 20) func[DS]: COMMON-NEXT: 94: 00 00 00 00 +RELOC: 00000094: R_POS (idx: 16) .func COMMON-NEXT: 98: 00 00 00 80 +RELOC: 00000098: R_POS (idx: 18) TOC[TC0] COMMON-NEXT: 9c: 00 00 00 00 PLAIN: 000000a0 : DESC: 000000a0 (idx: 28) b[RW]: diff --git a/llvm/test/tools/llvm-objdump/XCOFF/print-reloc.test b/llvm/test/tools/llvm-objdump/XCOFF/print-reloc.test index ee821360e5cb..2ddf97cbbb25 100644 --- a/llvm/test/tools/llvm-objdump/XCOFF/print-reloc.test +++ b/llvm/test/tools/llvm-objdump/XCOFF/print-reloc.test @@ -3,6 +3,9 @@ # RUN: llvm-objdump -r %p/Inputs/xcoff-section-headers.o | \ # RUN: FileCheck --match-full-lines --strict-whitespace %s +# RUN: llvm-objdump -r --symbol-description %p/Inputs/xcoff-section-headers.o | \ +# RUN: FileCheck --match-full-lines --strict-whitespace --check-prefix=DESCP %s + ## xcoff-section-headers.o Compiled with IBM XL C/C++ for AIX, V16.1.0 ## compiler command: xlc -qtls -o xcoff-section-headers.o -c test.c ## test.c: @@ -29,3 +32,18 @@ CHECK-EMPTY: CHECK-NEXT:00000014 R_POS .func CHECK-NEXT:00000018 R_POS TOC CHECK-EMPTY: + + DESCP:RELOCATION RECORDS FOR [.text]: + DESCP-NEXT:OFFSET TYPE VALUE + DESCP-NEXT:00000002 R_TOC (idx: 26) a[TC] +DESCP-EMPTY: + DESCP:RELOCATION RECORDS FOR [.data]: + DESCP-NEXT:OFFSET TYPE VALUE + DESCP-NEXT:00000000 R_POS (idx: 20) func[DS] + DESCP-NEXT:00000004 R_POS (idx: 24) a[RW] + DESCP-NEXT:00000008 R_POS (idx: 28) b[RW] + DESCP-NEXT:0000000c R_TLS (idx: 32) c[UL] + DESCP-NEXT:00000010 R_TLS (idx: 36) d[TL] + DESCP-NEXT:00000014 R_POS (idx: 16) .func + DESCP-NEXT:00000018 R_POS (idx: 18) TOC[TC0] +DESCP-EMPTY: diff --git a/llvm/tools/llvm-objdump/XCOFFDump.cpp b/llvm/tools/llvm-objdump/XCOFFDump.cpp index eedb8daa5f37..df37abbd3881 100644 --- a/llvm/tools/llvm-objdump/XCOFFDump.cpp +++ b/llvm/tools/llvm-objdump/XCOFFDump.cpp @@ -12,7 +12,9 @@ //===----------------------------------------------------------------------===// #include "XCOFFDump.h" -#include "llvm/MC/MCDisassembler/MCDisassembler.h" + +#include "llvm-objdump.h" +#include "llvm/Demangle/Demangle.h" using namespace llvm; using namespace llvm::object; @@ -29,7 +31,14 @@ Error objdump::getXCOFFRelocationValueString(const XCOFFObjectFile *Obj, Expected SymNameOrErr = SymI->getName(); if (!SymNameOrErr) return SymNameOrErr.takeError(); - StringRef SymName = *SymNameOrErr; + + std::string SymName = (*SymNameOrErr).str(); + if (Demangle) + SymName = demangle(SymName); + + if (SymbolDescription) + SymName = getXCOFFSymbolDescription(createSymbolInfo(Obj, *SymI), SymName); + Result.append(SymName.begin(), SymName.end()); return Error::success(); } @@ -55,20 +64,25 @@ bool objdump::isLabel(const XCOFFObjectFile *Obj, const SymbolRef &Sym) { return false; } -void objdump::printXCOFFSymbolDescription(const SymbolInfoTy &SymbolInfo, - StringRef SymbolName) { +std::string objdump::getXCOFFSymbolDescription(const SymbolInfoTy &SymbolInfo, + StringRef SymbolName) { assert(SymbolInfo.isXCOFF() && "Must be a XCOFFSymInfo."); + std::string Result; // Dummy symbols have no symbol index. if (SymbolInfo.XCOFFSymInfo.Index) - outs() << "(idx: " << SymbolInfo.XCOFFSymInfo.Index.getValue() << ") "; - - outs() << SymbolName; + Result = ("(idx: " + Twine(SymbolInfo.XCOFFSymInfo.Index.getValue()) + + ") " + SymbolName) + .str(); + else + Result.append(SymbolName.begin(), SymbolName.end()); if (SymbolInfo.XCOFFSymInfo.StorageMappingClass && !SymbolInfo.XCOFFSymInfo.IsLabel) { const XCOFF::StorageMappingClass Smc = SymbolInfo.XCOFFSymInfo.StorageMappingClass.getValue(); - outs() << "[" << XCOFF::getMappingClassString(Smc) << "]"; + Result.append(("[" + XCOFF::getMappingClassString(Smc) + "]").str()); } + + return Result; } diff --git a/llvm/tools/llvm-objdump/XCOFFDump.h b/llvm/tools/llvm-objdump/XCOFFDump.h index f4b64e7dec41..dbf520021594 100644 --- a/llvm/tools/llvm-objdump/XCOFFDump.h +++ b/llvm/tools/llvm-objdump/XCOFFDump.h @@ -22,8 +22,8 @@ getXCOFFSymbolCsectSMC(const object::XCOFFObjectFile *Obj, bool isLabel(const object::XCOFFObjectFile *Obj, const object::SymbolRef &Sym); -void printXCOFFSymbolDescription(const SymbolInfoTy &SymbolInfo, - StringRef SymbolName); +std::string getXCOFFSymbolDescription(const SymbolInfoTy &SymbolInfo, + StringRef SymbolName); Error getXCOFFRelocationValueString(const object::XCOFFObjectFile *Obj, const object::RelocationRef &RelRef, diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 4ce8f691acbc..92c130be113a 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -131,11 +131,11 @@ static cl::alias DisassembleAllShort("D", cl::NotHidden, cl::Grouping, cl::aliasopt(DisassembleAll)); -static cl::opt - SymbolDescription("symbol-description", - cl::desc("Add symbol description for disassembly. This " - "option is for XCOFF files only"), - cl::init(false), cl::cat(ObjdumpCat)); +cl::opt objdump::SymbolDescription( + "symbol-description", + cl::desc("Add symbol description for disassembly. This " + "option is for XCOFF files only"), + cl::init(false), cl::cat(ObjdumpCat)); static cl::list DisassembleSymbols("disassemble-symbols", cl::CommaSeparated, @@ -1422,8 +1422,7 @@ static void disassembleObject(const Target *TheTarget, const ObjectFile *Obj, outs() << format(Is64Bits ? "%016" PRIx64 " " : "%08" PRIx64 " ", SectionAddr + Start + VMAAdjustment); if (Obj->isXCOFF() && SymbolDescription) { - printXCOFFSymbolDescription(Symbols[SI], SymbolName); - outs() << ":\n"; + outs() << getXCOFFSymbolDescription(Symbols[SI], SymbolName) << ":\n"; } else outs() << '<' << SymbolName << ">:\n"; diff --git a/llvm/tools/llvm-objdump/llvm-objdump.h b/llvm/tools/llvm-objdump/llvm-objdump.h index 18fd9032c0d5..360ff09f1379 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.h +++ b/llvm/tools/llvm-objdump/llvm-objdump.h @@ -10,6 +10,7 @@ #include "llvm/ADT/StringSet.h" #include "llvm/DebugInfo/DIContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/Object/Archive.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" @@ -43,6 +44,7 @@ extern cl::opt PrivateHeaders; extern cl::opt Relocations; extern cl::opt SectionHeaders; extern cl::opt SectionContents; +extern cl::opt SymbolDescription; extern cl::opt SymbolTable; extern cl::opt TripleName; extern cl::opt UnwindInfo; @@ -151,6 +153,8 @@ T unwrapOrError(Expected EO, Ts &&... Args) { std::string getFileNameForError(const object::Archive::Child &C, unsigned Index); +SymbolInfoTy createSymbolInfo(const object::ObjectFile *Obj, + const object::SymbolRef &Symbol); } // end namespace llvm -- GitLab From 78aa260df742bc1fbe252bffdb7a1da0613ef116 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 22 Apr 2020 14:42:44 +0100 Subject: [PATCH 086/910] [NFC] Fix unused result of dyn_cast in non-assert build --- llvm/lib/IR/Constants.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index 338029fa00de..b86b747f7519 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -1895,8 +1895,8 @@ Constant *ConstantExpr::getPtrToInt(Constant *C, Type *DstTy, assert(DstTy->isIntOrIntVectorTy() && "PtrToInt destination must be integer or integer vector"); assert(isa(C->getType()) == isa(DstTy)); - if (auto *CVTy = dyn_cast(C->getType())) - assert(CVTy->getNumElements() == + if (isa(C->getType())) + assert(cast(C->getType())->getNumElements() == cast(DstTy)->getNumElements() && "Invalid cast between a different number of vector elements"); return getFoldedCast(Instruction::PtrToInt, C, DstTy, OnlyIfReduced); @@ -1909,8 +1909,8 @@ Constant *ConstantExpr::getIntToPtr(Constant *C, Type *DstTy, assert(DstTy->isPtrOrPtrVectorTy() && "IntToPtr destination must be a pointer or pointer vector"); assert(isa(C->getType()) == isa(DstTy)); - if (auto *CVTy = dyn_cast(C->getType())) - assert(CVTy->getNumElements() == + if (isa(C->getType())) + assert(cast(C->getType())->getNumElements() == cast(DstTy)->getNumElements() && "Invalid cast between a different number of vector elements"); return getFoldedCast(Instruction::IntToPtr, C, DstTy, OnlyIfReduced); -- GitLab From 9202902ae657b41afc12c03051629aef7ba92004 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 14:16:40 +0100 Subject: [PATCH 087/910] RuntimeDyldImpl.h - remove unused Twine forward declaration. NFC. --- llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h index 1b167558b80d..a9346536fd09 100644 --- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h +++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h @@ -36,8 +36,6 @@ using namespace llvm::object; namespace llvm { -class Twine; - #define UNIMPLEMENTED_RELOC(RelType) \ case RelType: \ return make_error("Unimplemented relocation: " #RelType) -- GitLab From 93a33bab60b29d3eed58141c3471c41a5b1bf800 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 14:36:44 +0100 Subject: [PATCH 088/910] RecordStreamer.h - cleanup includes and forward declarations. NFC. Reduce MCSymbol.h include to forward declaration. Remove unused GlobalValue foward declaration. --- llvm/lib/Object/RecordStreamer.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Object/RecordStreamer.h b/llvm/lib/Object/RecordStreamer.h index 91d272354bc0..99d15f790a15 100644 --- a/llvm/lib/Object/RecordStreamer.h +++ b/llvm/lib/Object/RecordStreamer.h @@ -13,13 +13,12 @@ #include "llvm/ADT/StringMap.h" #include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCSymbol.h" #include "llvm/Support/SMLoc.h" #include namespace llvm { -class GlobalValue; +class MCSymbol; class Module; class RecordStreamer : public MCStreamer { -- GitLab From fc044530f7f130b9b675523e3b8a196f2f4b2bfa Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 14:38:04 +0100 Subject: [PATCH 089/910] BranchFolding.h - remove unused raw_ostream forward declaration. NFC. --- llvm/lib/CodeGen/BranchFolding.h | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/CodeGen/BranchFolding.h b/llvm/lib/CodeGen/BranchFolding.h index df1d082a18c4..56c14418ec34 100644 --- a/llvm/lib/CodeGen/BranchFolding.h +++ b/llvm/lib/CodeGen/BranchFolding.h @@ -27,7 +27,6 @@ class MachineModuleInfo; class MachineRegisterInfo; class MBFIWrapper; class ProfileSummaryInfo; -class raw_ostream; class TargetInstrInfo; class TargetRegisterInfo; -- GitLab From 54b3f91d205cbd0103bf83ee97faf13c9a4cdcb3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 14:45:07 +0100 Subject: [PATCH 090/910] [BPF] Remove unused forward declarations. NFC. --- llvm/lib/Target/BPF/BPFMCInstLower.h | 2 -- llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h | 1 - llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h | 3 --- 3 files changed, 6 deletions(-) diff --git a/llvm/lib/Target/BPF/BPFMCInstLower.h b/llvm/lib/Target/BPF/BPFMCInstLower.h index 0622d20814d3..4bd0f1f0bf1c 100644 --- a/llvm/lib/Target/BPF/BPFMCInstLower.h +++ b/llvm/lib/Target/BPF/BPFMCInstLower.h @@ -18,9 +18,7 @@ class MCInst; class MCOperand; class MCSymbol; class MachineInstr; -class MachineModuleInfoMachO; class MachineOperand; -class Mangler; // BPFMCInstLower - This class is used to lower an MachineInstr into an MCInst. class LLVM_LIBRARY_VISIBILITY BPFMCInstLower { diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h index 44dcbafc10e0..3292c3e5ebb5 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h @@ -17,7 +17,6 @@ #include "llvm/MC/MCAsmInfo.h" namespace llvm { -class Target; class BPFMCAsmInfo : public MCAsmInfo { public: diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h index 1a391321f60d..4d05aad0695d 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -27,11 +27,8 @@ class MCObjectTargetWriter; class MCRegisterInfo; class MCSubtargetInfo; class MCTargetOptions; -class StringRef; class Target; -class Triple; class raw_ostream; -class raw_pwrite_stream; MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, -- GitLab From a70d2ab323a2877a0d03d9c94aa363f75984f8d5 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 22 Apr 2020 17:30:58 +0300 Subject: [PATCH 091/910] [NFC][InstCombine] Tests for negation of sign-/zero- extensions * sext of non-positive can be negated. * zext of non-negative can be negated. --- .../InstCombine/sub-of-negatible.ll | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index d676c0ba0936..83f86ca7a5e1 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -675,3 +675,150 @@ define <2 x i4> @negate_shufflevector_oneinput_extrause(<2 x i4> %x, <2 x i4> %y %t2 = sub <2 x i4> %y, %t1 ret <2 x i4> %t2 } + +; zext of non-negative can be negated +; sext of non-positive can be negated +define i16 @negation_of_zeroext_of_nonnegative(i8 %x) { +; CHECK-LABEL: @negation_of_zeroext_of_nonnegative( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 +; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] +; CHECK: nonneg_bb: +; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: neg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp sge i8 %t0, 0 + br i1 %t1, label %nonneg_bb, label %neg_bb + +nonneg_bb: + %t2 = zext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +neg_bb: + ret i16 0 +} +define i16 @negation_of_zeroext_of_positive(i8 %x) { +; CHECK-LABEL: @negation_of_zeroext_of_positive( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], 0 +; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] +; CHECK: nonneg_bb: +; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: neg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp sgt i8 %t0, 0 + br i1 %t1, label %nonneg_bb, label %neg_bb + +nonneg_bb: + %t2 = zext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +neg_bb: + ret i16 0 +} +define i16 @negation_of_signext_of_negative(i8 %x) { +; CHECK-LABEL: @negation_of_signext_of_negative( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp slt i8 [[T0]], 0 +; CHECK-NEXT: br i1 [[T1]], label [[NEG_BB:%.*]], label [[NONNEG_BB:%.*]] +; CHECK: neg_bb: +; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: nonneg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp slt i8 %t0, 0 + br i1 %t1, label %neg_bb, label %nonneg_bb + +neg_bb: + %t2 = sext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +nonneg_bb: + ret i16 0 +} +define i16 @negation_of_signext_of_nonpositive(i8 %x) { +; CHECK-LABEL: @negation_of_signext_of_nonpositive( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp slt i8 [[T0]], 1 +; CHECK-NEXT: br i1 [[T1]], label [[NEG_BB:%.*]], label [[NONNEG_BB:%.*]] +; CHECK: neg_bb: +; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: nonneg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp sle i8 %t0, 0 + br i1 %t1, label %neg_bb, label %nonneg_bb + +neg_bb: + %t2 = sext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +nonneg_bb: + ret i16 0 +} +define i16 @negation_of_signext_of_nonnegative__wrong_cast(i8 %x) { +; CHECK-LABEL: @negation_of_signext_of_nonnegative__wrong_cast( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp sgt i8 [[T0]], -1 +; CHECK-NEXT: br i1 [[T1]], label [[NONNEG_BB:%.*]], label [[NEG_BB:%.*]] +; CHECK: nonneg_bb: +; CHECK-NEXT: [[T2:%.*]] = sext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: neg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp sge i8 %t0, 0 + br i1 %t1, label %nonneg_bb, label %neg_bb + +nonneg_bb: + %t2 = sext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +neg_bb: + ret i16 0 +} +define i16 @negation_of_zeroext_of_negative_wrongcast(i8 %x) { +; CHECK-LABEL: @negation_of_zeroext_of_negative_wrongcast( +; CHECK-NEXT: [[T0:%.*]] = sub i8 0, [[X:%.*]] +; CHECK-NEXT: [[T1:%.*]] = icmp slt i8 [[T0]], 0 +; CHECK-NEXT: br i1 [[T1]], label [[NEG_BB:%.*]], label [[NONNEG_BB:%.*]] +; CHECK: neg_bb: +; CHECK-NEXT: [[T2:%.*]] = zext i8 [[T0]] to i16 +; CHECK-NEXT: [[T3:%.*]] = sub nsw i16 0, [[T2]] +; CHECK-NEXT: ret i16 [[T3]] +; CHECK: nonneg_bb: +; CHECK-NEXT: ret i16 0 +; + %t0 = sub i8 0, %x + %t1 = icmp slt i8 %t0, 0 + br i1 %t1, label %neg_bb, label %nonneg_bb + +neg_bb: + %t2 = zext i8 %t0 to i16 + %t3 = sub i16 0, %t2 + ret i16 %t3 + +nonneg_bb: + ret i16 0 +} -- GitLab From 347226d1388f3eb6478a575d8f15c83a26edac01 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 8 Apr 2020 12:26:59 -0400 Subject: [PATCH 092/910] [CMake] Add a warning message to prepare the upcoming upgrade to CMake 3.13.4 As discussed in http://lists.llvm.org/pipermail/llvm-dev/2020-March/140349.html, the minimum version of CMake required to build LLVM will be upgraded to 3.13.4 right after we create the release branch for LLVM 11.0.0. As part of this effort, this commit adds a warning to give a heads up to folks regarding the upcoming upgrade. This should allow users to upgrade their CMake in advance so that the upgrade can sail right through when the time comes. Differential Revision: https://reviews.llvm.org/D77740 --- llvm/CMakeLists.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index b483dd421b3f..29a3fbade10e 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -2,6 +2,14 @@ cmake_minimum_required(VERSION 3.4.3) +if ("${CMAKE_VERSION}" VERSION_LESS "3.13.4") + message(WARNING + "Your CMake version is ${CMAKE_VERSION}. Starting with LLVM 12.0.0, the " + "minimum version of CMake required to build LLVM will become 3.13.4, and " + "using an older CMake will become an error. Please upgrade your CMake to " + "at least 3.13.4 now to avoid issues in the future!") +endif() + if(POLICY CMP0068) cmake_policy(SET CMP0068 NEW) set(CMAKE_BUILD_WITH_INSTALL_NAME_DIR ON) -- GitLab From d482fe2add95c38691edb2c91d0f5681bebcd81d Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 22 Apr 2020 16:46:29 +0200 Subject: [PATCH 093/910] [nfc] [lldb] DWARF callbacks: DIERef -> DWARFDIE Pavel Labath wrote in D73206: The internal representation of DebugNames and Apple indexes is fixed by the relevant (pseudo-)standards, so we can't really change it. The question is how to efficiently (and cleanly) convert from the internal representation to some common thing. The conversion from AppleIndex to DIERef is trivial (which is not surprising as it was the first and the overall design was optimized for that). With debug_names, the situation gets more tricky. The internal representation of debug_names uses CU-relative DIE offsets, but DIERef wants an absolute offset. That means the index has to do more work to produce the common representation. And it needs to do that for all results, even though a lot of the index users are really interested only in a single entry. With the switch to user_id_t, _all_ indexes would have to do some extra work to encode it, only for their users to have to immediately decode it back. Having a iterator/callback based api would allow us to minimize the impact of that, as it would only need to happen for the entries that are really used. And /I think/ we could make it interface returns DWARFDies directly, and each index converts to that using the most direct approach available. Jan Kratochvil: It also makes all the callers shorter as they no longer need to fetch DWARFDIE from DIERef (and handling if not found by ReportInvalidDIERef) but the callers are already served DWARFDIE which they need. In some cases the DWARFDIE had to be fetched both by callee (DWARFIndex implementation) and caller. Differential Revision: https://reviews.llvm.org/D77970 --- .../SymbolFile/DWARF/AppleDWARFIndex.cpp | 69 ++++++------ .../SymbolFile/DWARF/AppleDWARFIndex.h | 23 ++-- .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 7 +- .../Plugins/SymbolFile/DWARF/DWARFIndex.cpp | 23 ++++ .../Plugins/SymbolFile/DWARF/DWARFIndex.h | 46 +++++--- .../SymbolFile/DWARF/DebugNamesDWARFIndex.cpp | 62 ++++++----- .../SymbolFile/DWARF/DebugNamesDWARFIndex.h | 27 ++--- .../SymbolFile/DWARF/ManualDWARFIndex.cpp | 100 +++++++++--------- .../SymbolFile/DWARF/ManualDWARFIndex.h | 23 ++-- .../SymbolFile/DWARF/SymbolFileDWARF.cpp | 73 ++----------- .../SymbolFile/DWARF/SymbolFileDWARF.h | 2 +- .../SymbolFile/DWARF/SymbolFileDWARFDwo.cpp | 2 +- .../SymbolFile/DWARF/SymbolFileDWARFDwo.h | 2 +- 13 files changed, 235 insertions(+), 224 deletions(-) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp index ad34a754ad7e..33ab11a3ca40 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.cpp @@ -53,59 +53,69 @@ std::unique_ptr AppleDWARFIndex::Create( } void AppleDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref callback) { + ConstString basename, llvm::function_ref callback) { if (!m_apple_names_up) return; - m_apple_names_up->FindByName(basename.GetStringRef(), callback); + m_apple_names_up->FindByName( + basename.GetStringRef(), + DIERefCallback(callback, basename.GetStringRef())); } void AppleDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { if (!m_apple_names_up) return; DWARFMappedHash::DIEInfoArray hash_data; m_apple_names_up->AppendAllDIEsThatMatchingRegex(regex, hash_data); - DWARFMappedHash::ExtractDIEArray(hash_data, callback); + // This is not really the DIE name. + DWARFMappedHash::ExtractDIEArray(hash_data, + DIERefCallback(callback, regex.GetText())); } void AppleDWARFIndex::GetGlobalVariables( - const DWARFUnit &cu, llvm::function_ref callback) { + const DWARFUnit &cu, llvm::function_ref callback) { if (!m_apple_names_up) return; DWARFMappedHash::DIEInfoArray hash_data; m_apple_names_up->AppendAllDIEsInRange(cu.GetOffset(), cu.GetNextUnitOffset(), hash_data); - DWARFMappedHash::ExtractDIEArray(hash_data, callback); + DWARFMappedHash::ExtractDIEArray(hash_data, DIERefCallback(callback)); } void AppleDWARFIndex::GetObjCMethods( - ConstString class_name, llvm::function_ref callback) { + ConstString class_name, llvm::function_ref callback) { if (!m_apple_objc_up) return; - m_apple_objc_up->FindByName(class_name.GetStringRef(), callback); + m_apple_objc_up->FindByName( + class_name.GetStringRef(), + DIERefCallback(callback, class_name.GetStringRef())); } void AppleDWARFIndex::GetCompleteObjCClass( ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) { + llvm::function_ref callback) { if (!m_apple_types_up) return; m_apple_types_up->FindCompleteObjCClassByName( - class_name.GetStringRef(), callback, must_be_implementation); + class_name.GetStringRef(), + DIERefCallback(callback, class_name.GetStringRef()), + must_be_implementation); } -void AppleDWARFIndex::GetTypes(ConstString name, - llvm::function_ref callback) { +void AppleDWARFIndex::GetTypes( + ConstString name, llvm::function_ref callback) { if (!m_apple_types_up) return; - m_apple_types_up->FindByName(name.GetStringRef(), callback); + m_apple_types_up->FindByName(name.GetStringRef(), + DIERefCallback(callback, name.GetStringRef())); } -void AppleDWARFIndex::GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) { +void AppleDWARFIndex::GetTypes( + const DWARFDeclContext &context, + llvm::function_ref callback) { if (!m_apple_types_up) return; @@ -125,7 +135,8 @@ void AppleDWARFIndex::GetTypes(const DWARFDeclContext &context, if (log) m_module.LogMessage(log, "FindByNameAndTagAndQualifiedNameHash()"); m_apple_types_up->FindByNameAndTagAndQualifiedNameHash( - type_name.GetStringRef(), tag, qualified_name_hash, callback); + type_name.GetStringRef(), tag, qualified_name_hash, + DIERefCallback(callback, type_name.GetStringRef())); return; } @@ -146,18 +157,23 @@ void AppleDWARFIndex::GetTypes(const DWARFDeclContext &context, if (log) m_module.LogMessage(log, "FindByNameAndTag()"); - m_apple_types_up->FindByNameAndTag(type_name.GetStringRef(), tag, callback); + m_apple_types_up->FindByNameAndTag( + type_name.GetStringRef(), tag, + DIERefCallback(callback, type_name.GetStringRef())); return; } - m_apple_types_up->FindByName(type_name.GetStringRef(), callback); + m_apple_types_up->FindByName( + type_name.GetStringRef(), + DIERefCallback(callback, type_name.GetStringRef())); } void AppleDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref callback) { + ConstString name, llvm::function_ref callback) { if (!m_apple_namespaces_up) return; - m_apple_namespaces_up->FindByName(name.GetStringRef(), callback); + m_apple_namespaces_up->FindByName( + name.GetStringRef(), DIERefCallback(callback, name.GetStringRef())); } void AppleDWARFIndex::GetFunctions( @@ -172,21 +188,14 @@ void AppleDWARFIndex::GetFunctions( void AppleDWARFIndex::GetFunctions( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { if (!m_apple_names_up) return; DWARFMappedHash::DIEInfoArray hash_data; m_apple_names_up->AppendAllDIEsThatMatchingRegex(regex, hash_data); - DWARFMappedHash::ExtractDIEArray(hash_data, callback); -} - -void AppleDWARFIndex::ReportInvalidDIERef(const DIERef &ref, - llvm::StringRef name) { - m_module.ReportErrorIfModifyDetected( - "the DWARF debug information has been modified (accelerator table had " - "bad die 0x%8.8x for '%s')\n", - ref.die_offset(), name.str().c_str()); + DWARFMappedHash::ExtractDIEArray(hash_data, + DIERefCallback(callback, regex.GetText())); } void AppleDWARFIndex::Dump(Stream &s) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h index fcb02a35bd9f..a7032f50e590 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/AppleDWARFIndex.h @@ -34,32 +34,31 @@ public: void GetGlobalVariables(ConstString basename, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const DWARFUnit &cu, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetObjCMethods(ConstString class_name, - llvm::function_ref callback) override; - void - GetCompleteObjCClass(ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) override; + llvm::function_ref callback) override; + void GetCompleteObjCClass( + ConstString class_name, bool must_be_implementation, + llvm::function_ref callback) override; void GetTypes(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetNamespaces(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetFunctions(ConstString name, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, uint32_t name_type_mask, llvm::function_ref callback) override; void GetFunctions(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; - void ReportInvalidDIERef(const DIERef &ref, llvm::StringRef name) override; void Dump(Stream &s) override; private: diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp index da7cb3be1054..1540bdbea6ab 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp @@ -2013,11 +2013,8 @@ bool DWARFASTParserClang::CompleteRecordType(const DWARFDIE &die, if (class_language == eLanguageTypeObjC) { ConstString class_name(clang_type.GetTypeName()); if (class_name) { - dwarf->GetObjCMethods(class_name, [&](DIERef die_ref) { - DWARFDebugInfo &debug_info = dwarf->DebugInfo(); - DWARFDIE method_die = debug_info.GetDIE(die_ref); - if (method_die) - method_die.ResolveType(); + dwarf->GetObjCMethods(class_name, [&](DWARFDIE method_die) { + method_die.ResolveType(); return true; }); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp index ab3fd1f59a28..683033d0ee4c 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp @@ -11,6 +11,8 @@ #include "Plugins/SymbolFile/DWARF/DWARFDIE.h" #include "Plugins/SymbolFile/DWARF/SymbolFileDWARF.h" +#include "lldb/Core/Module.h" + using namespace lldb_private; using namespace lldb; @@ -61,3 +63,24 @@ bool DWARFIndex::ProcessFunctionDIE( return true; } + +DWARFIndex::DIERefCallbackImpl::DIERefCallbackImpl( + const DWARFIndex &index, llvm::function_ref callback, + llvm::StringRef name) + : m_index(index), + m_dwarf(*llvm::cast(index.m_module.GetSymbolFile())), + m_callback(callback), m_name(name) {} + +bool DWARFIndex::DIERefCallbackImpl::operator()(DIERef ref) const { + if (DWARFDIE die = m_dwarf.GetDIE(ref)) + return m_callback(die); + m_index.ReportInvalidDIERef(ref, m_name); + return true; +} + +void DWARFIndex::ReportInvalidDIERef(DIERef ref, llvm::StringRef name) const { + m_module.ReportErrorIfModifyDetected( + "the DWARF debug information has been modified (accelerator table had " + "bad die 0x%8.8x for '%s')\n", + ref.die_offset(), name.str().c_str()); +} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h index 2181b6739a85..ecf82a910b66 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h @@ -29,35 +29,36 @@ public: /// the consumer. virtual void GetGlobalVariables(ConstString basename, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetGlobalVariables(const DWARFUnit &cu, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetObjCMethods(ConstString class_name, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetCompleteObjCClass(ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetTypes(ConstString name, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; virtual void GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) = 0; - virtual void GetNamespaces(ConstString name, - llvm::function_ref callback) = 0; + llvm::function_ref callback) = 0; + virtual void + GetNamespaces(ConstString name, + llvm::function_ref callback) = 0; virtual void GetFunctions(ConstString name, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, uint32_t name_type_mask, llvm::function_ref callback) = 0; - virtual void GetFunctions(const RegularExpression ®ex, - llvm::function_ref callback) = 0; + virtual void + GetFunctions(const RegularExpression ®ex, + llvm::function_ref callback) = 0; - virtual void ReportInvalidDIERef(const DIERef &ref, llvm::StringRef name) = 0; virtual void Dump(Stream &s) = 0; protected: @@ -72,6 +73,27 @@ protected: const CompilerDeclContext &parent_decl_ctx, uint32_t name_type_mask, llvm::function_ref callback); + + class DIERefCallbackImpl { + public: + DIERefCallbackImpl(const DWARFIndex &index, + llvm::function_ref callback, + llvm::StringRef name); + bool operator()(DIERef ref) const; + + private: + const DWARFIndex &m_index; + SymbolFileDWARF &m_dwarf; + const llvm::function_ref m_callback; + const llvm::StringRef m_name; + }; + DIERefCallbackImpl + DIERefCallback(llvm::function_ref callback, + llvm::StringRef name = {}) const { + return DIERefCallbackImpl(*this, callback, name); + } + + void ReportInvalidDIERef(DIERef ref, llvm::StringRef name) const; }; } // namespace lldb_private diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp index 23e9b0b36c04..cb3e662a6cdf 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp @@ -10,6 +10,7 @@ #include "Plugins/SymbolFile/DWARF/DWARFDebugInfo.h" #include "Plugins/SymbolFile/DWARF/DWARFDeclContext.h" #include "Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h" +#include "lldb/Core/Module.h" #include "lldb/Utility/RegularExpression.h" #include "lldb/Utility/Stream.h" @@ -59,10 +60,16 @@ DebugNamesDWARFIndex::ToDIERef(const DebugNames::Entry &entry) { bool DebugNamesDWARFIndex::ProcessEntry( const DebugNames::Entry &entry, - llvm::function_ref callback) { - if (llvm::Optional ref = ToDIERef(entry)) - return callback(*ref); - return true; + llvm::function_ref callback, llvm::StringRef name) { + llvm::Optional ref = ToDIERef(entry); + if (!ref) + return true; + SymbolFileDWARF &dwarf = + *llvm::cast(m_module.GetSymbolFile()); + DWARFDIE die = dwarf.GetDIE(*ref); + if (!die) + return true; + return callback(die); } void DebugNamesDWARFIndex::MaybeLogLookupError(llvm::Error error, @@ -77,13 +84,13 @@ void DebugNamesDWARFIndex::MaybeLogLookupError(llvm::Error error, } void DebugNamesDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref callback) { + ConstString basename, llvm::function_ref callback) { for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(basename.GetStringRef())) { if (entry.tag() != DW_TAG_variable) continue; - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, callback, basename.GetStringRef())) return; } @@ -92,7 +99,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( void DebugNamesDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { for (const DebugNames::NameIndex &ni: *m_debug_names_up) { for (DebugNames::NameTableEntry nte: ni) { if (!regex.Execute(nte.getString())) @@ -104,7 +111,8 @@ void DebugNamesDWARFIndex::GetGlobalVariables( if (entry_or->tag() != DW_TAG_variable) continue; - if (!ProcessEntry(*entry_or, callback)) + if (!ProcessEntry(*entry_or, callback, + llvm::StringRef(nte.getString()))) return; } MaybeLogLookupError(entry_or.takeError(), ni, nte.getString()); @@ -115,7 +123,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( } void DebugNamesDWARFIndex::GetGlobalVariables( - const DWARFUnit &cu, llvm::function_ref callback) { + const DWARFUnit &cu, llvm::function_ref callback) { uint64_t cu_offset = cu.GetOffset(); for (const DebugNames::NameIndex &ni: *m_debug_names_up) { for (DebugNames::NameTableEntry nte: ni) { @@ -127,7 +135,8 @@ void DebugNamesDWARFIndex::GetGlobalVariables( if (entry_or->getCUOffset() != cu_offset) continue; - if (!ProcessEntry(*entry_or, callback)) + if (!ProcessEntry(*entry_or, callback, + llvm::StringRef(nte.getString()))) return; } MaybeLogLookupError(entry_or.takeError(), ni, nte.getString()); @@ -139,7 +148,7 @@ void DebugNamesDWARFIndex::GetGlobalVariables( void DebugNamesDWARFIndex::GetCompleteObjCClass( ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) { + llvm::function_ref callback) { // Keep a list of incomplete types as fallback for when we don't find the // complete type. DIEArray incomplete_types; @@ -160,32 +169,34 @@ void DebugNamesDWARFIndex::GetCompleteObjCClass( continue; } - // FIXME: We should return DWARFDIEs so we don't have to resolve it twice. DWARFDIE die = m_debug_info.GetDIE(*ref); - if (!die) + if (!die) { + ReportInvalidDIERef(*ref, class_name.GetStringRef()); continue; + } if (die.GetAttributeValueAsUnsigned(DW_AT_APPLE_objc_complete_type, 0)) { // If we find the complete version we're done. - callback(*ref); + callback(die); return; } incomplete_types.push_back(*ref); } + auto dierefcallback = DIERefCallback(callback, class_name.GetStringRef()); for (DIERef ref : incomplete_types) - if (!callback(ref)) + if (!dierefcallback(ref)) return; m_fallback.GetCompleteObjCClass(class_name, must_be_implementation, callback); } void DebugNamesDWARFIndex::GetTypes( - ConstString name, llvm::function_ref callback) { + ConstString name, llvm::function_ref callback) { for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(name.GetStringRef())) { if (isType(entry.tag())) { - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, callback, name.GetStringRef())) return; } } @@ -195,11 +206,11 @@ void DebugNamesDWARFIndex::GetTypes( void DebugNamesDWARFIndex::GetTypes( const DWARFDeclContext &context, - llvm::function_ref callback) { - for (const DebugNames::Entry &entry : - m_debug_names_up->equal_range(context[0].name)) { + llvm::function_ref callback) { + auto name = context[0].name; + for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(name)) { if (entry.tag() == context[0].tag) { - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, callback, name)) return; } } @@ -208,11 +219,11 @@ void DebugNamesDWARFIndex::GetTypes( } void DebugNamesDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref callback) { + ConstString name, llvm::function_ref callback) { for (const DebugNames::Entry &entry : m_debug_names_up->equal_range(name.GetStringRef())) { if (entry.tag() == DW_TAG_namespace) { - if (!ProcessEntry(entry, callback)) + if (!ProcessEntry(entry, callback, name.GetStringRef())) return; } } @@ -249,7 +260,7 @@ void DebugNamesDWARFIndex::GetFunctions( void DebugNamesDWARFIndex::GetFunctions( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { for (const DebugNames::NameIndex &ni: *m_debug_names_up) { for (DebugNames::NameTableEntry nte: ni) { if (!regex.Execute(nte.getString())) @@ -262,7 +273,8 @@ void DebugNamesDWARFIndex::GetFunctions( if (tag != DW_TAG_subprogram && tag != DW_TAG_inlined_subroutine) continue; - if (!ProcessEntry(*entry_or, callback)) + if (!ProcessEntry(*entry_or, callback, + llvm::StringRef(nte.getString()))) return; } MaybeLogLookupError(entry_or.takeError(), ni, nte.getString()); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h index 204007b57b0d..5d041c36c8f2 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h @@ -27,32 +27,32 @@ public: void GetGlobalVariables(ConstString basename, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const DWARFUnit &cu, - llvm::function_ref callback) override; - void GetObjCMethods(ConstString class_name, - llvm::function_ref callback) override {} + llvm::function_ref callback) override; void - GetCompleteObjCClass(ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) override; + GetObjCMethods(ConstString class_name, + llvm::function_ref callback) override {} + void GetCompleteObjCClass( + ConstString class_name, bool must_be_implementation, + llvm::function_ref callback) override; void GetTypes(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetNamespaces(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetFunctions(ConstString name, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, uint32_t name_type_mask, llvm::function_ref callback) override; void GetFunctions(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; - void ReportInvalidDIERef(const DIERef &ref, llvm::StringRef name) override {} void Dump(Stream &s) override; private: @@ -79,7 +79,8 @@ private: llvm::Optional ToDIERef(const DebugNames::Entry &entry); bool ProcessEntry(const DebugNames::Entry &entry, - llvm::function_ref callback); + llvm::function_ref callback, + llvm::StringRef name); static void MaybeLogLookupError(llvm::Error error, const DebugNames::NameIndex &ni, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp index 3fe38e75e612..f405a2189429 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp @@ -321,53 +321,59 @@ void ManualDWARFIndex::IndexUnitImpl(DWARFUnit &unit, } void ManualDWARFIndex::GetGlobalVariables( - ConstString basename, llvm::function_ref callback) { + ConstString basename, llvm::function_ref callback) { Index(); - m_set.globals.Find(basename, callback); + m_set.globals.Find(basename, + DIERefCallback(callback, basename.GetStringRef())); } void ManualDWARFIndex::GetGlobalVariables( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { Index(); - m_set.globals.Find(regex, callback); + m_set.globals.Find(regex, DIERefCallback(callback, regex.GetText())); } void ManualDWARFIndex::GetGlobalVariables( - const DWARFUnit &unit, llvm::function_ref callback) { + const DWARFUnit &unit, llvm::function_ref callback) { Index(); - m_set.globals.FindAllEntriesForUnit(unit, callback); + m_set.globals.FindAllEntriesForUnit(unit, DIERefCallback(callback)); } void ManualDWARFIndex::GetObjCMethods( - ConstString class_name, llvm::function_ref callback) { + ConstString class_name, llvm::function_ref callback) { Index(); - m_set.objc_class_selectors.Find(class_name, callback); + m_set.objc_class_selectors.Find( + class_name, DIERefCallback(callback, class_name.GetStringRef())); } void ManualDWARFIndex::GetCompleteObjCClass( ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) { + llvm::function_ref callback) { Index(); - m_set.types.Find(class_name, callback); + m_set.types.Find(class_name, + DIERefCallback(callback, class_name.GetStringRef())); } -void ManualDWARFIndex::GetTypes(ConstString name, - llvm::function_ref callback) { +void ManualDWARFIndex::GetTypes( + ConstString name, llvm::function_ref callback) { Index(); - m_set.types.Find(name, callback); + m_set.types.Find(name, DIERefCallback(callback, name.GetStringRef())); } -void ManualDWARFIndex::GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) { +void ManualDWARFIndex::GetTypes( + const DWARFDeclContext &context, + llvm::function_ref callback) { Index(); - m_set.types.Find(ConstString(context[0].name), callback); + auto name = context[0].name; + m_set.types.Find(ConstString(name), + DIERefCallback(callback, llvm::StringRef(name))); } void ManualDWARFIndex::GetNamespaces( - ConstString name, llvm::function_ref callback) { + ConstString name, llvm::function_ref callback) { Index(); - m_set.namespaces.Find(name, callback); + m_set.namespaces.Find(name, DIERefCallback(callback, name.GetStringRef())); } void ManualDWARFIndex::GetFunctions( @@ -377,58 +383,54 @@ void ManualDWARFIndex::GetFunctions( Index(); if (name_type_mask & eFunctionNameTypeFull) { - if (!m_set.function_fullnames.Find(name, [&](DIERef die_ref) { - DWARFDIE die = dwarf.GetDIE(die_ref); - if (!die) - return true; - if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, die)) - return true; - return callback(die); - })) + if (!m_set.function_fullnames.Find( + name, DIERefCallback( + [&](DWARFDIE die) { + if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, + die)) + return true; + return callback(die); + }, + name.GetStringRef()))) return; } if (name_type_mask & eFunctionNameTypeBase) { - if (!m_set.function_basenames.Find(name, [&](DIERef die_ref) { - DWARFDIE die = dwarf.GetDIE(die_ref); - if (!die) - return true; - if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, die)) - return true; - return callback(die); - })) + if (!m_set.function_basenames.Find( + name, DIERefCallback( + [&](DWARFDIE die) { + if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, + die)) + return true; + return callback(die); + }, + name.GetStringRef()))) return; } if (name_type_mask & eFunctionNameTypeMethod && !parent_decl_ctx.IsValid()) { - if (!m_set.function_methods.Find(name, [&](DIERef die_ref) { - DWARFDIE die = dwarf.GetDIE(die_ref); - if (!die) - return true; - return callback(die); - })) + if (!m_set.function_methods.Find( + name, DIERefCallback(callback, name.GetStringRef()))) return; } if (name_type_mask & eFunctionNameTypeSelector && !parent_decl_ctx.IsValid()) { - if (!m_set.function_selectors.Find(name, [&](DIERef die_ref) { - DWARFDIE die = dwarf.GetDIE(die_ref); - if (!die) - return true; - return callback(die); - })) + if (!m_set.function_selectors.Find( + name, DIERefCallback(callback, name.GetStringRef()))) return; } } void ManualDWARFIndex::GetFunctions( const RegularExpression ®ex, - llvm::function_ref callback) { + llvm::function_ref callback) { Index(); - if (!m_set.function_basenames.Find(regex, callback)) + if (!m_set.function_basenames.Find(regex, + DIERefCallback(callback, regex.GetText()))) return; - if (!m_set.function_fullnames.Find(regex, callback)) + if (!m_set.function_fullnames.Find(regex, + DIERefCallback(callback, regex.GetText()))) return; } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h index 72a5c8ff3681..baff989eecca 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.h @@ -28,32 +28,31 @@ public: void GetGlobalVariables(ConstString basename, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetGlobalVariables(const DWARFUnit &unit, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetObjCMethods(ConstString class_name, - llvm::function_ref callback) override; - void - GetCompleteObjCClass(ConstString class_name, bool must_be_implementation, - llvm::function_ref callback) override; + llvm::function_ref callback) override; + void GetCompleteObjCClass( + ConstString class_name, bool must_be_implementation, + llvm::function_ref callback) override; void GetTypes(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetTypes(const DWARFDeclContext &context, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetNamespaces(ConstString name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; void GetFunctions(ConstString name, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, uint32_t name_type_mask, llvm::function_ref callback) override; void GetFunctions(const RegularExpression ®ex, - llvm::function_ref callback) override; + llvm::function_ref callback) override; - void ReportInvalidDIERef(const DIERef &ref, llvm::StringRef name) override {} void Dump(Stream &s) override; private: diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index b13331c4852e..5eebc9657905 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -1464,7 +1464,7 @@ SymbolFileDWARF::GetCompUnitForDWARFCompUnit(DWARFCompileUnit &dwarf_cu) { } void SymbolFileDWARF::GetObjCMethods( - ConstString class_name, llvm::function_ref callback) { + ConstString class_name, llvm::function_ref callback) { m_index->GetObjCMethods(class_name, callback); } @@ -2051,17 +2051,11 @@ void SymbolFileDWARF::FindGlobalVariables( uint32_t pruned_idx = original_size; SymbolContext sc; - m_index->GetGlobalVariables(ConstString(basename), [&](DIERef die_ref) { + m_index->GetGlobalVariables(ConstString(basename), [&](DWARFDIE die) { if (!sc.module_sp) sc.module_sp = m_objfile_sp->GetModule(); assert(sc.module_sp); - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, name.GetStringRef()); - return true; - } - if (die.Tag() != DW_TAG_variable) return true; @@ -2123,17 +2117,11 @@ void SymbolFileDWARF::FindGlobalVariables(const RegularExpression ®ex, const uint32_t original_size = variables.GetSize(); SymbolContext sc; - m_index->GetGlobalVariables(regex, [&](DIERef die_ref) { + m_index->GetGlobalVariables(regex, [&](DWARFDIE die) { if (!sc.module_sp) sc.module_sp = m_objfile_sp->GetModule(); assert(sc.module_sp); - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, regex.GetText()); - return true; - } - DWARFCompileUnit *dwarf_cu = llvm::dyn_cast(die.GetCU()); if (!dwarf_cu) return true; @@ -2292,14 +2280,8 @@ void SymbolFileDWARF::FindFunctions(const RegularExpression ®ex, regex.GetText().str().c_str()); } - DWARFDebugInfo &info = DebugInfo(); llvm::DenseSet resolved_dies; - m_index->GetFunctions(regex, [&](DIERef ref) { - DWARFDIE die = info.GetDIE(ref); - if (!die) { - m_index->ReportInvalidDIERef(ref, regex.GetText()); - return true; - } + m_index->GetFunctions(regex, [&](DWARFDIE die) { if (resolved_dies.insert(die.GetDIE()).second) ResolveFunction(die, include_inlines, sc_list); return true; @@ -2359,13 +2341,7 @@ void SymbolFileDWARF::FindTypes( if (!DeclContextMatchesThisSymbolFile(parent_decl_ctx)) return; - m_index->GetTypes(name, [&](DIERef die_ref) { - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, name.GetStringRef()); - return true; - } - + m_index->GetTypes(name, [&](DWARFDIE die) { if (!DIEInDeclContext(parent_decl_ctx, die)) return true; // The containing decl contexts don't match @@ -2427,13 +2403,7 @@ void SymbolFileDWARF::FindTypes( if (!name) return; - m_index->GetTypes(name, [&](DIERef die_ref) { - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, name.GetStringRef()); - return true; - } - + m_index->GetTypes(name, [&](DWARFDIE die) { if (!languages[GetLanguage(*die.GetCU())]) return true; @@ -2478,13 +2448,7 @@ SymbolFileDWARF::FindNamespace(ConstString name, if (!DeclContextMatchesThisSymbolFile(parent_decl_ctx)) return namespace_decl_ctx; - m_index->GetNamespaces(name, [&](DIERef die_ref) { - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, name.GetStringRef()); - return true; - } - + m_index->GetNamespaces(name, [&](DWARFDIE die) { if (!DIEInDeclContext(parent_decl_ctx, die)) return true; // The containing decl contexts don't match @@ -2650,13 +2614,7 @@ TypeSP SymbolFileDWARF::FindCompleteObjCDefinitionTypeForDIE( return type_sp; m_index->GetCompleteObjCClass( - type_name, must_be_implementation, [&](DIERef die_ref) { - DWARFDIE type_die = GetDIE(die_ref); - if (!type_die) { - m_index->ReportInvalidDIERef(die_ref, type_name.GetStringRef()); - return true; - } - + type_name, must_be_implementation, [&](DWARFDIE type_die) { bool try_resolving_type = false; // Don't try and resolve the DIE we are looking for with the DIE @@ -2827,13 +2785,7 @@ TypeSP SymbolFileDWARF::FindDefinitionTypeForDWARFDeclContext( } } - m_index->GetTypes(dwarf_decl_ctx, [&](DIERef die_ref) { - DWARFDIE type_die = GetDIE(die_ref); - if (!type_die) { - m_index->ReportInvalidDIERef(die_ref, type_name.GetStringRef()); - return true; - } - + m_index->GetTypes(dwarf_decl_ctx, [&](DWARFDIE type_die) { // Make sure type_die's langauge matches the type system we are // looking for. We don't want to find a "Foo" type from Java if we // are looking for a "Foo" type for C, C++, ObjC, or ObjC++. @@ -3055,12 +3007,7 @@ size_t SymbolFileDWARF::ParseVariablesForContext(const SymbolContext &sc) { sc.comp_unit->SetVariableList(variables); m_index->GetGlobalVariables( - dwarf_cu->GetNonSkeletonUnit(), [&](DIERef die_ref) { - DWARFDIE die = GetDIE(die_ref); - if (!die) { - m_index->ReportInvalidDIERef(die_ref, ""); - return true; - } + dwarf_cu->GetNonSkeletonUnit(), [&](DWARFDIE die) { VariableSP var_sp( ParseVariableDIE(sc, die, LLDB_INVALID_ADDRESS)); if (var_sp) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h index 255fc9093ac1..de81145e78c2 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h @@ -238,7 +238,7 @@ public: GetCompUnitForDWARFCompUnit(DWARFCompileUnit &dwarf_cu); virtual void GetObjCMethods(lldb_private::ConstString class_name, - llvm::function_ref callback); + llvm::function_ref callback); bool Supports_DW_AT_APPLE_objc_complete_type(DWARFUnit *cu); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp index 5b232021056f..3aaa7d330b84 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp @@ -97,7 +97,7 @@ SymbolFileDWARFDwo::GetForwardDeclClangTypeToDie() { void SymbolFileDWARFDwo::GetObjCMethods( lldb_private::ConstString class_name, - llvm::function_ref callback) { + llvm::function_ref callback) { GetBaseSymbolFile().GetObjCMethods(class_name, callback); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h index d43579e0e280..93538aac3c54 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h @@ -32,7 +32,7 @@ public: DWARFCompileUnit *GetDWOCompileUnitForHash(uint64_t hash); void GetObjCMethods(lldb_private::ConstString class_name, - llvm::function_ref callback) override; + llvm::function_ref callback) override; llvm::Expected GetTypeSystemForLanguage(lldb::LanguageType language) override; -- GitLab From f33e86df3a4329fa32e0f49da692acd95350b650 Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Wed, 22 Apr 2020 17:17:41 +0200 Subject: [PATCH 094/910] Fix -Wunused-variable error. --- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index d38da836eb8c..a84d23d3bb96 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2669,6 +2669,7 @@ bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) { createPostIncLoadStore(BaseAccess, IncrementOffset, NewBaseReg, TII, TRI); BaseAccess->eraseFromParent(); Increment->eraseFromParent(); + (void)BaseAccessPost; LLVM_DEBUG(dbgs() << " To : "; BaseAccessPost->dump()); for (auto *Use : SuccessorAccesses) { -- GitLab From 72a9e7c926f4e32f209e528ec407fe526da5587e Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Wed, 22 Apr 2020 10:17:32 -0500 Subject: [PATCH 095/910] [OpenMP][FIX] Do not use InaccessibleMemOrArgMemOnly for barrier and flush This was reported as PR45635. --- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 1a82d772d26a..7599a7c98175 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -389,24 +389,16 @@ __OMP_ATTRS_SET(SetterAttrs, #define __OMP_RTL_ATTRS(Name, FnAttrSet, RetAttrSet, ArgAttrSets) \ OMP_RTL_ATTRS(OMPRTL_##Name, FnAttrSet, RetAttrSet, ArgAttrSets) -__OMP_RTL_ATTRS(__kmpc_barrier, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_barrier, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_cancel, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_cancel_barrier, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_flush, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_cancel_barrier, AttributeSet(), AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_flush, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_global_thread_num, GetterAttrs, AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_fork_call, AttributeSet(EnumAttr(NoUnwind)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_omp_taskwait, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_omp_taskwait, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_omp_taskyield, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) -- GitLab From ec16df706682c064a3e38e01068d5b2512971aa4 Mon Sep 17 00:00:00 2001 From: Denis Khalikov Date: Wed, 22 Apr 2020 17:39:39 +0300 Subject: [PATCH 096/910] [mlir][vulkan-runner] Fix testsuite. Summary: Fix testsuite after D78542. Differential Revision: https://reviews.llvm.org/D78639 --- mlir/test/mlir-vulkan-runner/addf.mlir | 4 ++-- mlir/test/mlir-vulkan-runner/mulf.mlir | 2 +- mlir/test/mlir-vulkan-runner/subf.mlir | 2 +- mlir/test/mlir-vulkan-runner/time.mlir | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/mlir/test/mlir-vulkan-runner/addf.mlir b/mlir/test/mlir-vulkan-runner/addf.mlir index 3ba86ef89119..73622e37ade5 100644 --- a/mlir/test/mlir-vulkan-runner/addf.mlir +++ b/mlir/test/mlir-vulkan-runner/addf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_add(%arg0 : memref<8xf32>, %arg1 : memref<8xf32>, %arg2 : memref<8xf32>) - attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { + kernel attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32> }} { %0 = "gpu.block_id"() {dimension = "x"} : () -> index %1 = load %arg0[%0] : memref<8xf32> %2 = load %arg1[%0] : memref<8xf32> @@ -39,7 +39,7 @@ module attributes { %cst1 = constant 1 : index %cst8 = constant 8 : index - gpu.launch_func"(%cst8, %cst1, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_add } + "gpu.launch_func"(%cst8, %cst1, %cst1, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_add } : (index, index, index, index, index, index, memref<8xf32>, memref<8xf32>, memref<8xf32>) -> () %arg6 = memref_cast %arg5 : memref to memref<*xf32> call @print_memref_f32(%arg6) : (memref<*xf32>) -> () diff --git a/mlir/test/mlir-vulkan-runner/mulf.mlir b/mlir/test/mlir-vulkan-runner/mulf.mlir index 89175e803d98..be0bd5afb425 100644 --- a/mlir/test/mlir-vulkan-runner/mulf.mlir +++ b/mlir/test/mlir-vulkan-runner/mulf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_mul(%arg0 : memref<4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<4x4xf32>) - attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { + kernel attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32> }} { %x = "gpu.block_id"() {dimension = "x"} : () -> index %y = "gpu.block_id"() {dimension = "y"} : () -> index %1 = load %arg0[%x, %y] : memref<4x4xf32> diff --git a/mlir/test/mlir-vulkan-runner/subf.mlir b/mlir/test/mlir-vulkan-runner/subf.mlir index b41094653d97..5fc7e0a91d29 100644 --- a/mlir/test/mlir-vulkan-runner/subf.mlir +++ b/mlir/test/mlir-vulkan-runner/subf.mlir @@ -10,7 +10,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_sub(%arg0 : memref<8x4x4xf32>, %arg1 : memref<4x4xf32>, %arg2 : memref<8x4x4xf32>) - attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>} } kernel { + kernel attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32> }} { %x = "gpu.block_id"() {dimension = "x"} : () -> index %y = "gpu.block_id"() {dimension = "y"} : () -> index %z = "gpu.block_id"() {dimension = "z"} : () -> index diff --git a/mlir/test/mlir-vulkan-runner/time.mlir b/mlir/test/mlir-vulkan-runner/time.mlir index ffa8985d488f..9a96d7f819fd 100644 --- a/mlir/test/mlir-vulkan-runner/time.mlir +++ b/mlir/test/mlir-vulkan-runner/time.mlir @@ -13,7 +13,7 @@ module attributes { } { gpu.module @kernels { gpu.func @kernel_add(%arg0 : memref<16384xf32>, %arg1 : memref<16384xf32>, %arg2 : memref<16384xf32>) - attributes { spv.entry_point_abi = {local_size = dense<[128, 1, 1]>: vector<3xi32>} } kernel { + kernel attributes { spv.entry_point_abi = {local_size = dense<[128, 1, 1]>: vector<3xi32> }} { %bid = "gpu.block_id"() {dimension = "x"} : () -> index %tid = "gpu.thread_id"() {dimension = "x"} : () -> index %cst = constant 128 : index -- GitLab From 5a2c31116f412c3b6888be361137efd705e05814 Mon Sep 17 00:00:00 2001 From: Dmitry Vyukov Date: Wed, 22 Apr 2020 16:01:33 +0200 Subject: [PATCH 097/910] [TSAN] Add optional support for distinguishing volatiles Add support to optionally emit different instrumentation for accesses to volatile variables. While the default TSAN runtime likely will never require this feature, other runtimes for different environments that have subtly different memory models or assumptions may require distinguishing volatiles. One such environment are OS kernels, where volatile is still used in various places for various reasons, and often declare volatile to be "safe enough" even in multi-threaded contexts. One such example is the Linux kernel, which implements various synchronization primitives using volatile (READ_ONCE(), WRITE_ONCE()). Here the Kernel Concurrency Sanitizer (KCSAN) [1], is a runtime that uses TSAN instrumentation but otherwise implements a very different approach to race detection from TSAN. While in the Linux kernel it is generally discouraged to use volatiles explicitly, the topic will likely come up again, and we will eventually need to distinguish volatile accesses [2]. The other use-case is ignoring data races on specially marked variables in the kernel, for example bit-flags (here we may hide 'volatile' behind a different name such as 'no_data_race'). [1] https://github.com/google/ktsan/wiki/KCSAN [2] https://lkml.kernel.org/r/CANpmjNOfXNE-Zh3MNP=-gmnhvKbsfUfTtWkyg_=VqTxS4nnptQ@mail.gmail.com Author: melver (Marco Elver) Reviewed-in: https://reviews.llvm.org/D78554 --- .../Instrumentation/ThreadSanitizer.cpp | 45 ++++- .../ThreadSanitizer/volatile.ll | 175 ++++++++++++++++++ 2 files changed, 216 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Instrumentation/ThreadSanitizer/volatile.ll diff --git a/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp index e8882e4217aa..1ef97087330e 100644 --- a/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp @@ -68,6 +68,10 @@ static cl::opt ClInstrumentAtomics( static cl::opt ClInstrumentMemIntrinsics( "tsan-instrument-memintrinsics", cl::init(true), cl::desc("Instrument memintrinsics (memset/memcpy/memmove)"), cl::Hidden); +static cl::opt ClDistinguishVolatile( + "tsan-distinguish-volatile", cl::init(false), + cl::desc("Emit special instrumentation for accesses to volatiles"), + cl::Hidden); STATISTIC(NumInstrumentedReads, "Number of instrumented reads"); STATISTIC(NumInstrumentedWrites, "Number of instrumented writes"); @@ -118,6 +122,10 @@ private: FunctionCallee TsanWrite[kNumberOfAccessSizes]; FunctionCallee TsanUnalignedRead[kNumberOfAccessSizes]; FunctionCallee TsanUnalignedWrite[kNumberOfAccessSizes]; + FunctionCallee TsanVolatileRead[kNumberOfAccessSizes]; + FunctionCallee TsanVolatileWrite[kNumberOfAccessSizes]; + FunctionCallee TsanUnalignedVolatileRead[kNumberOfAccessSizes]; + FunctionCallee TsanUnalignedVolatileWrite[kNumberOfAccessSizes]; FunctionCallee TsanAtomicLoad[kNumberOfAccessSizes]; FunctionCallee TsanAtomicStore[kNumberOfAccessSizes]; FunctionCallee TsanAtomicRMW[AtomicRMWInst::LAST_BINOP + 1] @@ -236,6 +244,24 @@ void ThreadSanitizer::initialize(Module &M) { TsanUnalignedWrite[i] = M.getOrInsertFunction( UnalignedWriteName, Attr, IRB.getVoidTy(), IRB.getInt8PtrTy()); + SmallString<64> VolatileReadName("__tsan_volatile_read" + ByteSizeStr); + TsanVolatileRead[i] = M.getOrInsertFunction( + VolatileReadName, Attr, IRB.getVoidTy(), IRB.getInt8PtrTy()); + + SmallString<64> VolatileWriteName("__tsan_volatile_write" + ByteSizeStr); + TsanVolatileWrite[i] = M.getOrInsertFunction( + VolatileWriteName, Attr, IRB.getVoidTy(), IRB.getInt8PtrTy()); + + SmallString<64> UnalignedVolatileReadName("__tsan_unaligned_volatile_read" + + ByteSizeStr); + TsanUnalignedVolatileRead[i] = M.getOrInsertFunction( + UnalignedVolatileReadName, Attr, IRB.getVoidTy(), IRB.getInt8PtrTy()); + + SmallString<64> UnalignedVolatileWriteName( + "__tsan_unaligned_volatile_write" + ByteSizeStr); + TsanUnalignedVolatileWrite[i] = M.getOrInsertFunction( + UnalignedVolatileWriteName, Attr, IRB.getVoidTy(), IRB.getInt8PtrTy()); + Type *Ty = Type::getIntNTy(M.getContext(), BitSize); Type *PtrTy = Ty->getPointerTo(); SmallString<32> AtomicLoadName("__tsan_atomic" + BitSizeStr + "_load"); @@ -565,13 +591,24 @@ bool ThreadSanitizer::instrumentLoadOrStore(Instruction *I, const unsigned Alignment = IsWrite ? cast(I)->getAlignment() : cast(I)->getAlignment(); + const bool IsVolatile = + ClDistinguishVolatile && (IsWrite ? cast(I)->isVolatile() + : cast(I)->isVolatile()); Type *OrigTy = cast(Addr->getType())->getElementType(); const uint32_t TypeSize = DL.getTypeStoreSizeInBits(OrigTy); FunctionCallee OnAccessFunc = nullptr; - if (Alignment == 0 || Alignment >= 8 || (Alignment % (TypeSize / 8)) == 0) - OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; - else - OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; + if (Alignment == 0 || Alignment >= 8 || (Alignment % (TypeSize / 8)) == 0) { + if (IsVolatile) + OnAccessFunc = IsWrite ? TsanVolatileWrite[Idx] : TsanVolatileRead[Idx]; + else + OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; + } else { + if (IsVolatile) + OnAccessFunc = IsWrite ? TsanUnalignedVolatileWrite[Idx] + : TsanUnalignedVolatileRead[Idx]; + else + OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; + } IRB.CreateCall(OnAccessFunc, IRB.CreatePointerCast(Addr, IRB.getInt8PtrTy())); if (IsWrite) NumInstrumentedWrites++; else NumInstrumentedReads++; diff --git a/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll b/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll new file mode 100644 index 000000000000..b4849280ed25 --- /dev/null +++ b/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll @@ -0,0 +1,175 @@ +; RUN: opt < %s -tsan -tsan-distinguish-volatile -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +define i16 @test_volatile_read2(i16* %a) sanitize_thread { +entry: + %tmp1 = load volatile i16, i16* %a, align 2 + ret i16 %tmp1 +} + +; CHECK-LABEL: define i16 @test_volatile_read2(i16* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i16* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_read2(i8* %1) +; CHECK-NEXT: %tmp1 = load volatile i16, i16* %a, align 2 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i16 + +define i32 @test_volatile_read4(i32* %a) sanitize_thread { +entry: + %tmp1 = load volatile i32, i32* %a, align 4 + ret i32 %tmp1 +} + +; CHECK-LABEL: define i32 @test_volatile_read4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_read4(i8* %1) +; CHECK-NEXT: %tmp1 = load volatile i32, i32* %a, align 4 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i32 + +define i64 @test_volatile_read8(i64* %a) sanitize_thread { +entry: + %tmp1 = load volatile i64, i64* %a, align 8 + ret i64 %tmp1 +} + +; CHECK-LABEL: define i64 @test_volatile_read8(i64* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i64* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_read8(i8* %1) +; CHECK-NEXT: %tmp1 = load volatile i64, i64* %a, align 8 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i64 + +define i128 @test_volatile_read16(i128* %a) sanitize_thread { +entry: + %tmp1 = load volatile i128, i128* %a, align 16 + ret i128 %tmp1 +} + +; CHECK-LABEL: define i128 @test_volatile_read16(i128* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i128* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_read16(i8* %1) +; CHECK-NEXT: %tmp1 = load volatile i128, i128* %a, align 16 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i128 + +define void @test_volatile_write2(i16* %a) sanitize_thread { +entry: + store volatile i16 1, i16* %a, align 2 + ret void +} + +; CHECK-LABEL: define void @test_volatile_write2(i16* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i16* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_write2(i8* %1) +; CHECK-NEXT: store volatile i16 1, i16* %a, align 2 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void + +define void @test_volatile_write4(i32* %a) sanitize_thread { +entry: + store volatile i32 1, i32* %a, align 4 + ret void +} + +; CHECK-LABEL: define void @test_volatile_write4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_write4(i8* %1) +; CHECK-NEXT: store volatile i32 1, i32* %a, align 4 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void + +define void @test_volatile_write8(i64* %a) sanitize_thread { +entry: + store volatile i64 1, i64* %a, align 8 + ret void +} + +; CHECK-LABEL: define void @test_volatile_write8(i64* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i64* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_write8(i8* %1) +; CHECK-NEXT: store volatile i64 1, i64* %a, align 8 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void + +define void @test_volatile_write16(i128* %a) sanitize_thread { +entry: + store volatile i128 1, i128* %a, align 16 + ret void +} + +; CHECK-LABEL: define void @test_volatile_write16(i128* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i128* %a to i8* +; CHECK-NEXT: call void @__tsan_volatile_write16(i8* %1) +; CHECK-NEXT: store volatile i128 1, i128* %a, align 16 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void + +; Check unaligned volatile accesses + +define i32 @test_unaligned_read4(i32* %a) sanitize_thread { +entry: + %tmp1 = load volatile i32, i32* %a, align 2 + ret i32 %tmp1 +} + +; CHECK-LABEL: define i32 @test_unaligned_read4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_unaligned_volatile_read4(i8* %1) +; CHECK-NEXT: %tmp1 = load volatile i32, i32* %a, align 2 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i32 + +define void @test_unaligned_write4(i32* %a) sanitize_thread { +entry: + store volatile i32 1, i32* %a, align 1 + ret void +} + +; CHECK-LABEL: define void @test_unaligned_write4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_unaligned_volatile_write4(i8* %1) +; CHECK-NEXT: store volatile i32 1, i32* %a, align 1 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void + +; Check that regular aligned accesses are unaffected + +define i32 @test_read4(i32* %a) sanitize_thread { +entry: + %tmp1 = load i32, i32* %a, align 4 + ret i32 %tmp1 +} + +; CHECK-LABEL: define i32 @test_read4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_read4(i8* %1) +; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret i32 + +define void @test_write4(i32* %a) sanitize_thread { +entry: + store i32 1, i32* %a, align 4 + ret void +} + +; CHECK-LABEL: define void @test_write4(i32* %a) +; CHECK: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %1 = bitcast i32* %a to i8* +; CHECK-NEXT: call void @__tsan_write4(i8* %1) +; CHECK-NEXT: store i32 1, i32* %a, align 4 +; CHECK-NEXT: call void @__tsan_func_exit() +; CHECK: ret void -- GitLab From d7ab9e7c9b309ebac094bba209f7c15ad5f01768 Mon Sep 17 00:00:00 2001 From: Mikhail Maltsev Date: Wed, 22 Apr 2020 16:34:19 +0100 Subject: [PATCH 098/910] [ARM] Release notes for the Custom Datapath Extension (CDE) Summary: This change mentions CDE assembly in the LLVM release notes and CDE intrinsics in both Clang and LLVM release notes. Reviewers: kristof.beyls, simon_tatham Reviewed By: kristof.beyls Subscribers: danielkiss, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D78481 --- clang/docs/ReleaseNotes.rst | 2 ++ llvm/docs/ReleaseNotes.rst | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 6ed00a5be936..1f4bc0f0d0da 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -61,6 +61,8 @@ Non-comprehensive list of changes in this release v8.1-M MVE instruction set. ```` supports the complete API defined in the Arm C Language Extensions. +- For the ARM target, C-language intrinsics for the CDE instruction + set are now provided. * clang adds support for a set of extended integer types (``_ExtInt(N)``) that permit non-power of 2 integers, exposing the LLVM integer types. Since a major diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index aad4ea88da1e..3afdce296fcd 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -76,6 +76,11 @@ During this release ... set. ```` now supports the complete API defined in the Arm C Language Extensions. +* Added support for assembly for the optional Custom Datapath Extension (CDE) + for Arm M-profile targets. + +* Implemented C-language intrinsics for the CDE instruction set. + Changes to the MIPS Target -------------------------- -- GitLab From 5daa25fd7a184524759b6ad065a8bd7e95aa149a Mon Sep 17 00:00:00 2001 From: Francois Ferrand Date: Fri, 15 Jun 2018 14:22:23 +0200 Subject: [PATCH 099/910] clang-format: support aligned nested conditionals formatting When multiple ternary operators are chained, e.g. like an if/else-if/ else-if/.../else sequence, clang-format will keep aligning the colon with the question mark, which increases the indent for each conditionals: int a = condition1 ? result1 : condition2 ? result2 : condition3 ? result3 : result4; This patch detects the situation (e.g. conditionals used in false branch of another conditional), to avoid indenting in that case: int a = condition1 ? result1 : condition2 ? result2 : condition3 ? result3 : result4; When BreakBeforeTernaryOperators is false, this will format like this: int a = condition1 ? result1 : condition2 ? result2 : conditino3 ? result3 : result4; --- clang/lib/Format/ContinuationIndenter.cpp | 47 ++++- clang/lib/Format/ContinuationIndenter.h | 29 ++- clang/lib/Format/WhitespaceManager.cpp | 85 ++++++++- clang/lib/Format/WhitespaceManager.h | 17 +- clang/unittests/Format/FormatTest.cpp | 211 ++++++++++++++++++++++ 5 files changed, 365 insertions(+), 24 deletions(-) diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index e70ae7efb0c3..8f1089dc81cb 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -367,6 +367,12 @@ bool ContinuationIndenter::mustBreak(const LineState &State) { State.Stack.back().BreakBeforeParameter && !Current.isTrailingComment() && !Current.isOneOf(tok::r_paren, tok::r_brace)) return true; + if (State.Stack.back().IsChainedConditional && + ((Style.BreakBeforeTernaryOperators && Current.is(TT_ConditionalExpr) && + Current.is(tok::colon)) || + (!Style.BreakBeforeTernaryOperators && Previous.is(TT_ConditionalExpr) && + Previous.is(tok::colon)))) + return true; if (((Previous.is(TT_DictLiteral) && Previous.is(tok::l_brace)) || (Previous.is(TT_ArrayInitializerLSquare) && Previous.ParameterCount > 1) || @@ -1022,8 +1028,21 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) { if (State.Stack.back().QuestionColumn != 0 && ((NextNonComment->is(tok::colon) && NextNonComment->is(TT_ConditionalExpr)) || - Previous.is(TT_ConditionalExpr))) + Previous.is(TT_ConditionalExpr))) { + if (((NextNonComment->is(tok::colon) && NextNonComment->Next && + !NextNonComment->Next->FakeLParens.empty() && + NextNonComment->Next->FakeLParens.back() == prec::Conditional) || + (Previous.is(tok::colon) && !Current.FakeLParens.empty() && + Current.FakeLParens.back() == prec::Conditional)) && + !State.Stack.back().IsWrappedConditional) { + //NOTE: we may tweak this slightly: + // * not remove the 'lead' ContinuationIndentWidth + // * always un-indent by the operator when BreakBeforeTernaryOperators=true + unsigned Indent = State.Stack.back().Indent - Style.ContinuationIndentWidth; + return Indent; + } return State.Stack.back().QuestionColumn; + } if (Previous.is(tok::comma) && State.Stack.back().VariablePos != 0) return State.Stack.back().VariablePos; if ((PreviousNonComment && @@ -1144,6 +1163,10 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, if (Current.is(TT_ArraySubscriptLSquare) && State.Stack.back().StartOfArraySubscripts == 0) State.Stack.back().StartOfArraySubscripts = State.Column; + if (Current.is(TT_ConditionalExpr) && Current.is(tok::question) && + ((Current.MustBreakBefore) || + (Current.getNextNonComment() && Current.getNextNonComment()->MustBreakBefore))) + State.Stack.back().IsWrappedConditional = true; if (Style.BreakBeforeTernaryOperators && Current.is(tok::question)) State.Stack.back().QuestionColumn = State.Column; if (!Style.BreakBeforeTernaryOperators && Current.isNot(tok::colon)) { @@ -1284,6 +1307,8 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, NewParenState.Tok = nullptr; NewParenState.ContainsLineBreak = false; NewParenState.LastOperatorWrapped = true; + NewParenState.IsChainedConditional = false; + NewParenState.IsWrappedConditional = false; NewParenState.NoLineBreak = NewParenState.NoLineBreak || State.Stack.back().NoLineBreakInOperand; @@ -1316,14 +1341,20 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, Style.AlignAfterOpenBracket != FormatStyle::BAS_DontAlign) NewParenState.StartOfFunctionCall = State.Column; - // Always indent conditional expressions. Never indent expression where - // the 'operator' is ',', ';' or an assignment (i.e. *I <= - // prec::Assignment) as those have different indentation rules. Indent - // other expression, unless the indentation needs to be skipped. - if (*I == prec::Conditional || - (!SkipFirstExtraIndent && *I > prec::Assignment && - !Current.isTrailingComment())) + // Indent conditional expressions, unless they are chained "else-if" + // conditionals. Never indent expression where the 'operator' is ',', ';' or + // an assignment (i.e. *I <= prec::Assignment) as those have different + // indentation rules. Indent other expression, unless the indentation needs + // to be skipped. + if (*I == prec::Conditional && Previous && Previous->is(tok::colon) && + Previous->is(TT_ConditionalExpr) && I == Current.FakeLParens.rbegin() && + !State.Stack.back().IsWrappedConditional) { + NewParenState.IsChainedConditional = true; + } else if (*I == prec::Conditional || + (!SkipFirstExtraIndent && *I > prec::Assignment && + !Current.isTrailingComment())) { NewParenState.Indent += Style.ContinuationIndentWidth; + } if ((Previous && !Previous->opensScope()) || *I != prec::Comma) NewParenState.BreakBeforeParameter = false; State.Stack.push_back(NewParenState); diff --git a/clang/lib/Format/ContinuationIndenter.h b/clang/lib/Format/ContinuationIndenter.h index 5ad4548529d7..67de57601f8f 100644 --- a/clang/lib/Format/ContinuationIndenter.h +++ b/clang/lib/Format/ContinuationIndenter.h @@ -202,14 +202,15 @@ struct ParenState { ParenState(const FormatToken *Tok, unsigned Indent, unsigned LastSpace, bool AvoidBinPacking, bool NoLineBreak) : Tok(Tok), Indent(Indent), LastSpace(LastSpace), - NestedBlockIndent(Indent), IsAligned(false), - BreakBeforeClosingBrace(false), AvoidBinPacking(AvoidBinPacking), - BreakBeforeParameter(false), NoLineBreak(NoLineBreak), - NoLineBreakInOperand(false), LastOperatorWrapped(true), - ContainsLineBreak(false), ContainsUnwrappedBuilder(false), - AlignColons(true), ObjCSelectorNameFound(false), - HasMultipleNestedBlocks(false), NestedBlockInlined(false), - IsInsideObjCArrayLiteral(false), IsCSharpGenericTypeConstraint(false) {} + NestedBlockIndent(Indent), BreakBeforeClosingBrace(false), + AvoidBinPacking(AvoidBinPacking), BreakBeforeParameter(false), + NoLineBreak(NoLineBreak), NoLineBreakInOperand(false), + LastOperatorWrapped(true), ContainsLineBreak(false), + ContainsUnwrappedBuilder(false), AlignColons(true), + ObjCSelectorNameFound(false), HasMultipleNestedBlocks(false), + NestedBlockInlined(false), IsInsideObjCArrayLiteral(false), + IsCSharpGenericTypeConstraint(false), IsChainedConditional(false), + IsWrappedConditional(false) {} /// \brief The token opening this parenthesis level, or nullptr if this level /// is opened by fake parenthesis. @@ -335,6 +336,14 @@ struct ParenState { bool IsCSharpGenericTypeConstraint : 1; + /// \brief true if the current \c ParenState represents the false branch of + /// a chained conditional expression (e.g. else-if) + bool IsChainedConditional : 1; + + /// \brief true if there conditionnal was wrapped on the first operator (the + /// question mark) + bool IsWrappedConditional : 1; + bool operator<(const ParenState &Other) const { if (Indent != Other.Indent) return Indent < Other.Indent; @@ -376,6 +385,10 @@ struct ParenState { return NestedBlockInlined; if (IsCSharpGenericTypeConstraint != Other.IsCSharpGenericTypeConstraint) return IsCSharpGenericTypeConstraint; + if (IsChainedConditional != Other.IsChainedConditional) + return IsChainedConditional; + if (IsWrappedConditional != Other.IsWrappedConditional) + return IsWrappedConditional; return false; } }; diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index bc71a89fc92b..ac033c023f6e 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -95,6 +95,7 @@ const tooling::Replacements &WhitespaceManager::generateReplacements() { alignConsecutiveMacros(); alignConsecutiveDeclarations(); alignConsecutiveAssignments(); + alignChainedConditionals(); alignTrailingComments(); alignEscapedNewlines(); generateChanges(); @@ -227,6 +228,32 @@ void WhitespaceManager::calculateLineBreakInformation() { LastBlockComment = nullptr; } } + + // Compute conditional nesting level + // Level is increased for each conditional, unless this conditional continues + // a chain of conditional, i.e. starts immediately after the colon of another + // conditional. + SmallVector ScopeStack; + int ConditionalsLevel = 0; + for (auto &Change : Changes) { + for (unsigned i = 0, e = Change.Tok->FakeLParens.size(); i != e; ++i) { + bool isNestedConditional = + Change.Tok->FakeLParens[e - 1 - i] == prec::Conditional && + !(i == 0 && Change.Tok->Previous && + Change.Tok->Previous->is(TT_ConditionalExpr) && + Change.Tok->Previous->is(tok::colon)); + if (isNestedConditional) + ++ConditionalsLevel; + ScopeStack.push_back(isNestedConditional); + } + + Change.ConditionalsLevel = ConditionalsLevel; + + for (unsigned i = Change.Tok->FakeRParens; i > 0 && ScopeStack.size(); --i) { + if (ScopeStack.pop_back_val()) + --ConditionalsLevel; + } + } } // Align a single sequence of tokens, see AlignTokens below. @@ -248,6 +275,7 @@ AlignTokenSequence(unsigned Start, unsigned End, unsigned Column, F &&Matches, // double z); // In the above example, we need to take special care to ensure that // 'double z' is indented along with it's owning function 'b'. + // Special handling is required for 'nested' ternary operators. SmallVector ScopeStack; for (unsigned i = Start; i != End; ++i) { @@ -288,7 +316,10 @@ AlignTokenSequence(unsigned Start, unsigned End, unsigned Column, F &&Matches, unsigned ScopeStart = ScopeStack.back(); if (Changes[ScopeStart - 1].Tok->is(TT_FunctionDeclarationName) || (ScopeStart > Start + 1 && - Changes[ScopeStart - 2].Tok->is(TT_FunctionDeclarationName))) + Changes[ScopeStart - 2].Tok->is(TT_FunctionDeclarationName)) || + Changes[i].Tok->is(TT_ConditionalExpr) || + (Changes[i].Tok->Previous && + Changes[i].Tok->Previous->is(TT_ConditionalExpr))) Changes[i].Spaces += Shift; } @@ -341,7 +372,7 @@ static unsigned AlignTokens(const FormatStyle &Style, F &&Matches, // abort when we hit any token in a higher scope than the starting one. auto IndentAndNestingLevel = StartAt < Changes.size() ? Changes[StartAt].indentAndNestingLevel() - : std::pair(0, 0); + : std::tuple(); // Keep track of the number of commas before the matching tokens, we will only // align a sequence of matching tokens if they are preceded by the same number @@ -409,8 +440,8 @@ static unsigned AlignTokens(const FormatStyle &Style, F &&Matches, StartOfSequence = i; unsigned ChangeMinColumn = Changes[i].StartOfTokenColumn; - int LineLengthAfter = -Changes[i].Spaces; - for (unsigned j = i; j != e && Changes[j].NewlinesBefore == 0; ++j) + int LineLengthAfter = Changes[i].TokenLength; + for (unsigned j = i + 1; j != e && Changes[j].NewlinesBefore == 0; ++j) LineLengthAfter += Changes[j].Spaces + Changes[j].TokenLength; unsigned ChangeMaxColumn = Style.ColumnLimit - LineLengthAfter; @@ -608,6 +639,52 @@ void WhitespaceManager::alignConsecutiveDeclarations() { Changes, /*StartAt=*/0); } +void WhitespaceManager::alignChainedConditionals() +{ + if (Style.BreakBeforeTernaryOperators) { + AlignTokens(Style, + [](Change const &C) { + // Align question operators and last colon + return C.Tok->is(TT_ConditionalExpr) && + ((C.Tok->is(tok::question) && !C.NewlinesBefore) || + (C.Tok->is(tok::colon) && C.Tok->Next && + (C.Tok->Next->FakeLParens.size() == 0 || + C.Tok->Next->FakeLParens.back() != + prec::Conditional))); + }, + Changes, /*StartAt=*/0); + } else { + static auto AlignWrappedOperand = [](Change const &C) { + auto Previous = C.Tok->getPreviousNonComment();//Previous; + return C.NewlinesBefore && Previous && Previous->is(TT_ConditionalExpr) && + (Previous->is(tok::question) || + (Previous->is(tok::colon) && + (C.Tok->FakeLParens.size() == 0 || + C.Tok->FakeLParens.back() != prec::Conditional))); + }; + // Ensure we keep alignment of wrapped operands with non-wrapped operands + // Since we actually align the operators, the wrapped operands need the + // extra offset to be properly aligned. + for (Change & C: Changes) { + if (AlignWrappedOperand(C)) + C.StartOfTokenColumn -= 2; + } + AlignTokens(Style, + [this](Change const &C) { + // Align question operators if next operand is not wrapped, as + // well as wrapped operands after question operator or last + // colon in conditional sequence + return (C.Tok->is(TT_ConditionalExpr) && + C.Tok->is(tok::question) && + &C != &Changes.back() && + (&C + 1)->NewlinesBefore == 0 && + !(&C + 1)->IsTrailingComment) || + AlignWrappedOperand(C); + }, + Changes, /*StartAt=*/0); + } +} + void WhitespaceManager::alignTrailingComments() { unsigned MinColumn = 0; unsigned MaxColumn = UINT_MAX; diff --git a/clang/lib/Format/WhitespaceManager.h b/clang/lib/Format/WhitespaceManager.h index a9f83920801f..87f24e97f0fb 100644 --- a/clang/lib/Format/WhitespaceManager.h +++ b/clang/lib/Format/WhitespaceManager.h @@ -19,6 +19,7 @@ #include "clang/Basic/SourceManager.h" #include "clang/Format/Format.h" #include +#include namespace clang { namespace format { @@ -158,11 +159,16 @@ public: const Change *StartOfBlockComment; int IndentationOffset; - // A combination of indent level and nesting level, which are used in - // tandem to compute lexical scope, for the purposes of deciding + // Depth of conditionals. Computed from tracking fake parenthesis, except + // it does not increase the indent for "chained" conditionals. + int ConditionalsLevel; + + // A combination of indent, nesting and conditionals levels, which are used + // in tandem to compute lexical scope, for the purposes of deciding // when to stop consecutive alignment runs. - std::pair indentAndNestingLevel() const { - return std::make_pair(Tok->IndentLevel, Tok->NestingLevel); + std::tuple indentAndNestingLevel() const { + return std::make_tuple(Tok->IndentLevel, Tok->NestingLevel, + ConditionalsLevel); } }; @@ -181,6 +187,9 @@ private: /// Align consecutive declarations over all \c Changes. void alignConsecutiveDeclarations(); + /// Align consecutive declarations over all \c Changes. + void alignChainedConditionals(); + /// Align trailing comments over all \c Changes. void alignTrailingComments(); diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 69a2001cd995..1206cedf70f1 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -5950,6 +5950,113 @@ TEST_F(FormatTest, BreaksConditionalExpressions) { " // comment\n" " ? a = b\n" " : a;"); + + // Chained conditionals + FormatStyle Style = getLLVMStyle(); + Style.ColumnLimit = 70; + Style.AlignOperands = true; + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 222222\n" + " : 333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : cccccccccccccc ? 3333333333333333\n" + " : 4444444444444444;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaa ? bbb : ccc)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : (aaa ? bbb : ccc);", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccccc)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccccc)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? a = (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : dddddddddddddddddd)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? a + (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : dddddddddddddddddd)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : a + (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : dddddddddddddddddd)\n", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccccc);", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : ccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : ccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee)\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccccc\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee\n" + " : bbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaa\n" + " ? (aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee)\n" + " : bbbbbbbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaaaaaa\n" + " ? aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : cccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee\n" + " : bbbbbbbbbbbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); } TEST_F(FormatTest, BreaksConditionalExpressionsAfterOperator) { @@ -6055,6 +6162,110 @@ TEST_F(FormatTest, BreaksConditionalExpressionsAfterOperator) { " aaaaa :\n" " bbbbbbbbbbbbbbb + cccccccccccccccc;", Style); + + // Chained conditionals + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 222222 :\n" + " 333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " cccccccccccccccc ? 3333333333333333 :\n" + " 4444444444444444;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaa ? bbb : ccc) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " (aaa ? bbb : ccc);", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? a = (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " dddddddddddddddddd) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? a + (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " dddddddddddddddddd) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " a + (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " dddddddddddddddddd)\n", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111 :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc);", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " ccccccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " ccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " ccccccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee) :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee :\n" + " bbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaa ?\n" + " (aaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee) :\n" + " bbbbbbbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaa ?\n" + " aaaaaaaaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb :\n" + " cccccccccccccccccccc ? dddddddddddddddddd :\n" + " eeeeeeeeeeeeeeeeee :\n" + " bbbbbbbbbbbbbbbbbbbbb ? 2222222222222222 :\n" + " 3333333333333333;", + Style); } TEST_F(FormatTest, DeclarationsOfMultipleVariables) { -- GitLab From 3d61b1120e8267aa39f4c9a33d618dbaec4ec6fa Mon Sep 17 00:00:00 2001 From: Francois Ferrand Date: Mon, 22 May 2017 11:23:08 +0200 Subject: [PATCH 100/910] clang-format: Introduce stricter AlignOperands flag Summary: Even when BreakBeforeBinaryOperators is set, AlignOperands kept aligning the beginning of the line, even when it could align the actual operands (e.g. after an assignment). With this patch, there is an option to actually align the operands, so that the operator gets right-aligned with the equal sign or return operator: int aaaaa = bbbbbb + cccccc; return aaaaaaa && bbbbbbb; This not happen in parentheses, to avoid 'breaking' the indentation: if (aaaaa && bbbbb) return; Reviewers: krasimir, djasper Subscribers: cfe-commits, klimek Differential Revision: https://reviews.llvm.org/D32478 --- clang/docs/ClangFormatStyleOptions.rst | 44 +++++++- clang/include/clang/Format/Format.h | 43 +++++-- clang/lib/Format/ContinuationIndenter.cpp | 33 +++++- clang/lib/Format/ContinuationIndenter.h | 8 +- clang/lib/Format/Format.cpp | 20 +++- clang/unittests/Format/FormatTest.cpp | 130 ++++++++++++++++++++-- clang/unittests/Format/FormatTestJS.cpp | 2 +- 7 files changed, 248 insertions(+), 32 deletions(-) diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 6d486224e3c2..e5a69fdb9c5a 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -270,17 +270,49 @@ the configuration (without a prefix: ``Auto``). -**AlignOperands** (``bool``) +**AlignOperands** (``OperandAlignmentStyle``) If ``true``, horizontally align operands of binary and ternary expressions. - Specifically, this aligns operands of a single expression that needs to be - split over multiple lines, e.g.: + Possible values: + + * ``OAS_DontAlign`` (in configuration: ``DontAlign``) + Do not align operands of binary and ternary expressions. + The wrapped lines are indented ``ContinuationIndentWidth`` spaces from + the start of the line. + + * ``OAS_Align`` (in configuration: ``Align``) + Horizontally align operands of binary and ternary expressions. + + Specifically, this aligns operands of a single expression that needs + to be split over multiple lines, e.g.: + + .. code-block:: c++ + + int aaa = bbbbbbbbbbbbbbb + + ccccccccccccccc; + + When ``BreakBeforeBinaryOperators`` is set, the wrapped operator is + aligned with the operand on the first line. + + .. code-block:: c++ + + int aaa = bbbbbbbbbbbbbbb + + ccccccccccccccc; + + * ``OAS_AlignAfterOperator`` (in configuration: ``AlignAfterOperator``) + Horizontally align operands of binary and ternary expressions. + + This is similar to ``AO_Align``, except when + ``BreakBeforeBinaryOperators`` is set, the operator is un-indented so + that the wrapped operand is aligned with the operand on the first line. + + .. code-block:: c++ + + int aaa = bbbbbbbbbbbbbbb + + ccccccccccccccc; - .. code-block:: c++ - int aaa = bbbbbbbbbbbbbbb + - ccccccccccccccc; **AlignTrailingComments** (``bool``) If ``true``, aligns trailing comments. diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 2b2edc4adc11..f5fa6b44a127 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -153,16 +153,43 @@ struct FormatStyle { /// Options for aligning backslashes in escaped newlines. EscapedNewlineAlignmentStyle AlignEscapedNewlines; + /// Different styles for aligning operands. + enum OperandAlignmentStyle { + /// Do not align operands of binary and ternary expressions. + /// The wrapped lines are indented ``ContinuationIndentWidth`` spaces from + /// the start of the line. + OAS_DontAlign, + /// Horizontally align operands of binary and ternary expressions. + /// + /// Specifically, this aligns operands of a single expression that needs + /// to be split over multiple lines, e.g.: + /// \code + /// int aaa = bbbbbbbbbbbbbbb + + /// ccccccccccccccc; + /// \endcode + /// + /// When ``BreakBeforeBinaryOperators`` is set, the wrapped operator is + /// aligned with the operand on the first line. + /// \code + /// int aaa = bbbbbbbbbbbbbbb + /// + ccccccccccccccc; + /// \endcode + OAS_Align, + /// Horizontally align operands of binary and ternary expressions. + /// + /// This is similar to ``AO_Align``, except when + /// ``BreakBeforeBinaryOperators`` is set, the operator is un-indented so + /// that the wrapped operand is aligned with the operand on the first line. + /// \code + /// int aaa = bbbbbbbbbbbbbbb + /// + ccccccccccccccc; + /// \endcode + OAS_AlignAfterOperator, + }; + /// If ``true``, horizontally align operands of binary and ternary /// expressions. - /// - /// Specifically, this aligns operands of a single expression that needs to be - /// split over multiple lines, e.g.: - /// \code - /// int aaa = bbbbbbbbbbbbbbb + - /// ccccccccccccccc; - /// \endcode - bool AlignOperands; + OperandAlignmentStyle AlignOperands; /// If ``true``, aligns trailing comments. /// \code diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index 8f1089dc81cb..dcecb30c22c7 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -693,7 +693,9 @@ void ContinuationIndenter::addTokenOnCurrentLine(LineState &State, bool DryRun, // does not help. bool HasTwoOperands = P->OperatorIndex == 0 && !P->NextOperator && !P->is(TT_ConditionalExpr); - if ((!BreakBeforeOperator && !(HasTwoOperands && Style.AlignOperands)) || + if ((!BreakBeforeOperator && + !(HasTwoOperands && + Style.AlignOperands != FormatStyle::OAS_DontAlign)) || (!State.Stack.back().LastOperatorWrapped && BreakBeforeOperator)) State.Stack.back().NoLineBreakInOperand = true; } @@ -1039,6 +1041,8 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) { // * not remove the 'lead' ContinuationIndentWidth // * always un-indent by the operator when BreakBeforeTernaryOperators=true unsigned Indent = State.Stack.back().Indent - Style.ContinuationIndentWidth; + if (Style.BreakBeforeTernaryOperators && State.Stack.back().UnindentOperator) + Indent -= 2; return Indent; } return State.Stack.back().QuestionColumn; @@ -1118,6 +1122,13 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) { return ContinuationIndent; if (Current.is(TT_ProtoExtensionLSquare)) return State.Stack.back().Indent; + if (Current.isBinaryOperator() && State.Stack.back().UnindentOperator) + return State.Stack.back().Indent - Current.Tok.getLength() - + Current.SpacesRequiredBefore; + if (Current.isOneOf(tok::comment, TT_BlockComment, TT_LineComment) && + NextNonComment->isBinaryOperator() && State.Stack.back().UnindentOperator) + return State.Stack.back().Indent - NextNonComment->Tok.getLength() - + NextNonComment->SpacesRequiredBefore; if (State.Stack.back().Indent == State.FirstIndent && PreviousNonComment && !PreviousNonComment->isOneOf(tok::r_brace, TT_CtorInitializerComma)) // Ensure that we fall back to the continuation indent width instead of @@ -1297,7 +1308,7 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, (Previous && (Previous->opensScope() || Previous->isOneOf(tok::semi, tok::kw_return) || (Previous->getPrecedence() == prec::Assignment && - Style.AlignOperands) || + Style.AlignOperands != FormatStyle::OAS_DontAlign) || Previous->is(TT_ObjCMethodExpr))); for (SmallVectorImpl::const_reverse_iterator I = Current.FakeLParens.rbegin(), @@ -1309,6 +1320,7 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, NewParenState.LastOperatorWrapped = true; NewParenState.IsChainedConditional = false; NewParenState.IsWrappedConditional = false; + NewParenState.UnindentOperator = false; NewParenState.NoLineBreak = NewParenState.NoLineBreak || State.Stack.back().NoLineBreakInOperand; @@ -1320,14 +1332,26 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, // a builder type call after 'return' or, if the alignment after opening // brackets is disabled. if (!Current.isTrailingComment() && - (Style.AlignOperands || *I < prec::Assignment) && + (Style.AlignOperands != FormatStyle::OAS_DontAlign || + *I < prec::Assignment) && (!Previous || Previous->isNot(tok::kw_return) || (Style.Language != FormatStyle::LK_Java && *I > 0)) && (Style.AlignAfterOpenBracket != FormatStyle::BAS_DontAlign || - *I != prec::Comma || Current.NestingLevel == 0)) + *I != prec::Comma || Current.NestingLevel == 0)) { NewParenState.Indent = std::max(std::max(State.Column, NewParenState.Indent), State.Stack.back().LastSpace); + } + + // If BreakBeforeBinaryOperators is set, un-indent a bit to account for + // the operator and keep the operands aligned + if (Style.AlignOperands == FormatStyle::OAS_AlignAfterOperator && Previous && + (Previous->getPrecedence() == prec::Assignment || + Previous->is(tok::kw_return) || + (*I == prec::Conditional && Previous->is(tok::question) && + Previous->is(TT_ConditionalExpr))) && + !Newline) + NewParenState.UnindentOperator = true; // Do not indent relative to the fake parentheses inserted for "." or "->". // This is a special case to make the following to statements consistent: @@ -1350,6 +1374,7 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, Previous->is(TT_ConditionalExpr) && I == Current.FakeLParens.rbegin() && !State.Stack.back().IsWrappedConditional) { NewParenState.IsChainedConditional = true; + NewParenState.UnindentOperator = State.Stack.back().UnindentOperator; } else if (*I == prec::Conditional || (!SkipFirstExtraIndent && *I > prec::Assignment && !Current.isTrailingComment())) { diff --git a/clang/lib/Format/ContinuationIndenter.h b/clang/lib/Format/ContinuationIndenter.h index 67de57601f8f..5caa1b5bad0e 100644 --- a/clang/lib/Format/ContinuationIndenter.h +++ b/clang/lib/Format/ContinuationIndenter.h @@ -210,7 +210,7 @@ struct ParenState { ObjCSelectorNameFound(false), HasMultipleNestedBlocks(false), NestedBlockInlined(false), IsInsideObjCArrayLiteral(false), IsCSharpGenericTypeConstraint(false), IsChainedConditional(false), - IsWrappedConditional(false) {} + IsWrappedConditional(false), UnindentOperator(false) {} /// \brief The token opening this parenthesis level, or nullptr if this level /// is opened by fake parenthesis. @@ -344,6 +344,10 @@ struct ParenState { /// question mark) bool IsWrappedConditional : 1; + /// \brief Indicates the indent should be reduced by the length of the + /// operator. + bool UnindentOperator : 1; + bool operator<(const ParenState &Other) const { if (Indent != Other.Indent) return Indent < Other.Indent; @@ -389,6 +393,8 @@ struct ParenState { return IsChainedConditional; if (IsWrappedConditional != Other.IsWrappedConditional) return IsWrappedConditional; + if (UnindentOperator != Other.UnindentOperator) + return UnindentOperator; return false; } }; diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index eead2b4a520a..c8fcb5b81cfe 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -308,6 +308,18 @@ struct ScalarEnumerationTraits { } }; +template <> struct ScalarEnumerationTraits { + static void enumeration(IO &IO, FormatStyle::OperandAlignmentStyle &Value) { + IO.enumCase(Value, "DontAlign", FormatStyle::OAS_DontAlign); + IO.enumCase(Value, "Align", FormatStyle::OAS_Align); + IO.enumCase(Value, "AlignAfterOperator", FormatStyle::OAS_AlignAfterOperator); + + // For backward compatibility. + IO.enumCase(Value, "true", FormatStyle::OAS_Align); + IO.enumCase(Value, "false", FormatStyle::OAS_DontAlign); + } +}; + template <> struct ScalarEnumerationTraits { static void enumeration(IO &IO, FormatStyle::PointerAlignmentStyle &Value) { IO.enumCase(Value, "Middle", FormatStyle::PAS_Middle); @@ -744,7 +756,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { LLVMStyle.AccessModifierOffset = -2; LLVMStyle.AlignEscapedNewlines = FormatStyle::ENAS_Right; LLVMStyle.AlignAfterOpenBracket = FormatStyle::BAS_Align; - LLVMStyle.AlignOperands = true; + LLVMStyle.AlignOperands = FormatStyle::OAS_Align; LLVMStyle.AlignTrailingComments = true; LLVMStyle.AlignConsecutiveAssignments = false; LLVMStyle.AlignConsecutiveDeclarations = false; @@ -943,7 +955,7 @@ FormatStyle getGoogleStyle(FormatStyle::LanguageKind Language) { if (Language == FormatStyle::LK_Java) { GoogleStyle.AlignAfterOpenBracket = FormatStyle::BAS_DontAlign; - GoogleStyle.AlignOperands = false; + GoogleStyle.AlignOperands = FormatStyle::OAS_DontAlign; GoogleStyle.AlignTrailingComments = false; GoogleStyle.AllowShortFunctionsOnASingleLine = FormatStyle::SFS_Empty; GoogleStyle.AllowShortIfStatementsOnASingleLine = FormatStyle::SIS_Never; @@ -954,7 +966,7 @@ FormatStyle getGoogleStyle(FormatStyle::LanguageKind Language) { GoogleStyle.SpacesBeforeTrailingComments = 1; } else if (Language == FormatStyle::LK_JavaScript) { GoogleStyle.AlignAfterOpenBracket = FormatStyle::BAS_AlwaysBreak; - GoogleStyle.AlignOperands = false; + GoogleStyle.AlignOperands = FormatStyle::OAS_DontAlign; GoogleStyle.AllowShortFunctionsOnASingleLine = FormatStyle::SFS_Empty; // TODO: still under discussion whether to switch to SLS_All. GoogleStyle.AllowShortLambdasOnASingleLine = FormatStyle::SLS_Empty; @@ -1085,7 +1097,7 @@ FormatStyle getWebKitStyle() { FormatStyle Style = getLLVMStyle(); Style.AccessModifierOffset = -4; Style.AlignAfterOpenBracket = FormatStyle::BAS_DontAlign; - Style.AlignOperands = false; + Style.AlignOperands = FormatStyle::OAS_DontAlign; Style.AlignTrailingComments = false; Style.AllowShortBlocksOnASingleLine = FormatStyle::SBS_Empty; Style.BreakBeforeBinaryOperators = FormatStyle::BOS_All; diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 1206cedf70f1..25555802a568 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -4240,6 +4240,9 @@ TEST_F(FormatTest, ExpressionIndentationBreakingBeforeOperators) { " > ccccc) {\n" "}", Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " && bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb;", + Style); verifyFormat("return (a)\n" " // comment\n" " + b;", @@ -4268,7 +4271,7 @@ TEST_F(FormatTest, ExpressionIndentationBreakingBeforeOperators) { Style.ColumnLimit = 60; verifyFormat("zzzzzzzzzz\n" - " = bbbbbbbbbbbbbbbbb\n" + " = bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n" " >> aaaaaaaaaaaaaaaa(aaaaaaaaaaaaaaaaaaaaaaaaaa);", Style); @@ -4277,7 +4280,7 @@ TEST_F(FormatTest, ExpressionIndentationBreakingBeforeOperators) { Style.TabWidth = 4; Style.UseTab = FormatStyle::UT_Always; Style.AlignAfterOpenBracket = FormatStyle::BAS_DontAlign; - Style.AlignOperands = false; + Style.AlignOperands = FormatStyle::OAS_DontAlign; EXPECT_EQ("return someVeryVeryLongConditionThatBarelyFitsOnALine\n" "\t&& (someOtherLongishConditionPart1\n" "\t\t|| someOtherEvenLongerNestedConditionPart2);", @@ -4287,6 +4290,107 @@ TEST_F(FormatTest, ExpressionIndentationBreakingBeforeOperators) { Style)); } +TEST_F(FormatTest, ExpressionIndentationStrictAlign) { + FormatStyle Style = getLLVMStyle(); + Style.BreakBeforeBinaryOperators = FormatStyle::BOS_All; + Style.AlignOperands = FormatStyle::OAS_AlignAfterOperator; + + verifyFormat("bool value = aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " + aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " + aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " == aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n" + " + bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n" + " && aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " > ccccccccccccccccccccccccccccccccccccccccc;", + Style); + verifyFormat("if (aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " + aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " == bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb) {\n}", + Style); + verifyFormat("if (aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " + aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " == bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb) {\n}", + Style); + verifyFormat("if (aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " == aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " + bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb) {\n}", + Style); + verifyFormat("if () {\n" + "} else if (aaaaa\n" + " && bbbbb // break\n" + " > ccccc) {\n" + "}", + Style); + verifyFormat("return aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " && bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb;", + Style); + verifyFormat("return (a)\n" + " // comment\n" + " + b;", + Style); + verifyFormat( + "int aaaaaa = aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " * bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n" + " + cc;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" + " : bbbbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("return aaaaaaaaaaaaaaaa ? (aaaaaaaaaaaaaa ? bbbbbbbbbbbbbbbbbb\n" + " : ccccccccccccccc ? dddddddddddddddddd\n" + " : eeeeeeeeeeeeeeeeee)\n" + " : bbbbbbbbbbbbbbbb ? 2222222222222222\n" + " : 3333333333333333;", + Style); + verifyFormat("aaaaaaaaaaaaaaaaaaaaaaaaaaaaa\n" + " = aaaaaaaaaaaaaaaaaaaa + aaaaaaaaaaaaaaaaaaaaaaaaaaaa;", + Style); + + verifyFormat("return boost::fusion::at_c<0>(iiii).second\n" + " == boost::fusion::at_c<1>(iiii).second;", + Style); + + Style.ColumnLimit = 60; + verifyFormat("zzzzzzzzzzzzz\n" + " = bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb\n" + " >> aaaaaaaaaaaaaaaa(aaaaaaaaaaaaaaaaaaaaaaaaaa);", + Style); + + // Forced by comments. + Style.ColumnLimit = 80; + verifyFormat( + "unsigned ContentSize\n" + " = sizeof(int16_t) // DWARF ARange version number\n" + " + sizeof(int32_t) // Offset of CU in the .debug_info section\n" + " + sizeof(int8_t) // Pointer Size (in bytes)\n" + " + sizeof(int8_t); // Segment Size (in bytes)", + Style); + + Style.BreakBeforeBinaryOperators = FormatStyle::BOS_NonAssignment; + verifyFormat( + "unsigned ContentSize =\n" + " sizeof(int16_t) // DWARF ARange version number\n" + " + sizeof(int32_t) // Offset of CU in the .debug_info section\n" + " + sizeof(int8_t) // Pointer Size (in bytes)\n" + " + sizeof(int8_t); // Segment Size (in bytes)", + Style); + + Style.BreakBeforeBinaryOperators = FormatStyle::BOS_None; + verifyFormat( + "unsigned ContentSize =\n" + " sizeof(int16_t) // DWARF ARange version number\n" + " + sizeof(int32_t) // Offset of CU in the .debug_info section\n" + " + sizeof(int8_t) // Pointer Size (in bytes)\n" + " + sizeof(int8_t); // Segment Size (in bytes)", + Style); +} + TEST_F(FormatTest, EnforcedOperatorWraps) { // Here we'd like to wrap after the || operators, but a comment is forcing an // earlier wrap. @@ -4298,7 +4402,7 @@ TEST_F(FormatTest, EnforcedOperatorWraps) { TEST_F(FormatTest, NoOperandAlignment) { FormatStyle Style = getLLVMStyle(); - Style.AlignOperands = false; + Style.AlignOperands = FormatStyle::OAS_DontAlign; verifyFormat("aaaaaaaaaaaaaa(aaaaaaaaaaaa,\n" " aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa +\n" " aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa);", @@ -5798,17 +5902,17 @@ TEST_F(FormatTest, ParenthesesAndOperandAlignment) { " bbbbbbbbbbbbbbbbbbbbbb);", Style); Style.AlignAfterOpenBracket = FormatStyle::BAS_Align; - Style.AlignOperands = false; + Style.AlignOperands = FormatStyle::OAS_DontAlign; verifyFormat("int a = f(aaaaaaaaaaaaaaaaaaaaaa &&\n" " bbbbbbbbbbbbbbbbbbbbbb);", Style); Style.AlignAfterOpenBracket = FormatStyle::BAS_DontAlign; - Style.AlignOperands = true; + Style.AlignOperands = FormatStyle::OAS_Align; verifyFormat("int a = f(aaaaaaaaaaaaaaaaaaaaaa &&\n" " bbbbbbbbbbbbbbbbbbbbbb);", Style); Style.AlignAfterOpenBracket = FormatStyle::BAS_DontAlign; - Style.AlignOperands = false; + Style.AlignOperands = FormatStyle::OAS_DontAlign; verifyFormat("int a = f(aaaaaaaaaaaaaaaaaaaaaa &&\n" " bbbbbbbbbbbbbbbbbbbbbb);", Style); @@ -5954,7 +6058,7 @@ TEST_F(FormatTest, BreaksConditionalExpressions) { // Chained conditionals FormatStyle Style = getLLVMStyle(); Style.ColumnLimit = 70; - Style.AlignOperands = true; + Style.AlignOperands = FormatStyle::OAS_Align; verifyFormat("return aaaaaaaaaaaaaaaa ? 1111111111111111\n" " : bbbbbbbbbbbbbb ? 2222222222222222\n" " : 3333333333333333;", @@ -13136,7 +13240,6 @@ TEST_F(FormatTest, GetsCorrectBasedOnStyle) { TEST_F(FormatTest, ParsesConfigurationBools) { FormatStyle Style = {}; Style.Language = FormatStyle::LK_Cpp; - CHECK_PARSE_BOOL(AlignOperands); CHECK_PARSE_BOOL(AlignTrailingComments); CHECK_PARSE_BOOL(AlignConsecutiveAssignments); CHECK_PARSE_BOOL(AlignConsecutiveDeclarations); @@ -13320,6 +13423,17 @@ TEST_F(FormatTest, ParsesConfiguration) { CHECK_PARSE("AlignEscapedNewlinesLeft: false", AlignEscapedNewlines, FormatStyle::ENAS_Right); + Style.AlignOperands = FormatStyle::OAS_Align; + CHECK_PARSE("AlignOperands: DontAlign", AlignOperands, + FormatStyle::OAS_DontAlign); + CHECK_PARSE("AlignOperands: Align", AlignOperands, FormatStyle::OAS_Align); + CHECK_PARSE("AlignOperands: AlignAfterOperator", AlignOperands, + FormatStyle::OAS_AlignAfterOperator); + // For backward compatibility: + CHECK_PARSE("AlignOperands: false", AlignOperands, + FormatStyle::OAS_DontAlign); + CHECK_PARSE("AlignOperands: true", AlignOperands, FormatStyle::OAS_Align); + Style.UseTab = FormatStyle::UT_ForIndentation; CHECK_PARSE("UseTab: Never", UseTab, FormatStyle::UT_Never); CHECK_PARSE("UseTab: ForIndentation", UseTab, FormatStyle::UT_ForIndentation); diff --git a/clang/unittests/Format/FormatTestJS.cpp b/clang/unittests/Format/FormatTestJS.cpp index eadea35f051a..c1c47065c185 100644 --- a/clang/unittests/Format/FormatTestJS.cpp +++ b/clang/unittests/Format/FormatTestJS.cpp @@ -277,7 +277,7 @@ TEST_F(FormatTestJS, UnderstandsJavaScriptOperators) { verifyFormat("var x = aaaaaaaaaaaaaaaaaaaaaaaaa() in\n" " aaaa.aaaaaa.aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;"); FormatStyle Style = getGoogleJSStyleWithColumns(80); - Style.AlignOperands = true; + Style.AlignOperands = FormatStyle::OAS_Align; verifyFormat("var x = aaaaaaaaaaaaaaaaaaaaaaaaa() in\n" " aaaa.aaaaaa.aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;", Style); -- GitLab From 188f5cde9635a29a3f20ee2a73abd02890a752c7 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Wed, 22 Apr 2020 10:36:23 -0500 Subject: [PATCH 101/910] Revert "[OpenMP][FIX] Do not use InaccessibleMemOrArgMemOnly for barrier and flush" Forgot to include test changes :( This reverts commit 72a9e7c926f4e32f209e528ec407fe526da5587e. --- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 7599a7c98175..1a82d772d26a 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -389,16 +389,24 @@ __OMP_ATTRS_SET(SetterAttrs, #define __OMP_RTL_ATTRS(Name, FnAttrSet, RetAttrSet, ArgAttrSets) \ OMP_RTL_ATTRS(OMPRTL_##Name, FnAttrSet, RetAttrSet, ArgAttrSets) -__OMP_RTL_ATTRS(__kmpc_barrier, AttributeSet(), AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_barrier, + AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), + AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_cancel, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_cancel_barrier, AttributeSet(), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_flush, AttributeSet(), AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_cancel_barrier, + AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), + AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_flush, + AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), + AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_global_thread_num, GetterAttrs, AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_fork_call, AttributeSet(EnumAttr(NoUnwind)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_omp_taskwait, AttributeSet(), AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_omp_taskwait, + AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), + AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_omp_taskyield, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) -- GitLab From 1b6b05a2501a8ad2cd35d275c03edb63dffb5cb7 Mon Sep 17 00:00:00 2001 From: Mircea Trofin Date: Tue, 21 Apr 2020 21:56:04 -0700 Subject: [PATCH 102/910] [llvm][NFC][CallSite] Remove CallSite from a few trivial locations Summary: Implementation details and internal (to module) APIs. Reviewers: craig.topper, dblaikie Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78610 --- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 16 +++++------ .../Transforms/IPO/IPConstantPropagation.cpp | 16 +++++------ llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 4 +-- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 7 ++--- .../IPO/SyntheticCountsPropagation.cpp | 7 ++--- .../Transforms/Instrumentation/CGProfile.cpp | 14 ++++------ .../Instrumentation/SanitizerCoverage.cpp | 9 +++--- .../Instrumentation/ValueProfilePlugins.inc | 2 +- llvm/lib/Transforms/Scalar/LoopUnswitch.cpp | 8 +++--- .../Scalar/LowerMatrixIntrinsics.cpp | 3 +- .../lib/Transforms/Scalar/MemCpyOptimizer.cpp | 28 ++++++++----------- 11 files changed, 50 insertions(+), 64 deletions(-) diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp index 360794e9dc8b..94c872a34125 100644 --- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp +++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp @@ -28,7 +28,6 @@ #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/CallingConv.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" @@ -2188,12 +2187,12 @@ static bool hasChangeableCC(Function *F) { /// Return true if the block containing the call site has a BlockFrequency of /// less than ColdCCRelFreq% of the entry block. -static bool isColdCallSite(CallSite CS, BlockFrequencyInfo &CallerBFI) { +static bool isColdCallSite(CallBase &CB, BlockFrequencyInfo &CallerBFI) { const BranchProbability ColdProb(ColdCCRelFreq, 100); - auto CallSiteBB = CS.getInstruction()->getParent(); + auto *CallSiteBB = CB.getParent(); auto CallSiteFreq = CallerBFI.getBlockFreq(CallSiteBB); auto CallerEntryFreq = - CallerBFI.getBlockFreq(&(CS.getCaller()->getEntryBlock())); + CallerBFI.getBlockFreq(&(CB.getCaller()->getEntryBlock())); return CallSiteFreq < CallerEntryFreq * ColdProb; } @@ -2213,10 +2212,10 @@ isValidCandidateForColdCC(Function &F, if (isa(U)) continue; - CallSite CS(cast(U)); - Function *CallerFunc = CS.getInstruction()->getParent()->getParent(); + CallBase &CB = cast(*U); + Function *CallerFunc = CB.getParent()->getParent(); BlockFrequencyInfo &CallerBFI = GetBFI(*CallerFunc); - if (!isColdCallSite(CS, CallerBFI)) + if (!isColdCallSite(CB, CallerBFI)) return false; auto It = std::find(AllCallsCold.begin(), AllCallsCold.end(), CallerFunc); if (It == AllCallsCold.end()) @@ -2242,7 +2241,6 @@ hasOnlyColdCalls(Function &F, for (BasicBlock &BB : F) { for (Instruction &I : BB) { if (CallInst *CI = dyn_cast(&I)) { - CallSite CS(cast(CI)); // Skip over isline asm instructions since they aren't function calls. if (CI->isInlineAsm()) continue; @@ -2259,7 +2257,7 @@ hasOnlyColdCalls(Function &F, CalledFn->hasAddressTaken()) return false; BlockFrequencyInfo &CallerBFI = GetBFI(F); - if (!isColdCallSite(CS, CallerBFI)) + if (!isColdCallSite(*CI, CallerBFI)) return false; } } diff --git a/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp b/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp index 87ebdb4482bc..fc62ec4f9565 100644 --- a/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp +++ b/llvm/lib/Transforms/IPO/IPConstantPropagation.cpp @@ -17,7 +17,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/ValueTracking.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Module.h" @@ -222,16 +221,15 @@ static bool PropagateConstantReturn(Function &F) { // constant. bool MadeChange = false; for (Use &U : F.uses()) { - CallSite CS(U.getUser()); - Instruction* Call = CS.getInstruction(); + CallBase *CB = dyn_cast(U.getUser()); // Not a call instruction or a call instruction that's not calling F // directly? - if (!Call || !CS.isCallee(&U)) + if (!CB || !CB->isCallee(&U)) continue; // Call result not used? - if (Call->use_empty()) + if (CB->use_empty()) continue; MadeChange = true; @@ -241,12 +239,12 @@ static bool PropagateConstantReturn(Function &F) { if (Argument *A = dyn_cast(New)) // Was an argument returned? Then find the corresponding argument in // the call instruction and use that. - New = CS.getArgument(A->getArgNo()); - Call->replaceAllUsesWith(New); + New = CB->getArgOperand(A->getArgNo()); + CB->replaceAllUsesWith(New); continue; } - for (auto I = Call->user_begin(), E = Call->user_end(); I != E;) { + for (auto I = CB->user_begin(), E = CB->user_end(); I != E;) { Instruction *Ins = cast(*I); // Increment now, so we can remove the use @@ -266,7 +264,7 @@ static bool PropagateConstantReturn(Function &F) { if (Argument *A = dyn_cast(New)) // Was an argument returned? Then find the corresponding argument in // the call instruction and use that. - New = CS.getArgument(A->getArgNo()); + New = CB->getArgOperand(A->getArgNo()); Ins->replaceAllUsesWith(New); Ins->eraseFromParent(); } diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index 6f38a3123932..8b108f1bf50c 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -1712,8 +1712,8 @@ bool LowerTypeTestsModule::runForTesting(Module &M) { static bool isDirectCall(Use& U) { auto *Usr = dyn_cast(U.getUser()); if (Usr) { - CallSite CS(Usr); - if (CS.isCallee(&U)) + auto *CB = dyn_cast(Usr); + if (CB && CB->isCallee(&U)) return true; } return false; diff --git a/llvm/lib/Transforms/IPO/MergeFunctions.cpp b/llvm/lib/Transforms/IPO/MergeFunctions.cpp index 06d2a2f31941..8cc19515f3db 100644 --- a/llvm/lib/Transforms/IPO/MergeFunctions.cpp +++ b/llvm/lib/Transforms/IPO/MergeFunctions.cpp @@ -95,7 +95,6 @@ #include "llvm/IR/Argument.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -467,13 +466,13 @@ void MergeFunctions::replaceDirectCallers(Function *Old, Function *New) { for (auto UI = Old->use_begin(), UE = Old->use_end(); UI != UE;) { Use *U = &*UI; ++UI; - CallSite CS(U->getUser()); - if (CS && CS.isCallee(U)) { + CallBase *CB = dyn_cast(U->getUser()); + if (CB && CB->isCallee(U)) { // Do not copy attributes from the called function to the call-site. // Function comparison ensures that the attributes are the same up to // type congruences in byval(), in which case we need to keep the byval // type of the call-site, not the callee function. - remove(CS.getInstruction()->getFunction()); + remove(CB->getFunction()); U->set(BitcastNew); } } diff --git a/llvm/lib/Transforms/IPO/SyntheticCountsPropagation.cpp b/llvm/lib/Transforms/IPO/SyntheticCountsPropagation.cpp index 45fd432fd721..5a5e94ae1fb5 100644 --- a/llvm/lib/Transforms/IPO/SyntheticCountsPropagation.cpp +++ b/llvm/lib/Transforms/IPO/SyntheticCountsPropagation.cpp @@ -31,7 +31,6 @@ #include "llvm/Analysis/CallGraph.h" #include "llvm/Analysis/ProfileSummaryInfo.h" #include "llvm/Analysis/SyntheticCountsUtils.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/Module.h" @@ -111,13 +110,13 @@ PreservedAnalyses SyntheticCountsPropagation::run(Module &M, if (!Edge.first) return Res; assert(isa(Edge.first)); - CallSite CS(cast(Edge.first)); - Function *Caller = CS.getCaller(); + CallBase &CB = cast(*Edge.first); + Function *Caller = CB.getCaller(); auto &BFI = FAM.getResult(*Caller); // Now compute the callsite count from relative frequency and // entry count: - BasicBlock *CSBB = CS.getInstruction()->getParent(); + BasicBlock *CSBB = CB.getParent(); Scaled64 EntryFreq(BFI.getEntryFreq(), 0); Scaled64 BBCount(BFI.getBlockFreq(CSBB).getFrequency(), 0); BBCount /= EntryFreq; diff --git a/llvm/lib/Transforms/Instrumentation/CGProfile.cpp b/llvm/lib/Transforms/Instrumentation/CGProfile.cpp index 358abab3cceb..2d5bd9570940 100644 --- a/llvm/lib/Transforms/Instrumentation/CGProfile.cpp +++ b/llvm/lib/Transforms/Instrumentation/CGProfile.cpp @@ -11,7 +11,6 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Analysis/BlockFrequencyInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/MDBuilder.h" @@ -49,16 +48,15 @@ PreservedAnalyses CGProfilePass::run(Module &M, ModuleAnalysisManager &MAM) { if (!BBCount) continue; for (auto &I : BB) { - CallSite CS(&I); - if (!CS) + CallBase *CB = dyn_cast(&I); + if (!CB) continue; - if (CS.isIndirectCall()) { + if (CB->isIndirectCall()) { InstrProfValueData ValueData[8]; uint32_t ActualNumValueData; uint64_t TotalC; - if (!getValueProfDataFromInst(*CS.getInstruction(), - IPVK_IndirectCallTarget, 8, ValueData, - ActualNumValueData, TotalC)) + if (!getValueProfDataFromInst(*CB, IPVK_IndirectCallTarget, 8, + ValueData, ActualNumValueData, TotalC)) continue; for (const auto &VD : ArrayRef(ValueData, ActualNumValueData)) { @@ -66,7 +64,7 @@ PreservedAnalyses CGProfilePass::run(Module &M, ModuleAnalysisManager &MAM) { } continue; } - UpdateCounts(TTI, &F, CS.getCalledFunction(), *BBCount); + UpdateCounts(TTI, &F, CB->getCalledFunction(), *BBCount); } } } diff --git a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp index 81e1eba739fa..d3eeb0252352 100644 --- a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp +++ b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp @@ -16,7 +16,6 @@ #include "llvm/Analysis/EHPersonalities.h" #include "llvm/Analysis/PostDominators.h" #include "llvm/IR/CFG.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DebugInfo.h" @@ -661,8 +660,8 @@ void ModuleSanitizerCoverage::instrumentFunction( BlocksToInstrument.push_back(&BB); for (auto &Inst : BB) { if (Options.IndirectCalls) { - CallSite CS(&Inst); - if (CS && !CS.getCalledFunction()) + CallBase *CB = dyn_cast(&Inst); + if (CB && !CB->getCalledFunction()) IndirCalls.push_back(&Inst); } if (Options.TraceCmp) { @@ -786,8 +785,8 @@ void ModuleSanitizerCoverage::InjectCoverageForIndirectCalls( Options.Inline8bitCounters || Options.InlineBoolFlag); for (auto I : IndirCalls) { IRBuilder<> IRB(I); - CallSite CS(I); - Value *Callee = CS.getCalledValue(); + CallBase &CB = cast(*I); + Value *Callee = CB.getCalledValue(); if (isa(Callee)) continue; IRB.CreateCall(SanCovTracePCIndir, IRB.CreatePointerCast(Callee, IntptrTy)); diff --git a/llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc b/llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc index 4cc4c6c848c3..08195ee54ab0 100644 --- a/llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc +++ b/llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc @@ -59,7 +59,7 @@ public: void run(std::vector &Candidates) { std::vector Result = findIndirectCalls(F); for (Instruction *I : Result) { - Value *Callee = CallSite(I).getCalledValue(); + Value *Callee = cast(I)->getCalledValue(); Instruction *InsertPt = I; Instruction *AnnotatedInst = I; Candidates.emplace_back(CandidateInfo{Callee, InsertPt, AnnotatedInst}); diff --git a/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp index 9b38106bb731..645a89bbd0ff 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp @@ -43,7 +43,6 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" @@ -682,9 +681,10 @@ bool LoopUnswitch::processCurrentLoop() { for (const auto BB : CurrentLoop->blocks()) { for (auto &I : *BB) { - auto CS = CallSite(&I); - if (!CS) continue; - if (CS.isConvergent()) + auto *CB = dyn_cast(&I); + if (!CB) + continue; + if (CB->isConvergent()) return false; if (auto *II = dyn_cast(&I)) if (!II->getUnwindDest()->canSplitPredecessors()) diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp index 86c560022deb..45709cb65503 100644 --- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp +++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp @@ -1612,8 +1612,7 @@ public: if (auto *CI = dyn_cast(I)) { writeFnName(CI); - Ops.append(CallSite(CI).arg_begin(), - CallSite(CI).arg_end() - getNumShapeArgs(CI)); + Ops.append(CI->arg_begin(), CI->arg_end() - getNumShapeArgs(CI)); } else if (isa(Expr)) { // Special case bitcasts, which are used to materialize matrixes from // non-matrix ops. diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp index 4168f2f20bf5..a2e13a959ddf 100644 --- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp +++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp @@ -27,7 +27,6 @@ #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Argument.h" #include "llvm/IR/BasicBlock.h" -#include "llvm/IR/CallSite.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" @@ -728,10 +727,6 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpy, Value *cpyDest, if (F->isIntrinsic() && F->getIntrinsicID() == Intrinsic::lifetime_start) return false; - // Deliberately get the source and destination with bitcasts stripped away, - // because we'll need to do type comparisons based on the underlying type. - CallSite CS(C); - // Require that src be an alloca. This simplifies the reasoning considerably. AllocaInst *srcAlloca = dyn_cast(cpySrc); if (!srcAlloca) @@ -831,8 +826,8 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpy, Value *cpyDest, // Check that src isn't captured by the called function since the // transformation can cause aliasing issues in that case. - for (unsigned i = 0, e = CS.arg_size(); i != e; ++i) - if (CS.getArgument(i) == cpySrc && !CS.doesNotCapture(i)) + for (unsigned ArgI = 0, E = C->arg_size(); ArgI != E; ++ArgI) + if (C->getArgOperand(ArgI) == cpySrc && !C->doesNotCapture(ArgI)) return false; // Since we're changing the parameter to the callsite, we need to make sure @@ -859,25 +854,26 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpy, Value *cpyDest, if (cpySrc->getType()->getPointerAddressSpace() != cpyDest->getType()->getPointerAddressSpace()) return false; - for (unsigned i = 0; i < CS.arg_size(); ++i) - if (CS.getArgument(i)->stripPointerCasts() == cpySrc && + for (unsigned ArgI = 0; ArgI < C->arg_size(); ++ArgI) + if (C->getArgOperand(ArgI)->stripPointerCasts() == cpySrc && cpySrc->getType()->getPointerAddressSpace() != - CS.getArgument(i)->getType()->getPointerAddressSpace()) + C->getArgOperand(ArgI)->getType()->getPointerAddressSpace()) return false; // All the checks have passed, so do the transformation. bool changedArgument = false; - for (unsigned i = 0; i < CS.arg_size(); ++i) - if (CS.getArgument(i)->stripPointerCasts() == cpySrc) { + for (unsigned ArgI = 0; ArgI < C->arg_size(); ++ArgI) + if (C->getArgOperand(ArgI)->stripPointerCasts() == cpySrc) { Value *Dest = cpySrc->getType() == cpyDest->getType() ? cpyDest : CastInst::CreatePointerCast(cpyDest, cpySrc->getType(), cpyDest->getName(), C); changedArgument = true; - if (CS.getArgument(i)->getType() == Dest->getType()) - CS.setArgument(i, Dest); + if (C->getArgOperand(ArgI)->getType() == Dest->getType()) + C->setArgOperand(ArgI, Dest); else - CS.setArgument(i, CastInst::CreatePointerCast(Dest, - CS.getArgument(i)->getType(), Dest->getName(), C)); + C->setArgOperand(ArgI, CastInst::CreatePointerCast( + Dest, C->getArgOperand(ArgI)->getType(), + Dest->getName(), C)); } if (!changedArgument) -- GitLab From 662cbaf6476b7cc58d0d71ff98d95d00ce5b420e Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Wed, 22 Apr 2020 15:00:01 +0100 Subject: [PATCH 103/910] [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat Add the IsOverloadNone flag to tell CGBuiltin that it does not have an overloaded type. This is used for e.g. svpfalse which does not take any arguments and always returns a svbool_t. This patch also adds builtins for svcntb_pat, svcnth_pat, svcntw_pat and svcntd_pat, as those don't require custom codegen. Reviewers: SjoerdMeijer, efriedma, rovka Reviewed By: efriedma Tags: #clang Differential Revision: https://reviews.llvm.org/D77596 --- clang/include/clang/Basic/TargetBuiltins.h | 2 + clang/include/clang/Basic/arm_sve.td | 20 +++ clang/lib/CodeGen/CGBuiltin.cpp | 41 ++++-- clang/lib/CodeGen/CodeGenFunction.h | 2 + .../aarch64-sve-intrinsics/acle_sve_cntb.c | 139 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_cntd.c | 139 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_cnth.c | 139 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_cntw.c | 139 ++++++++++++++++++ .../aarch64-sve-intrinsics/acle_sve_pfalse.c | 18 +++ clang/utils/TableGen/SveEmitter.cpp | 36 +++++ 10 files changed, 665 insertions(+), 10 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c create mode 100644 clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index d07b2d81988d..042f60739f85 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -233,6 +233,8 @@ namespace clang { bool isStructStore() const { return Flags & IsStructStore; } bool isZExtReturn() const { return Flags & IsZExtReturn; } bool isByteIndexed() const { return Flags & IsByteIndexed; } + bool isOverloadNone() const { return Flags & IsOverloadNone; } + bool isOverloadDefault() const { return !(Flags & OverloadKindMask); } uint64_t getBits() const { return Flags; } bool isFlagSet(uint64_t Flag) const { return Flags & Flag; } diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index cc579f773669..c2794356d251 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -70,6 +70,10 @@ // o: 4x width elements, 1/4 element count // // i: constant uint64_t +// k: int32_t +// l: int64_t +// m: uint32_t +// n: uint64_t // // I: Predicate Pattern (sv_pattern) @@ -163,6 +167,8 @@ def IsScatterStore : FlagType<0x00010000>; def IsStructLoad : FlagType<0x00020000>; def IsStructStore : FlagType<0x00040000>; def IsZExtReturn : FlagType<0x00080000>; // Return value is sign-extend by default +def IsOverloadNone : FlagType<0x00100000>; // Intrinsic does not take any overloaded types. +def OverloadKindMask : FlagType<0x00E00000>; // When the masked values are all '0', the default type is used as overload type. // : : // : : def IsByteIndexed : FlagType<0x02000000>; @@ -542,6 +548,20 @@ def SVCMLA_M : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeOp1, "aarch64_sve_fc def SVQDECH_S : SInst<"svqdech_pat[_{d}]", "ddIi", "s", MergeNone, "aarch64_sve_sqdech", [], [ImmCheck<2, ImmCheck1_16>]>; def SVQDECH_U : SInst<"svqdech_pat[_{d}]", "ddIi", "Us", MergeNone, "aarch64_sve_uqdech", [], [ImmCheck<2, ImmCheck1_16>]>; + +//////////////////////////////////////////////////////////////////////////////// +// Predicate creation + +def SVPFALSE : SInst<"svpfalse[_b]", "P", "", MergeNone, "", [IsOverloadNone]>; + + +//////////////////////////////////////////////////////////////////////////////// +// Counting elements + +def SVCNTB_PAT : SInst<"svcntb_pat", "nI", "", MergeNone, "aarch64_sve_cntb", [IsOverloadNone]>; +def SVCNTH_PAT : SInst<"svcnth_pat", "nI", "", MergeNone, "aarch64_sve_cnth", [IsOverloadNone]>; +def SVCNTW_PAT : SInst<"svcntw_pat", "nI", "", MergeNone, "aarch64_sve_cntw", [IsOverloadNone]>; +def SVCNTD_PAT : SInst<"svcntd_pat", "nI", "", MergeNone, "aarch64_sve_cntd", [IsOverloadNone]>; //////////////////////////////////////////////////////////////////////////////// // Integer arithmetic def SVDOT_LANE_S : SInst<"svdot_lane[_{d}]", "ddqqi", "il", MergeNone, "aarch64_sve_sdot_lane", [], [ImmCheck<3, ImmCheckLaneIndexDot, 2>]>; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 3e24f0f53ab8..fa461a5dd9bf 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -7773,6 +7773,18 @@ static void InsertExplicitUndefOperand(CGBuilderTy &Builder, llvm::Type *Ty, Ops.insert(Ops.begin(), SplatUndef); } +SmallVector +CodeGenFunction::getSVEOverloadTypes(SVETypeFlags TypeFlags, + ArrayRef Ops) { + if (TypeFlags.isOverloadNone()) + return {}; + + llvm::Type *DefaultType = getSVEType(TypeFlags); + + assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads"); + return {DefaultType}; +} + Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, const CallExpr *E) { // Find out if any arguments are required to be integer constant expressions. @@ -7814,8 +7826,6 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, else if (TypeFlags.isScatterStore()) return EmitSVEScatterStore(TypeFlags, Ops, Builtin->LLVMIntrinsic); else if (Builtin->LLVMIntrinsic != 0) { - llvm::VectorType *OverloadedTy = getSVEType(TypeFlags); - if (TypeFlags.getMergeType() == SVETypeFlags::MergeZeroExp) InsertExplicitZeroOperand(Builder, Ty, Ops); @@ -7823,13 +7833,10 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, InsertExplicitUndefOperand(Builder, Ty, Ops); // Predicates must match the main datatype. - for (unsigned i = 0, e = Ops.size(); i != e; ++i) { + for (unsigned i = 0, e = Ops.size(); i != e; ++i) if (auto PredTy = dyn_cast(Ops[i]->getType())) - if (PredTy->getScalarType()->isIntegerTy(1)) { - auto NewPredTy = cast(OverloadedTy); - Ops[i] = EmitSVEPredicateCast(Ops[i], NewPredTy); - } - } + if (PredTy->getElementType()->isIntegerTy(1)) + Ops[i] = EmitSVEPredicateCast(Ops[i], getSVEType(TypeFlags)); // Splat scalar operand to vector (intrinsics with _n infix) if (TypeFlags.hasSplatOperand()) { @@ -7845,9 +7852,23 @@ Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, Ops[1] = Builder.CreateCall(Sel, {Ops[0], Ops[1], SplatZero}); } - Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy); + Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, + getSVEOverloadTypes(TypeFlags, Ops)); Value *Call = Builder.CreateCall(F, Ops); - return Call; + + // Predicate results must be converted to svbool_t. + if (auto PredTy = dyn_cast(Call->getType())) + if (PredTy->getScalarType()->isIntegerTy(1)) + Call = EmitSVEPredicateCast(Call, cast(Ty)); + + return Call; + } + + switch (BuiltinID) { + default: + return nullptr; + case SVE::BI__builtin_sve_svpfalse_b: + return ConstantInt::getFalse(Ty); } /// Should not happen diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 6d9415d93c6f..7e2624a48259 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3908,6 +3908,8 @@ public: /// pointer operand. llvm::Type *SVEBuiltinMemEltTy(SVETypeFlags TypeFlags); + SmallVector getSVEOverloadTypes(SVETypeFlags TypeFlags, + ArrayRef Ops); llvm::Type *getEltType(SVETypeFlags TypeFlags); llvm::VectorType *getSVEType(const SVETypeFlags &TypeFlags); llvm::Value *EmitSVEDupX(llvm::Value *Scalar); diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c new file mode 100644 index 000000000000..b8ca5f475f13 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c @@ -0,0 +1,139 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s + +#include + +uint64_t test_svcntb_pat() +{ + // CHECK-LABEL: test_svcntb_pat + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 0) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_POW2); +} + +uint64_t test_svcntb_pat_1() +{ + // CHECK-LABEL: test_svcntb_pat_1 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 1) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL1); +} + +uint64_t test_svcntb_pat_2() +{ + // CHECK-LABEL: test_svcntb_pat_2 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 2) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL2); +} + +uint64_t test_svcntb_pat_3() +{ + // CHECK-LABEL: test_svcntb_pat_3 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 3) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL3); +} + +uint64_t test_svcntb_pat_4() +{ + // CHECK-LABEL: test_svcntb_pat_4 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 4) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL4); +} + +uint64_t test_svcntb_pat_5() +{ + // CHECK-LABEL: test_svcntb_pat_5 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 5) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL5); +} + +uint64_t test_svcntb_pat_6() +{ + // CHECK-LABEL: test_svcntb_pat_6 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 6) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL6); +} + +uint64_t test_svcntb_pat_7() +{ + // CHECK-LABEL: test_svcntb_pat_7 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 7) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL7); +} + +uint64_t test_svcntb_pat_8() +{ + // CHECK-LABEL: test_svcntb_pat_8 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 8) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL8); +} + +uint64_t test_svcntb_pat_9() +{ + // CHECK-LABEL: test_svcntb_pat_9 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 9) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL16); +} + +uint64_t test_svcntb_pat_10() +{ + // CHECK-LABEL: test_svcntb_pat_10 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 10) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL32); +} + +uint64_t test_svcntb_pat_11() +{ + // CHECK-LABEL: test_svcntb_pat_11 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 11) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL64); +} + +uint64_t test_svcntb_pat_12() +{ + // CHECK-LABEL: test_svcntb_pat_12 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 12) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL128); +} + +uint64_t test_svcntb_pat_13() +{ + // CHECK-LABEL: test_svcntb_pat_13 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 13) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_VL256); +} + +uint64_t test_svcntb_pat_14() +{ + // CHECK-LABEL: test_svcntb_pat_14 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 29) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_MUL4); +} + +uint64_t test_svcntb_pat_15() +{ + // CHECK-LABEL: test_svcntb_pat_15 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 30) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_MUL3); +} + +uint64_t test_svcntb_pat_16() +{ + // CHECK-LABEL: test_svcntb_pat_16 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntb(i32 31) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntb_pat(SV_ALL); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c new file mode 100644 index 000000000000..f01036703405 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c @@ -0,0 +1,139 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s + +#include + +uint64_t test_svcntd_pat() +{ + // CHECK-LABEL: test_svcntd_pat + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 0) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_POW2); +} + +uint64_t test_svcntd_pat_1() +{ + // CHECK-LABEL: test_svcntd_pat_1 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 1) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL1); +} + +uint64_t test_svcntd_pat_2() +{ + // CHECK-LABEL: test_svcntd_pat_2 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 2) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL2); +} + +uint64_t test_svcntd_pat_3() +{ + // CHECK-LABEL: test_svcntd_pat_3 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 3) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL3); +} + +uint64_t test_svcntd_pat_4() +{ + // CHECK-LABEL: test_svcntd_pat_4 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 4) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL4); +} + +uint64_t test_svcntd_pat_5() +{ + // CHECK-LABEL: test_svcntd_pat_5 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 5) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL5); +} + +uint64_t test_svcntd_pat_6() +{ + // CHECK-LABEL: test_svcntd_pat_6 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 6) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL6); +} + +uint64_t test_svcntd_pat_7() +{ + // CHECK-LABEL: test_svcntd_pat_7 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 7) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL7); +} + +uint64_t test_svcntd_pat_8() +{ + // CHECK-LABEL: test_svcntd_pat_8 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 8) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL8); +} + +uint64_t test_svcntd_pat_9() +{ + // CHECK-LABEL: test_svcntd_pat_9 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 9) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL16); +} + +uint64_t test_svcntd_pat_10() +{ + // CHECK-LABEL: test_svcntd_pat_10 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 10) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL32); +} + +uint64_t test_svcntd_pat_11() +{ + // CHECK-LABEL: test_svcntd_pat_11 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 11) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL64); +} + +uint64_t test_svcntd_pat_12() +{ + // CHECK-LABEL: test_svcntd_pat_12 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 12) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL128); +} + +uint64_t test_svcntd_pat_13() +{ + // CHECK-LABEL: test_svcntd_pat_13 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 13) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_VL256); +} + +uint64_t test_svcntd_pat_14() +{ + // CHECK-LABEL: test_svcntd_pat_14 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 29) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_MUL4); +} + +uint64_t test_svcntd_pat_15() +{ + // CHECK-LABEL: test_svcntd_pat_15 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 30) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_MUL3); +} + +uint64_t test_svcntd_pat_16() +{ + // CHECK-LABEL: test_svcntd_pat_16 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntd(i32 31) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntd_pat(SV_ALL); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c new file mode 100644 index 000000000000..652970a5f8c4 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c @@ -0,0 +1,139 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s + +#include + +uint64_t test_svcnth_pat() +{ + // CHECK-LABEL: test_svcnth_pat + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 0) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_POW2); +} + +uint64_t test_svcnth_pat_1() +{ + // CHECK-LABEL: test_svcnth_pat_1 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 1) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL1); +} + +uint64_t test_svcnth_pat_2() +{ + // CHECK-LABEL: test_svcnth_pat_2 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 2) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL2); +} + +uint64_t test_svcnth_pat_3() +{ + // CHECK-LABEL: test_svcnth_pat_3 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 3) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL3); +} + +uint64_t test_svcnth_pat_4() +{ + // CHECK-LABEL: test_svcnth_pat_4 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 4) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL4); +} + +uint64_t test_svcnth_pat_5() +{ + // CHECK-LABEL: test_svcnth_pat_5 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 5) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL5); +} + +uint64_t test_svcnth_pat_6() +{ + // CHECK-LABEL: test_svcnth_pat_6 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 6) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL6); +} + +uint64_t test_svcnth_pat_7() +{ + // CHECK-LABEL: test_svcnth_pat_7 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 7) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL7); +} + +uint64_t test_svcnth_pat_8() +{ + // CHECK-LABEL: test_svcnth_pat_8 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 8) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL8); +} + +uint64_t test_svcnth_pat_9() +{ + // CHECK-LABEL: test_svcnth_pat_9 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 9) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL16); +} + +uint64_t test_svcnth_pat_10() +{ + // CHECK-LABEL: test_svcnth_pat_10 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 10) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL32); +} + +uint64_t test_svcnth_pat_11() +{ + // CHECK-LABEL: test_svcnth_pat_11 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 11) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL64); +} + +uint64_t test_svcnth_pat_12() +{ + // CHECK-LABEL: test_svcnth_pat_12 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 12) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL128); +} + +uint64_t test_svcnth_pat_13() +{ + // CHECK-LABEL: test_svcnth_pat_13 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 13) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_VL256); +} + +uint64_t test_svcnth_pat_14() +{ + // CHECK-LABEL: test_svcnth_pat_14 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 29) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_MUL4); +} + +uint64_t test_svcnth_pat_15() +{ + // CHECK-LABEL: test_svcnth_pat_15 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 30) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_MUL3); +} + +uint64_t test_svcnth_pat_16() +{ + // CHECK-LABEL: test_svcnth_pat_16 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cnth(i32 31) + // CHECK: ret i64 %[[INTRINSIC]] + return svcnth_pat(SV_ALL); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c new file mode 100644 index 000000000000..be03d50b891f --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c @@ -0,0 +1,139 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s + +#include + +uint64_t test_svcntw_pat() +{ + // CHECK-LABEL: test_svcntw_pat + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 0) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_POW2); +} + +uint64_t test_svcntw_pat_1() +{ + // CHECK-LABEL: test_svcntw_pat_1 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 1) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL1); +} + +uint64_t test_svcntw_pat_2() +{ + // CHECK-LABEL: test_svcntw_pat_2 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 2) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL2); +} + +uint64_t test_svcntw_pat_3() +{ + // CHECK-LABEL: test_svcntw_pat_3 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 3) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL3); +} + +uint64_t test_svcntw_pat_4() +{ + // CHECK-LABEL: test_svcntw_pat_4 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 4) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL4); +} + +uint64_t test_svcntw_pat_5() +{ + // CHECK-LABEL: test_svcntw_pat_5 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 5) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL5); +} + +uint64_t test_svcntw_pat_6() +{ + // CHECK-LABEL: test_svcntw_pat_6 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 6) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL6); +} + +uint64_t test_svcntw_pat_7() +{ + // CHECK-LABEL: test_svcntw_pat_7 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 7) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL7); +} + +uint64_t test_svcntw_pat_8() +{ + // CHECK-LABEL: test_svcntw_pat_8 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 8) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL8); +} + +uint64_t test_svcntw_pat_9() +{ + // CHECK-LABEL: test_svcntw_pat_9 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 9) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL16); +} + +uint64_t test_svcntw_pat_10() +{ + // CHECK-LABEL: test_svcntw_pat_10 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 10) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL32); +} + +uint64_t test_svcntw_pat_11() +{ + // CHECK-LABEL: test_svcntw_pat_11 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 11) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL64); +} + +uint64_t test_svcntw_pat_12() +{ + // CHECK-LABEL: test_svcntw_pat_12 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 12) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL128); +} + +uint64_t test_svcntw_pat_13() +{ + // CHECK-LABEL: test_svcntw_pat_13 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 13) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_VL256); +} + +uint64_t test_svcntw_pat_14() +{ + // CHECK-LABEL: test_svcntw_pat_14 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 29) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_MUL4); +} + +uint64_t test_svcntw_pat_15() +{ + // CHECK-LABEL: test_svcntw_pat_15 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 30) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_MUL3); +} + +uint64_t test_svcntw_pat_16() +{ + // CHECK-LABEL: test_svcntw_pat_16 + // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 31) + // CHECK: ret i64 %[[INTRINSIC]] + return svcntw_pat(SV_ALL); +} diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c new file mode 100644 index 000000000000..89b6729dcbba --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c @@ -0,0 +1,18 @@ +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s + +#include + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +svbool_t test_svpfalse_b() +{ + // CHECK-LABEL: test_svpfalse_b + // CHECK: ret zeroinitializer + return SVE_ACLE_FUNC(svpfalse,_b,,)(); +} diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index b51047f89db8..287ff53d5186 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -264,6 +264,14 @@ public: llvm_unreachable("Unsupported imm check"); } + /// Returns the enum value for the flag type + uint64_t getEnumValueForFlag(StringRef C) const { + auto Res = FlagTypes.find(C); + if (Res != FlagTypes.end()) + return Res->getValue(); + llvm_unreachable("Unsupported flag"); + } + // Returns the SVETypeFlags for a given value and mask. uint64_t encodeFlag(uint64_t V, StringRef MaskName) const { auto It = FlagTypes.find(MaskName); @@ -528,6 +536,13 @@ void SVEType::applyModifier(char Mod) { Immediate = true; PredicatePattern = true; break; + case 'k': + Predicate = false; + Signed = true; + Float = false; + ElementBitwidth = Bitwidth = 32; + NumVectors = 0; + break; case 'l': Predicate = false; Signed = true; @@ -535,6 +550,20 @@ void SVEType::applyModifier(char Mod) { ElementBitwidth = Bitwidth = 64; NumVectors = 0; break; + case 'm': + Predicate = false; + Signed = false; + Float = false; + ElementBitwidth = Bitwidth = 32; + NumVectors = 0; + break; + case 'n': + Predicate = false; + Signed = false; + Float = false; + ElementBitwidth = Bitwidth = 64; + NumVectors = 0; + break; case 'S': Constant = true; Pointer = true; @@ -831,6 +860,13 @@ void SVEEmitter::createIntrinsic( for (auto FlagRec : FlagsList) Flags |= FlagRec->getValueAsInt("Value"); + // Create a dummy TypeSpec for non-overloaded builtins. + if (Types.empty()) { + assert((Flags & getEnumValueForFlag("IsOverloadNone")) && + "Expect TypeSpec for overloaded builtin!"); + Types = "i"; + } + // Extract type specs from string SmallVector TypeSpecs; TypeSpec Acc; -- GitLab From 43abef06f42d5f9bab4e8363207d5c486705f6b6 Mon Sep 17 00:00:00 2001 From: Victor Huang Date: Wed, 22 Apr 2020 10:45:01 -0500 Subject: [PATCH 104/910] [PowerPC][Future] Initial support for PCRel addressing for jump tables. Add initial support for PC Relative addressing to get jump table base address instead of using TOC. Differential Revision: https://reviews.llvm.org/D75931 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 13 +++++ llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll | 57 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 3c3a144a9b98..4f065dfd4f7c 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2602,6 +2602,9 @@ bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const { if (GlobalAddressSDNode *GAN = dyn_cast(N)) if (GAN->getTargetFlags() & PPCII::MO_PCREL_FLAG) return true; + if (JumpTableSDNode *JT = dyn_cast(N)) + if (JT->getTargetFlags() & PPCII::MO_PCREL_FLAG) + return true; return false; } @@ -2894,6 +2897,16 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast(Op); + // isUsingPCRelativeCalls() returns true when PCRelative is enabled + if (Subtarget.isUsingPCRelativeCalls()) { + SDLoc DL(JT); + EVT Ty = getPointerTy(DAG.getDataLayout()); + SDValue GA = + DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG); + SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA); + return MatAddr; + } + // 64-bit SVR4 ABI and AIX ABI code are always position-independent. // The actual address of the GlobalValue is stored in the TOC. if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { diff --git a/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll new file mode 100644 index 000000000000..a7d3ca7e6d73 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll @@ -0,0 +1,57 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefix=CHECK-R +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-use-absolute-jumptables \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefix=CHECK-A + +; This test checks for getting relative and absolute jump table base address +; using PC Relative addressing. + +define dso_local signext i32 @jumptable(i32 signext %param) { +; CHECK-R-LABEL: jumptable: +; CHECK-R: # %bb.1: # %entry +; CHECK-R-NEXT: rldic r4, r4 +; CHECK-R-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1 +; CHECK-R-NEXT: lwax r4, r4, r5 +; CHECK-R-NEXT: add r4, r4, r5 +; CHECK-R-NEXT: mtctr r4 +; CHECK-R-NEXT: bctr +; CHECK-A-LABEL: jumptable: +; CHECK-A: # %bb.1: # %entry +; CHECK-A-NEXT: rldic r4, r4 +; CHECK-A-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1 +; CHECK-A-NEXT: ldx r4, r4, r5 +; CHECK-A-NEXT: mtctr r4 +; CHECK-A-NEXT: bctr + +entry: + switch i32 %param, label %sw.default [ + i32 1, label %return + i32 2, label %sw.bb1 + i32 3, label %sw.bb2 + i32 4, label %sw.bb3 + i32 20, label %sw.bb4 + ] + +sw.bb1: ; preds = %entry + br label %return + +sw.bb2: ; preds = %entry + br label %return + +sw.bb3: ; preds = %entry + br label %return + +sw.bb4: ; preds = %entry + br label %return + +sw.default: ; preds = %entry + br label %return + +return: ; preds = %entry, %sw.default, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1 + %retval.0 = phi i32 [ -1, %sw.default ], [ 400, %sw.bb4 ], [ 16, %sw.bb3 ], + [ 9, %sw.bb2 ], [ 4, %sw.bb1 ], [ %param, %entry ] + ret i32 %retval.0 +} -- GitLab From 3df8135286a2180a8fadcdddfcf9d9c232fb6ad7 Mon Sep 17 00:00:00 2001 From: Mark Murray Date: Mon, 20 Apr 2020 16:21:46 +0100 Subject: [PATCH 105/910] [ARM][MC][Thumb] Recommit: Revert relocation for some pc-relative fixups. Summary: This commit recommits the reversion of https://reviews.llvm.org/D75039. Concensus appears to be in favour of assembly-time resolution of these ADR and LDR relocations, in line with GNU. The previous backout broke many lld tests, now fixed by Peter Smith in 61bccda9d9d920c72f49025f11e8601daeb096ec. Reviewers: psmith Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78301 --- .../Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 12 +++++------- .../ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 7 ------- llvm/test/MC/ARM/pcrel-global-rel.s | 18 ------------------ llvm/test/MC/ARM/pcrel-global.s | 8 ++++++++ llvm/test/MC/ARM/thumb1-relax-adr.s | 5 +---- llvm/test/MC/ARM/thumb1-relax-ldrlit.s | 5 +---- 6 files changed, 15 insertions(+), 40 deletions(-) delete mode 100644 llvm/test/MC/ARM/pcrel-global-rel.s diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 5407bc6f5ffe..6d7fd9f12da9 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -71,8 +71,7 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { // Name Offset (bits) Size (bits) Flags {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_ldst_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant}, {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant}, {"fixup_t2_pcrel_10", 0, 32, @@ -82,12 +81,10 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_t2_pcrel_9", 0, 32, IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_thumb_adr_pcrel_10", 0, 8, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant}, {"fixup_t2_adr_pcrel_12", 0, 32, - MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, + IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, @@ -119,7 +116,8 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, {"fixup_bfcsel_else_target", 0, 32, 0}, {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, - {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}}; + {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel} + }; const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { // This table *must* be in the order that the fixup_* kinds are defined in // ARMFixupKinds.h. diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp index f803671ac976..6bd6addcb6d4 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -147,13 +147,6 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, default: return ELF::R_ARM_THM_CALL; } - case ARM::fixup_thumb_adr_pcrel_10: - case ARM::fixup_arm_thumb_cp: - return ELF::R_ARM_THM_PC8; - case ARM::fixup_t2_adr_pcrel_12: - return ELF::R_ARM_THM_ALU_PREL_11_0; - case ARM::fixup_t2_ldst_pcrel_12: - return ELF::R_ARM_THM_PC12; case ARM::fixup_bf_target: return ELF::R_ARM_THM_BF16; case ARM::fixup_bfc_target: diff --git a/llvm/test/MC/ARM/pcrel-global-rel.s b/llvm/test/MC/ARM/pcrel-global-rel.s deleted file mode 100644 index f1a71e6db773..000000000000 --- a/llvm/test/MC/ARM/pcrel-global-rel.s +++ /dev/null @@ -1,18 +0,0 @@ -@ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t -@ RUN: llvm-readobj -r %t - -@ Check that for ELF targets we generate a relocation for a within section -@ pc-relative reference to a global symbol as it may be interposed and we won't -@ know till link time whether this is possible. -.thumb -.thumb_func - -.globl bar -bar: -adr r0, bar @ thumb_adr_pcrel_10 -adr.w r0, bar @ t2_adr_pcrel_12 -ldr.w pc, bar @ t2_ldst_pcrel_12 - -@ CHECK: 0x0 R_ARM_THM_ALU_PREL_11_0 bar 0x0 -@ CHECK-NEXT: 0x4 R_ARM_THM_ALU_PREL_11_0 bar 0x0 -@ CHECK-NEXT: 0x8 R_ARM_THM_PC12 bar 0x0 diff --git a/llvm/test/MC/ARM/pcrel-global.s b/llvm/test/MC/ARM/pcrel-global.s index c1ab43547532..cec6c1cb52f3 100644 --- a/llvm/test/MC/ARM/pcrel-global.s +++ b/llvm/test/MC/ARM/pcrel-global.s @@ -11,3 +11,11 @@ vldr d0, foo @ arm_pcrel_10 adr r2, foo @ arm_adr_pcrel_12 ldr r0, foo @ arm_ldst_pcrel_12 +.thumb +.thumb_func + +.globl bar +bar: +adr r0, bar @ thumb_adr_pcrel_10 +adr.w r0, bar @ t2_adr_pcrel_12 +ldr.w pc, bar @ t2_ldst_pcrel_12 diff --git a/llvm/test/MC/ARM/thumb1-relax-adr.s b/llvm/test/MC/ARM/thumb1-relax-adr.s index 213c96822536..3eb2a02ad1f4 100644 --- a/llvm/test/MC/ARM/thumb1-relax-adr.s +++ b/llvm/test/MC/ARM/thumb1-relax-adr.s @@ -1,11 +1,8 @@ @ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s @ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s -@ RUN: llvm-mc -triple thumbv6m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T1 %s -@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T2 %s +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s .global func1 _func1: adr r0, _func2 @ CHECK-ERROR: unsupported relocation on symbol -@ CHECK-ELF-T1: 0x0 R_ARM_THM_PC8 _func2 0x0 -@ CHECK-ELF-T2: 0x0 R_ARM_THM_ALU_PREL_11_0 _func2 0x0 diff --git a/llvm/test/MC/ARM/thumb1-relax-ldrlit.s b/llvm/test/MC/ARM/thumb1-relax-ldrlit.s index e65ee52de7cb..f9335842d85d 100644 --- a/llvm/test/MC/ARM/thumb1-relax-ldrlit.s +++ b/llvm/test/MC/ARM/thumb1-relax-ldrlit.s @@ -1,11 +1,8 @@ @ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s @ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s -@ RUN: llvm-mc -triple thumbv6m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T1 %s -@ RUN: llvm-mc -triple thumbv7m-none-eabi -filetype=obj %s -o - | llvm-readobj --relocs | FileCheck --check-prefix=CHECK-ELF-T2 %s +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s .global func1 _func1: ldr r0, _func2 @ CHECK-ERROR: unsupported relocation on symbol -@ CHECK-ELF-T1: 0x0 R_ARM_THM_PC8 _func2 0x0 -@ CHECK-ELF-T2: 0x0 R_ARM_THM_PC12 _func2 0x0 -- GitLab From 2dea3f129878e929e5d1f00b91a622eb1ec8be4e Mon Sep 17 00:00:00 2001 From: Christopher Tetreault Date: Wed, 22 Apr 2020 08:02:02 -0700 Subject: [PATCH 106/910] [SVE] Add new VectorType subclasses Summary: Introduce new types for fixed width and scalable vectors. Does not remove getNumElements yet so as to not break code during transition period. Reviewers: deadalnix, efriedma, sdesmalen, craig.topper, huntergr Reviewed By: sdesmalen Subscribers: jholewinski, arsenm, jvesely, nhaehnle, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, csigg, arpith-jacob, mgester, lucyrfox, liufengdb, kerbowa, Joonsoo, grosul1, frgossen, lldb-commits, tschuett, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm, #lldb Differential Revision: https://reviews.llvm.org/D77587 --- lldb/source/Expression/IRInterpreter.cpp | 3 +- llvm/include/llvm-c/Core.h | 5 +- llvm/include/llvm/IR/DataLayout.h | 3 +- llvm/include/llvm/IR/DerivedTypes.h | 71 +++++++++++++------ llvm/include/llvm/IR/Type.h | 38 +++++----- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 3 +- llvm/lib/CodeGen/ValueTypes.cpp | 6 +- llvm/lib/ExecutionEngine/ExecutionEngine.cpp | 35 ++++----- .../ExecutionEngine/Interpreter/Execution.cpp | 58 +++++++-------- llvm/lib/IR/AsmWriter.cpp | 3 +- llvm/lib/IR/Constants.cpp | 39 +++++----- llvm/lib/IR/Core.cpp | 6 +- llvm/lib/IR/DataLayout.cpp | 3 +- llvm/lib/IR/Type.cpp | 67 ++++++++++++----- llvm/lib/Linker/IRMover.cpp | 3 +- .../AMDGPU/AMDGPUHSAMetadataStreamer.cpp | 8 +-- .../AMDGPU/AMDGPUPrintfRuntimeBinding.cpp | 5 +- .../Hexagon/HexagonTargetObjectFile.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 6 +- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 3 +- .../Transforms/Utils/FunctionComparator.cpp | 3 +- llvm/tools/llvm-c-test/echo.cpp | 5 +- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp | 12 ++-- 23 files changed, 235 insertions(+), 152 deletions(-) diff --git a/lldb/source/Expression/IRInterpreter.cpp b/lldb/source/Expression/IRInterpreter.cpp index 3ae843f69d70..ddb2d975d554 100644 --- a/lldb/source/Expression/IRInterpreter.cpp +++ b/lldb/source/Expression/IRInterpreter.cpp @@ -597,7 +597,8 @@ bool IRInterpreter::CanInterpret(llvm::Module &module, llvm::Function &function, switch (operand_type->getTypeID()) { default: break; - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { LLDB_LOGF(log, "Unsupported operand type: %s", PrintType(operand_type).c_str()); error.SetErrorString(unsupported_operand_error); diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h index 852e16400f3a..2d6490dcbcf1 100644 --- a/llvm/include/llvm-c/Core.h +++ b/llvm/include/llvm-c/Core.h @@ -157,10 +157,11 @@ typedef enum { LLVMStructTypeKind, /**< Structures */ LLVMArrayTypeKind, /**< Arrays */ LLVMPointerTypeKind, /**< Pointers */ - LLVMVectorTypeKind, /**< SIMD 'packed' format, or other vector type */ LLVMMetadataTypeKind, /**< Metadata */ LLVMX86_MMXTypeKind, /**< X86 MMX */ - LLVMTokenTypeKind /**< Tokens */ + LLVMTokenTypeKind, /**< Tokens */ + LLVMFixedVectorTypeKind, /**< Fixed width SIMD vector type */ + LLVMScalableVectorTypeKind /**< Scalable SIMD vector type */ } LLVMTypeKind; typedef enum { diff --git a/llvm/include/llvm/IR/DataLayout.h b/llvm/include/llvm/IR/DataLayout.h index 98bdf30f5a46..010469c8107b 100644 --- a/llvm/include/llvm/IR/DataLayout.h +++ b/llvm/include/llvm/IR/DataLayout.h @@ -664,7 +664,8 @@ inline TypeSize DataLayout::getTypeSizeInBits(Type *Ty) const { // only 80 bits contain information. case Type::X86_FP80TyID: return TypeSize::Fixed(80); - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { VectorType *VTy = cast(Ty); auto EltCnt = VTy->getElementCount(); uint64_t MinBits = EltCnt.Min * diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h index 306d388cb8a7..75c48f301026 100644 --- a/llvm/include/llvm/IR/DerivedTypes.h +++ b/llvm/include/llvm/IR/DerivedTypes.h @@ -386,7 +386,7 @@ uint64_t Type::getArrayNumElements() const { return cast(this)->getNumElements(); } -/// Class to represent vector types. +/// Base class of all SIMD vector types class VectorType : public Type { /// A fully specified VectorType is of the form . 'n' is the /// minimum number of elements of type Ty contained within the vector, and @@ -403,24 +403,22 @@ class VectorType : public Type { /// The element type of the vector. Type *ContainedType; - /// Minumum number of elements in the vector. - uint64_t NumElements; - VectorType(Type *ElType, unsigned NumEl, bool Scalable = false); - VectorType(Type *ElType, ElementCount EC); + /// The element count of this vector + ElementCount EC; - // If true, the total number of elements is an unknown multiple of the - // minimum 'NumElements'. Otherwise the total number of elements is exactly - // equal to 'NumElements'. - bool Scalable; +protected: + VectorType(Type *ElType, ElementCount EC, Type::TypeID TID); public: VectorType(const VectorType &) = delete; VectorType &operator=(const VectorType &) = delete; - /// For scalable vectors, this will return the minimum number of elements - /// in the vector. - unsigned getNumElements() const { return NumElements; } + /// Get the number of elements in this vector. It does not make sense to call + /// this function on a scalable vector, and this will be moved into + /// FixedVectorType in a future commit + unsigned getNumElements() const { return EC.Min; } + Type *getElementType() const { return ContainedType; } /// This static method is the primary way to construct an VectorType. @@ -430,6 +428,10 @@ public: return VectorType::get(ElementType, {NumElements, Scalable}); } + static VectorType *get(Type *ElementType, const VectorType *Other) { + return VectorType::get(ElementType, Other->getElementCount()); + } + /// This static method gets a VectorType with the same number of elements as /// the input type, and the element type is an integer type of the same width /// as the input element type. @@ -507,26 +509,53 @@ public: /// Return an ElementCount instance to represent the (possibly scalable) /// number of elements in the vector. - ElementCount getElementCount() const { - uint64_t MinimumEltCnt = getNumElements(); - assert(MinimumEltCnt <= UINT_MAX && "Too many elements in vector"); - return { (unsigned)MinimumEltCnt, Scalable }; - } + ElementCount getElementCount() const { return EC; } /// Returns whether or not this is a scalable vector (meaning the total /// element count is a multiple of the minimum). - bool isScalable() const { - return Scalable; - } + bool isScalable() const { return EC.Scalable; } /// Methods for support type inquiry through isa, cast, and dyn_cast. static bool classof(const Type *T) { - return T->getTypeID() == VectorTyID; + return T->getTypeID() == FixedVectorTyID || + T->getTypeID() == ScalableVectorTyID; } }; bool Type::isVectorTy() const { return isa(this); } +/// Class to represent fixed width SIMD vectors +class FixedVectorType : public VectorType { +protected: + FixedVectorType(Type *ElTy, unsigned NumElts) + : VectorType(ElTy, {NumElts, false}, FixedVectorTyID) {} + +public: + static FixedVectorType *get(Type *ElementType, unsigned NumElts); + + static bool classof(const Type *T) { + return T->getTypeID() == FixedVectorTyID; + } +}; + +/// Class to represent scalable SIMD vectors +class ScalableVectorType : public VectorType { +protected: + ScalableVectorType(Type *ElTy, unsigned MinNumElts) + : VectorType(ElTy, {MinNumElts, true}, ScalableVectorTyID) {} + +public: + static ScalableVectorType *get(Type *ElementType, unsigned MinNumElts); + + /// Get the minimum number of elements in this vector. The actual number of + /// elements in the vector is an integer multiple of this value. + uint64_t getMinNumElements() const { return getElementCount().Min; } + + static bool classof(const Type *T) { + return T->getTypeID() == ScalableVectorTyID; + } +}; + /// Class to represent pointers. class PointerType : public Type { explicit PointerType(Type *ElType, unsigned AddrSpace); diff --git a/llvm/include/llvm/IR/Type.h b/llvm/include/llvm/IR/Type.h index 67be3ef480b7..618eee06dcf7 100644 --- a/llvm/include/llvm/IR/Type.h +++ b/llvm/include/llvm/IR/Type.h @@ -54,26 +54,27 @@ public: /// enum TypeID { // PrimitiveTypes - make sure LastPrimitiveTyID stays up to date. - VoidTyID = 0, ///< 0: type with no size - HalfTyID, ///< 1: 16-bit floating point type - FloatTyID, ///< 2: 32-bit floating point type - DoubleTyID, ///< 3: 64-bit floating point type - X86_FP80TyID, ///< 4: 80-bit floating point type (X87) - FP128TyID, ///< 5: 128-bit floating point type (112-bit mantissa) - PPC_FP128TyID, ///< 6: 128-bit floating point type (two 64-bits, PowerPC) - LabelTyID, ///< 7: Labels - MetadataTyID, ///< 8: Metadata - X86_MMXTyID, ///< 9: MMX vectors (64 bits, X86 specific) - TokenTyID, ///< 10: Tokens + VoidTyID = 0, ///< 0: type with no size + HalfTyID, ///< 1: 16-bit floating point type + FloatTyID, ///< 2: 32-bit floating point type + DoubleTyID, ///< 3: 64-bit floating point type + X86_FP80TyID, ///< 4: 80-bit floating point type (X87) + FP128TyID, ///< 5: 128-bit floating point type (112-bit mantissa) + PPC_FP128TyID, ///< 6: 128-bit floating point type (two 64-bits, PowerPC) + LabelTyID, ///< 7: Labels + MetadataTyID, ///< 8: Metadata + X86_MMXTyID, ///< 9: MMX vectors (64 bits, X86 specific) + TokenTyID, ///< 10: Tokens // Derived types... see DerivedTypes.h file. // Make sure FirstDerivedTyID stays up to date! - IntegerTyID, ///< 11: Arbitrary bit width integers - FunctionTyID, ///< 12: Functions - StructTyID, ///< 13: Structures - ArrayTyID, ///< 14: Arrays - PointerTyID, ///< 15: Pointers - VectorTyID ///< 16: SIMD 'packed' format, or other vector type + IntegerTyID, ///< 11: Arbitrary bit width integers + FunctionTyID, ///< 12: Functions + StructTyID, ///< 13: Structures + ArrayTyID, ///< 14: Arrays + PointerTyID, ///< 15: Pointers + FixedVectorTyID, ///< 16: Fixed width SIMD vector type + ScalableVectorTyID ///< 17: Scalable SIMD vector type }; private: @@ -266,8 +267,7 @@ public: return true; // If it is not something that can have a size (e.g. a function or label), // it doesn't have a size. - if (getTypeID() != StructTyID && getTypeID() != ArrayTyID && - getTypeID() != VectorTyID) + if (getTypeID() != StructTyID && getTypeID() != ArrayTyID && !isVectorTy()) return false; // Otherwise we have to try harder to decide. return isSizedDerivedType(Visited); diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index f6d0e40aa639..7a92c4bf1009 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -949,7 +949,8 @@ void ModuleBitcodeWriter::writeTypeTable() { AbbrevToUse = ArrayAbbrev; break; } - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { VectorType *VT = cast(T); // VECTOR [numelts, eltty] or // [numelts, eltty, scalable] diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp index eac07be08a81..ae2606f8dba6 100644 --- a/llvm/lib/CodeGen/ValueTypes.cpp +++ b/llvm/lib/CodeGen/ValueTypes.cpp @@ -362,7 +362,8 @@ MVT MVT::getVT(Type *Ty, bool HandleUnknown){ case Type::FP128TyID: return MVT(MVT::f128); case Type::PPC_FP128TyID: return MVT(MVT::ppcf128); case Type::PointerTyID: return MVT(MVT::iPTR); - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { VectorType *VTy = cast(Ty); return getVectorVT( getVT(VTy->getElementType(), /*HandleUnknown=*/ false), @@ -380,7 +381,8 @@ EVT EVT::getEVT(Type *Ty, bool HandleUnknown){ return MVT::getVT(Ty, HandleUnknown); case Type::IntegerTyID: return getIntegerVT(Ty->getContext(), cast(Ty)->getBitWidth()); - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { VectorType *VTy = cast(Ty); return getVectorVT(Ty->getContext(), getEVT(VTy->getElementType(), /*HandleUnknown=*/ false), diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp index 64d313e28030..6e8f88e21c8b 100644 --- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp @@ -624,17 +624,18 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { } } break; - case Type::VectorTyID: - // if the whole vector is 'undef' just reserve memory for the value. - auto* VTy = cast(C->getType()); - Type *ElemTy = VTy->getElementType(); - unsigned int elemNum = VTy->getNumElements(); - Result.AggregateVal.resize(elemNum); - if (ElemTy->isIntegerTy()) - for (unsigned int i = 0; i < elemNum; ++i) - Result.AggregateVal[i].IntVal = - APInt(ElemTy->getPrimitiveSizeInBits(), 0); - break; + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: + // if the whole vector is 'undef' just reserve memory for the value. + auto *VTy = cast(C->getType()); + Type *ElemTy = VTy->getElementType(); + unsigned int elemNum = VTy->getNumElements(); + Result.AggregateVal.resize(elemNum); + if (ElemTy->isIntegerTy()) + for (unsigned int i = 0; i < elemNum; ++i) + Result.AggregateVal[i].IntVal = + APInt(ElemTy->getPrimitiveSizeInBits(), 0); + break; } return Result; } @@ -914,7 +915,8 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { else llvm_unreachable("Unknown constant pointer type!"); break; - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { unsigned elemNum; Type* ElemTy; const ConstantDataVector *CDV = dyn_cast(C); @@ -1006,8 +1008,7 @@ GenericValue ExecutionEngine::getConstantValue(const Constant *C) { break; } llvm_unreachable("Unknown constant pointer type!"); - } - break; + } break; default: SmallString<256> Msg; @@ -1046,7 +1047,8 @@ void ExecutionEngine::StoreValueToMemory(const GenericValue &Val, *((PointerTy*)Ptr) = Val.PointerVal; break; - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: for (unsigned i = 0; i < Val.AggregateVal.size(); ++i) { if (cast(Ty)->getElementType()->isDoubleTy()) *(((double*)Ptr)+i) = Val.AggregateVal[i].DoubleVal; @@ -1096,7 +1098,8 @@ void ExecutionEngine::LoadValueFromMemory(GenericValue &Result, Result.IntVal = APInt(80, y); break; } - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { auto *VT = cast(Ty); Type *ElemT = VT->getElementType(); const unsigned numElems = VT->getNumElements(); diff --git a/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp b/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp index 6332b92b122a..46fc1bbe0a6b 100644 --- a/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp +++ b/llvm/lib/ExecutionEngine/Interpreter/Execution.cpp @@ -169,13 +169,14 @@ static void executeFRemInst(GenericValue &Dest, GenericValue Src1, Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \ break; -#define IMPLEMENT_VECTOR_INTEGER_ICMP(OP, TY) \ - case Type::VectorTyID: { \ - assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \ - Dest.AggregateVal.resize( Src1.AggregateVal.size() ); \ - for( uint32_t _i=0;_i(Ty)->getElementType()->isFloatTy()) { \ - IMPLEMENT_VECTOR_FCMP_T(OP, Float); \ - } else { \ - IMPLEMENT_VECTOR_FCMP_T(OP, Double); \ +#define IMPLEMENT_VECTOR_FCMP(OP) \ + case Type::FixedVectorTyID: \ + case Type::ScalableVectorTyID: \ + if (cast(Ty)->getElementType()->isFloatTy()) { \ + IMPLEMENT_VECTOR_FCMP_T(OP, Float); \ + } else { \ + IMPLEMENT_VECTOR_FCMP_T(OP, Double); \ } static GenericValue executeFCMP_OEQ(GenericValue Src1, GenericValue Src2, @@ -1327,7 +1329,7 @@ GenericValue Interpreter::executeFPTruncInst(Value *SrcVal, Type *DstTy, ExecutionContext &SF) { GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcVal->getType()->getTypeID() == Type::VectorTyID) { + if (isa(SrcVal->getType())) { assert(SrcVal->getType()->getScalarType()->isDoubleTy() && DstTy->getScalarType()->isFloatTy() && "Invalid FPTrunc instruction"); @@ -1350,7 +1352,7 @@ GenericValue Interpreter::executeFPExtInst(Value *SrcVal, Type *DstTy, ExecutionContext &SF) { GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcVal->getType()->getTypeID() == Type::VectorTyID) { + if (isa(SrcVal->getType())) { assert(SrcVal->getType()->getScalarType()->isFloatTy() && DstTy->getScalarType()->isDoubleTy() && "Invalid FPExt instruction"); @@ -1373,7 +1375,7 @@ GenericValue Interpreter::executeFPToUIInst(Value *SrcVal, Type *DstTy, Type *SrcTy = SrcVal->getType(); GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcTy->getTypeID() == Type::VectorTyID) { + if (isa(SrcTy)) { Type *DstVecTy = DstTy->getScalarType(); Type *SrcVecTy = SrcTy->getScalarType(); uint32_t DBitWidth = cast(DstVecTy)->getBitWidth(); @@ -1411,7 +1413,7 @@ GenericValue Interpreter::executeFPToSIInst(Value *SrcVal, Type *DstTy, Type *SrcTy = SrcVal->getType(); GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcTy->getTypeID() == Type::VectorTyID) { + if (isa(SrcTy)) { Type *DstVecTy = DstTy->getScalarType(); Type *SrcVecTy = SrcTy->getScalarType(); uint32_t DBitWidth = cast(DstVecTy)->getBitWidth(); @@ -1447,7 +1449,7 @@ GenericValue Interpreter::executeUIToFPInst(Value *SrcVal, Type *DstTy, ExecutionContext &SF) { GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcVal->getType()->getTypeID() == Type::VectorTyID) { + if (isa(SrcVal->getType())) { Type *DstVecTy = DstTy->getScalarType(); unsigned size = Src.AggregateVal.size(); // the sizes of src and dst vectors must be equal @@ -1479,7 +1481,7 @@ GenericValue Interpreter::executeSIToFPInst(Value *SrcVal, Type *DstTy, ExecutionContext &SF) { GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if (SrcVal->getType()->getTypeID() == Type::VectorTyID) { + if (isa(SrcVal->getType())) { Type *DstVecTy = DstTy->getScalarType(); unsigned size = Src.AggregateVal.size(); // the sizes of src and dst vectors must be equal @@ -1540,8 +1542,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy, Type *SrcTy = SrcVal->getType(); GenericValue Dest, Src = getOperandValue(SrcVal, SF); - if ((SrcTy->getTypeID() == Type::VectorTyID) || - (DstTy->getTypeID() == Type::VectorTyID)) { + if (isa(SrcTy) || isa(DstTy)) { // vector src bitcast to vector dst or vector src bitcast to scalar dst or // scalar src bitcast to vector dst bool isLittleEndian = getDataLayout().isLittleEndian(); @@ -1553,7 +1554,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy, unsigned SrcNum; unsigned DstNum; - if (SrcTy->getTypeID() == Type::VectorTyID) { + if (isa(SrcTy)) { SrcElemTy = SrcTy->getScalarType(); SrcBitSize = SrcTy->getScalarSizeInBits(); SrcNum = Src.AggregateVal.size(); @@ -1566,7 +1567,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy, SrcVec.AggregateVal.push_back(Src); } - if (DstTy->getTypeID() == Type::VectorTyID) { + if (isa(DstTy)) { DstElemTy = DstTy->getScalarType(); DstBitSize = DstTy->getScalarSizeInBits(); DstNum = (SrcNum * SrcBitSize) / DstBitSize; @@ -1639,7 +1640,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy, } // convert result from integer to specified type - if (DstTy->getTypeID() == Type::VectorTyID) { + if (isa(DstTy)) { if (DstElemTy->isDoubleTy()) { Dest.AggregateVal.resize(DstNum); for (unsigned i = 0; i < DstNum; i++) @@ -1662,8 +1663,7 @@ GenericValue Interpreter::executeBitCastInst(Value *SrcVal, Type *DstTy, Dest.IntVal = TempDst.AggregateVal[0].IntVal; } } - } else { // if ((SrcTy->getTypeID() == Type::VectorTyID) || - // (DstTy->getTypeID() == Type::VectorTyID)) + } else { // if (isa(SrcTy)) || isa(DstTy)) // scalar src bitcast to scalar dst if (DstTy->isPointerTy()) { @@ -1954,7 +1954,8 @@ void Interpreter::visitExtractValueInst(ExtractValueInst &I) { break; case Type::ArrayTyID: case Type::StructTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: Dest.AggregateVal = pSrc->AggregateVal; break; case Type::PointerTyID: @@ -2001,7 +2002,8 @@ void Interpreter::visitInsertValueInst(InsertValueInst &I) { break; case Type::ArrayTyID: case Type::StructTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: pDest->AggregateVal = Src2.AggregateVal; break; case Type::PointerTyID: diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 5c04881d1af7..685bb948f974 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -650,7 +650,8 @@ void TypePrinting::print(Type *Ty, raw_ostream &OS) { OS << ']'; return; } - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { VectorType *PTy = cast(Ty); OS << "<"; if (PTy->isScalable()) diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index b86b747f7519..d180059ccf13 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -352,7 +352,8 @@ Constant *Constant::getNullValue(Type *Ty) { return ConstantPointerNull::get(cast(Ty)); case Type::StructTyID: case Type::ArrayTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: return ConstantAggregateZero::get(Ty); case Type::TokenTyID: return ConstantTokenNone::get(Ty->getContext()); @@ -1780,8 +1781,8 @@ Constant *ConstantExpr::getFPCast(Constant *C, Type *Ty) { Constant *ConstantExpr::getTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isIntOrIntVectorTy() && "Trunc operand must be integer"); @@ -1794,8 +1795,8 @@ Constant *ConstantExpr::getTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getSExt(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isIntOrIntVectorTy() && "SExt operand must be integral"); @@ -1808,8 +1809,8 @@ Constant *ConstantExpr::getSExt(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isIntOrIntVectorTy() && "ZEXt operand must be integral"); @@ -1822,8 +1823,8 @@ Constant *ConstantExpr::getZExt(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() && @@ -1834,8 +1835,8 @@ Constant *ConstantExpr::getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPExtend(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isFPOrFPVectorTy() && Ty->isFPOrFPVectorTy() && @@ -1846,8 +1847,8 @@ Constant *ConstantExpr::getFPExtend(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getUIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() && @@ -1857,8 +1858,8 @@ Constant *ConstantExpr::getUIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getSIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isIntOrIntVectorTy() && Ty->isFPOrFPVectorTy() && @@ -1868,8 +1869,8 @@ Constant *ConstantExpr::getSIToFP(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPToUI(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() && @@ -1879,8 +1880,8 @@ Constant *ConstantExpr::getFPToUI(Constant *C, Type *Ty, bool OnlyIfReduced) { Constant *ConstantExpr::getFPToSI(Constant *C, Type *Ty, bool OnlyIfReduced) { #ifndef NDEBUG - bool fromVec = C->getType()->getTypeID() == Type::VectorTyID; - bool toVec = Ty->getTypeID() == Type::VectorTyID; + bool fromVec = isa(C->getType()); + bool toVec = isa(Ty); #endif assert((fromVec == toVec) && "Cannot convert from scalar to/from vector"); assert(C->getType()->isFPOrFPVectorTy() && Ty->isIntOrIntVectorTy() && diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp index d7d6e97626d5..cfa1ebfe63c6 100644 --- a/llvm/lib/IR/Core.cpp +++ b/llvm/lib/IR/Core.cpp @@ -501,12 +501,14 @@ LLVMTypeKind LLVMGetTypeKind(LLVMTypeRef Ty) { return LLVMArrayTypeKind; case Type::PointerTyID: return LLVMPointerTypeKind; - case Type::VectorTyID: - return LLVMVectorTypeKind; case Type::X86_MMXTyID: return LLVMX86_MMXTypeKind; case Type::TokenTyID: return LLVMTokenTypeKind; + case Type::FixedVectorTyID: + return LLVMFixedVectorTypeKind; + case Type::ScalableVectorTyID: + return LLVMScalableVectorTypeKind; } llvm_unreachable("Unhandled TypeID."); } diff --git a/llvm/lib/IR/DataLayout.cpp b/llvm/lib/IR/DataLayout.cpp index c2ac1c3fa020..cb5038992cf8 100644 --- a/llvm/lib/IR/DataLayout.cpp +++ b/llvm/lib/IR/DataLayout.cpp @@ -739,7 +739,8 @@ Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const { AlignType = FLOAT_ALIGN; break; case Type::X86_MMXTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: AlignType = VECTOR_ALIGN; break; default: diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp index e8c693aedf64..b97b70167511 100644 --- a/llvm/lib/IR/Type.cpp +++ b/llvm/lib/IR/Type.cpp @@ -73,13 +73,10 @@ bool Type::canLosslesslyBitCastTo(Type *Ty) const { return getPrimitiveSizeInBits() == Ty->getPrimitiveSizeInBits(); // 64-bit fixed width vector types can be losslessly converted to x86mmx. - if (((isa(this) && - !cast(this)->getElementCount().Scalable) && - Ty->isX86_MMXTy()) && + if (((isa(this)) && Ty->isX86_MMXTy()) && getPrimitiveSizeInBits().getFixedSize() == 64) return true; - if ((isX86_MMXTy() && (isa(Ty) && - !cast(Ty)->getElementCount().Scalable)) && + if ((isX86_MMXTy() && isa(Ty)) && Ty->getPrimitiveSizeInBits().getFixedSize() == 64) return true; @@ -123,7 +120,8 @@ TypeSize Type::getPrimitiveSizeInBits() const { case Type::X86_MMXTyID: return TypeSize::Fixed(64); case Type::IntegerTyID: return TypeSize::Fixed(cast(this)->getBitWidth()); - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { const VectorType *VTy = cast(this); ElementCount EC = VTy->getElementCount(); TypeSize ETS = VTy->getElementType()->getPrimitiveSizeInBits(); @@ -586,30 +584,65 @@ bool ArrayType::isValidElementType(Type *ElemTy) { // VectorType Implementation //===----------------------------------------------------------------------===// -VectorType::VectorType(Type *ElType, ElementCount EC) - : Type(ElType->getContext(), VectorTyID), ContainedType(ElType), - NumElements(EC.Min), Scalable(EC.Scalable) { +VectorType::VectorType(Type *ElType, ElementCount EC, Type::TypeID TID) + : Type(ElType->getContext(), TID), ContainedType(ElType), EC(EC) { ContainedTys = &ContainedType; NumContainedTys = 1; } VectorType *VectorType::get(Type *ElementType, ElementCount EC) { - assert(EC.Min > 0 && "#Elements of a VectorType must be greater than 0"); + if (EC.Scalable) + return ScalableVectorType::get(ElementType, EC.Min); + else + return FixedVectorType::get(ElementType, EC.Min); +} + +bool VectorType::isValidElementType(Type *ElemTy) { + return ElemTy->isIntegerTy() || ElemTy->isFloatingPointTy() || + ElemTy->isPointerTy(); +} + +//===----------------------------------------------------------------------===// +// FixedVectorType Implementation +//===----------------------------------------------------------------------===// + +FixedVectorType *FixedVectorType::get(Type *ElementType, unsigned NumElts) { + assert(NumElts > 0 && "#Elements of a VectorType must be greater than 0"); assert(isValidElementType(ElementType) && "Element type of a VectorType must " "be an integer, floating point, or " "pointer type."); + ElementCount EC(NumElts, false); + LLVMContextImpl *pImpl = ElementType->getContext().pImpl; - VectorType *&Entry = ElementType->getContext().pImpl - ->VectorTypes[std::make_pair(ElementType, EC)]; + VectorType *&Entry = ElementType->getContext() + .pImpl->VectorTypes[std::make_pair(ElementType, EC)]; + if (!Entry) - Entry = new (pImpl->Alloc) VectorType(ElementType, EC); - return Entry; + Entry = new (pImpl->Alloc) FixedVectorType(ElementType, NumElts); + return cast(Entry); } -bool VectorType::isValidElementType(Type *ElemTy) { - return ElemTy->isIntegerTy() || ElemTy->isFloatingPointTy() || - ElemTy->isPointerTy(); +//===----------------------------------------------------------------------===// +// ScalableVectorType Implementation +//===----------------------------------------------------------------------===// + +ScalableVectorType *ScalableVectorType::get(Type *ElementType, + unsigned MinNumElts) { + assert(MinNumElts > 0 && "#Elements of a VectorType must be greater than 0"); + assert(isValidElementType(ElementType) && "Element type of a VectorType must " + "be an integer, floating point, or " + "pointer type."); + + ElementCount EC(MinNumElts, true); + + LLVMContextImpl *pImpl = ElementType->getContext().pImpl; + VectorType *&Entry = ElementType->getContext() + .pImpl->VectorTypes[std::make_pair(ElementType, EC)]; + + if (!Entry) + Entry = new (pImpl->Alloc) ScalableVectorType(ElementType, MinNumElts); + return cast(Entry); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp index df7c542d7077..ce1133583f7a 100644 --- a/llvm/lib/Linker/IRMover.cpp +++ b/llvm/lib/Linker/IRMover.cpp @@ -305,7 +305,8 @@ Type *TypeMapTy::get(Type *Ty, SmallPtrSet &Visited) { case Type::ArrayTyID: return *Entry = ArrayType::get(ElementTypes[0], cast(Ty)->getNumElements()); - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: return *Entry = VectorType::get(ElementTypes[0], cast(Ty)->getNumElements()); case Type::PointerTyID: diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp index 46778ccb3482..4e726c33a3d7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp @@ -152,7 +152,7 @@ ValueType MetadataStreamerV2::getValueType(Type *Ty, StringRef TypeName) const { return ValueType::F64; case Type::PointerTyID: return getValueType(Ty->getPointerElementType(), TypeName); - case Type::VectorTyID: + case Type::FixedVectorTyID: return getValueType(cast(Ty)->getElementType(), TypeName); default: return ValueType::Struct; @@ -185,7 +185,7 @@ std::string MetadataStreamerV2::getTypeName(Type *Ty, bool Signed) const { return "float"; case Type::DoubleTyID: return "double"; - case Type::VectorTyID: { + case Type::FixedVectorTyID: { auto VecTy = cast(Ty); auto ElTy = VecTy->getElementType(); auto NumElements = VecTy->getNumElements(); @@ -599,7 +599,7 @@ StringRef MetadataStreamerV3::getValueType(Type *Ty, StringRef TypeName) const { return "f64"; case Type::PointerTyID: return getValueType(Ty->getPointerElementType(), TypeName); - case Type::VectorTyID: + case Type::FixedVectorTyID: return getValueType(cast(Ty)->getElementType(), TypeName); default: return "struct"; @@ -632,7 +632,7 @@ std::string MetadataStreamerV3::getTypeName(Type *Ty, bool Signed) const { return "float"; case Type::DoubleTyID: return "double"; - case Type::VectorTyID: { + case Type::FixedVectorTyID: { auto VecTy = cast(Ty); auto ElTy = VecTy->getElementType(); auto NumElements = VecTy->getNumElements(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp index 881eb96b3794..543d38d553ac 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp @@ -408,8 +408,7 @@ bool AMDGPUPrintfRuntimeBinding::lowerPrintfForGpu( Value *Arg = CI->getArgOperand(ArgCount); Type *ArgType = Arg->getType(); SmallVector WhatToStore; - if (ArgType->isFPOrFPVectorTy() && - (ArgType->getTypeID() != Type::VectorTyID)) { + if (ArgType->isFPOrFPVectorTy() && !isa(ArgType)) { Type *IType = (ArgType->isFloatTy()) ? Int32Ty : Int64Ty; if (OpConvSpecifiers[ArgCount - 1] == 'f') { ConstantFP *fpCons = dyn_cast(Arg); @@ -478,7 +477,7 @@ bool AMDGPUPrintfRuntimeBinding::lowerPrintfForGpu( Arg = new PtrToIntInst(Arg, DstType, "PrintArgPtr", Brnch); WhatToStore.push_back(Arg); } - } else if (ArgType->getTypeID() == Type::VectorTyID) { + } else if (isa(ArgType)) { Type *IType = NULL; uint32_t EleCount = cast(ArgType)->getNumElements(); uint32_t EleSize = ArgType->getScalarSizeInBits(); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 1dc1a783e6da..6f74c6b8a8c1 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -307,7 +307,7 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, const ArrayType *ATy = cast(Ty); return getSmallestAddressableSize(ATy->getElementType(), GV, TM); } - case Type::VectorTyID: { + case Type::FixedVectorTyID: { const VectorType *PTy = cast(Ty); return getSmallestAddressableSize(PTy->getElementType(), GV, TM); } diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 6fcadfb5a160..c68ac5cd024a 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -1184,7 +1184,7 @@ void NVPTXAsmPrinter::printModuleLevelGV(const GlobalVariable *GVar, case Type::IntegerTyID: // Integers larger than 64 bits case Type::StructTyID: case Type::ArrayTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: ElementSize = DL.getTypeStoreSize(ETy); // Ptx allows variable initilization only for constant and // global state spaces. @@ -1358,7 +1358,7 @@ void NVPTXAsmPrinter::emitPTXGlobalVariable(const GlobalVariable *GVar, switch (ETy->getTypeID()) { case Type::StructTyID: case Type::ArrayTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: ElementSize = DL.getTypeStoreSize(ETy); O << " .b8 "; getSymbol(GVar)->print(O, MAI); @@ -1892,7 +1892,7 @@ void NVPTXAsmPrinter::bufferLEByte(const Constant *CPV, int Bytes, } case Type::ArrayTyID: - case Type::VectorTyID: + case Type::FixedVectorTyID: case Type::StructTyID: { if (isa(CPV) || isa(CPV)) { int ElementSize = DL.getTypeAllocSize(CPV->getType()); diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp index 94c872a34125..2f0783017ce6 100644 --- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp +++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp @@ -129,7 +129,8 @@ static bool isLeakCheckerRoot(GlobalVariable *GV) { default: break; case Type::PointerTyID: return true; - case Type::VectorTyID: + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: if (cast(Ty)->getElementType()->isPointerTy()) return true; break; diff --git a/llvm/lib/Transforms/Utils/FunctionComparator.cpp b/llvm/lib/Transforms/Utils/FunctionComparator.cpp index 0d5a882e9b0a..655ba9350b02 100644 --- a/llvm/lib/Transforms/Utils/FunctionComparator.cpp +++ b/llvm/lib/Transforms/Utils/FunctionComparator.cpp @@ -488,7 +488,8 @@ int FunctionComparator::cmpTypes(Type *TyL, Type *TyR) const { return cmpNumbers(STyL->getNumElements(), STyR->getNumElements()); return cmpTypes(STyL->getElementType(), STyR->getElementType()); } - case Type::VectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { auto *STyL = cast(TyL); auto *STyR = cast(TyR); if (STyL->getElementCount().Scalable != STyR->getElementCount().Scalable) diff --git a/llvm/tools/llvm-c-test/echo.cpp b/llvm/tools/llvm-c-test/echo.cpp index 710b5b053460..bf284da95935 100644 --- a/llvm/tools/llvm-c-test/echo.cpp +++ b/llvm/tools/llvm-c-test/echo.cpp @@ -137,7 +137,10 @@ struct TypeCloner { Clone(LLVMGetElementType(Src)), LLVMGetPointerAddressSpace(Src) ); - case LLVMVectorTypeKind: + case LLVMScalableVectorTypeKind: + // FIXME: scalable vectors unsupported + break; + case LLVMFixedVectorTypeKind: return LLVMVectorType( Clone(LLVMGetElementType(Src)), LLVMGetVectorSize(Src) diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp index bcab9af93b65..ffc47fca24d9 100644 --- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp +++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp @@ -168,12 +168,12 @@ LLVMType Importer::processType(llvm::Type *type) { return nullptr; return LLVMType::getArrayTy(elementType, type->getArrayNumElements()); } - case llvm::Type::VectorTyID: { - auto *typeVTy = llvm::cast(type); - if (typeVTy->isScalable()) { - emitError(unknownLoc) << "scalable vector types not supported"; - return nullptr; - } + case llvm::Type::ScalableVectorTyID: { + emitError(unknownLoc) << "scalable vector types not supported"; + return nullptr; + } + case llvm::Type::FixedVectorTyID: { + auto *typeVTy = llvm::cast(type); LLVMType elementType = processType(typeVTy->getElementType()); if (!elementType) return nullptr; -- GitLab From 68a27587c2acb9b8772d75e552adcc22836844c2 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Wed, 22 Apr 2020 10:17:32 -0500 Subject: [PATCH 107/910] [OpenMP][FIX] Do not use InaccessibleMemOrArgMemOnly for barrier and flush This was reported as PR45635, committed first as 72a9e7c926f4e32f209e528ec407fe526da5587e, reverted by 188f5cde9635a29a3f20ee2a73abd02890a752c7, and now recommitted with the test change. --- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 16 ++++------------ llvm/test/Transforms/OpenMP/add_attributes.ll | 16 ++++++++-------- 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 1a82d772d26a..7599a7c98175 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -389,24 +389,16 @@ __OMP_ATTRS_SET(SetterAttrs, #define __OMP_RTL_ATTRS(Name, FnAttrSet, RetAttrSet, ArgAttrSets) \ OMP_RTL_ATTRS(OMPRTL_##Name, FnAttrSet, RetAttrSet, ArgAttrSets) -__OMP_RTL_ATTRS(__kmpc_barrier, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_barrier, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_cancel, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_cancel_barrier, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_flush, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_cancel_barrier, AttributeSet(), AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_flush, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_global_thread_num, GetterAttrs, AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_fork_call, AttributeSet(EnumAttr(NoUnwind)), AttributeSet(), {}) -__OMP_RTL_ATTRS(__kmpc_omp_taskwait, - AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), - AttributeSet(), {}) +__OMP_RTL_ATTRS(__kmpc_omp_taskwait, AttributeSet(), AttributeSet(), {}) __OMP_RTL_ATTRS(__kmpc_omp_taskyield, AttributeSet(EnumAttr(InaccessibleMemOrArgMemOnly)), AttributeSet(), {}) diff --git a/llvm/test/Transforms/OpenMP/add_attributes.ll b/llvm/test/Transforms/OpenMP/add_attributes.ll index 017bc1382e06..2536ea4a8cdc 100644 --- a/llvm/test/Transforms/OpenMP/add_attributes.ll +++ b/llvm/test/Transforms/OpenMP/add_attributes.ll @@ -720,17 +720,17 @@ declare void @__kmpc_end_critical(%struct.ident_t*, i32, [8 x i32]*) ; CHECK: ; Function Attrs: nounwind ; CHECK-NEXT: declare dso_local i32 @omp_get_supported_active_levels() #0 -; CHECK: Function Attrs: inaccessiblemem_or_argmemonly -; CHECK-NEXT: declare void @__kmpc_barrier(%struct.ident_t*, i32) +; CHECK-NOT: Function Attrs +; CHECK: declare void @__kmpc_barrier(%struct.ident_t*, i32) ; CHECK: Function Attrs: inaccessiblemem_or_argmemonly ; CHECK-NEXT: declare i32 @__kmpc_cancel(%struct.ident_t*, i32, i32) -; CHECK: Function Attrs: inaccessiblemem_or_argmemonly -; CHECK-NEXT: declare i32 @__kmpc_cancel_barrier(%struct.ident_t*, i32) +; CHECK-NOT: Function Attrs +; CHECK: declare i32 @__kmpc_cancel_barrier(%struct.ident_t*, i32) -; CHECK: Function Attrs: inaccessiblemem_or_argmemonly -; CHECK-NEXT: declare void @__kmpc_flush(%struct.ident_t*) +; CHECK-NOT: Function Attrs +; CHECK: declare void @__kmpc_flush(%struct.ident_t*) ; CHECK: Function Attrs: nounwind ; CHECK-NEXT: declare i32 @__kmpc_global_thread_num(%struct.ident_t*) @@ -738,8 +738,8 @@ declare void @__kmpc_end_critical(%struct.ident_t*, i32, [8 x i32]*) ; CHECK: Function Attrs: nounwind ; CHECK-NEXT: declare void @__kmpc_fork_call(%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) -; CHECK: Function Attrs: inaccessiblemem_or_argmemonly -; CHECK-NEXT: declare i32 @__kmpc_omp_taskwait(%struct.ident_t*, i32) +; CHECK-NOT: Function Attrs +; CHECK: declare i32 @__kmpc_omp_taskwait(%struct.ident_t*, i32) ; CHECK: Function Attrs: inaccessiblemem_or_argmemonly ; CHECK-NEXT: declare i32 @__kmpc_omp_taskyield(%struct.ident_t*, i32, i32) -- GitLab From e57361c055d7617ee25cdac8167625000d098ef5 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Wed, 22 Apr 2020 08:48:31 -0700 Subject: [PATCH 108/910] [lldb/Host] Remove TaskPool and replace its uses with llvm::ThreadPool Remove LLDB's TaskPool and replace its uses with LLVM's ThreadPool. Differential revision: https://reviews.llvm.org/D78337 --- lldb/include/lldb/Host/TaskPool.h | 92 ------------- lldb/include/lldb/module.modulemap | 1 - lldb/source/Host/CMakeLists.txt | 1 - lldb/source/Host/common/TaskPool.cpp | 126 ------------------ .../SymbolFile/DWARF/ManualDWARFIndex.cpp | 34 +++-- lldb/unittests/Host/CMakeLists.txt | 1 - lldb/unittests/Host/TaskPoolTest.cpp | 45 ------- 7 files changed, 21 insertions(+), 279 deletions(-) delete mode 100644 lldb/include/lldb/Host/TaskPool.h delete mode 100644 lldb/source/Host/common/TaskPool.cpp delete mode 100644 lldb/unittests/Host/TaskPoolTest.cpp diff --git a/lldb/include/lldb/Host/TaskPool.h b/lldb/include/lldb/Host/TaskPool.h deleted file mode 100644 index bb91d807ed2c..000000000000 --- a/lldb/include/lldb/Host/TaskPool.h +++ /dev/null @@ -1,92 +0,0 @@ -//===--------------------- TaskPool.h ---------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_HOST_TASKPOOL_H -#define LLDB_HOST_TASKPOOL_H - -#include "llvm/ADT/STLExtras.h" -#include -#include -#include -#include -#include -#include - -namespace lldb_private { - -// Global TaskPool class for running tasks in parallel on a set of worker -// thread created the first time the task pool is used. The TaskPool provide no -// guarantee about the order the task will be run and about what tasks will run -// in parallel. None of the task added to the task pool should block on -// something (mutex, future, condition variable) what will be set only by the -// completion of an other task on the task pool as they may run on the same -// thread sequentally. -class TaskPool { -public: - // Add a new task to the task pool and return a std::future belonging to the - // newly created task. The caller of this function has to wait on the future - // for this task to complete. - template - static std::future::type> - AddTask(F &&f, Args &&... args); - - // Run all of the specified tasks on the task pool and wait until all of them - // are finished before returning. This method is intended to be used for - // small number tasks where listing them as function arguments is acceptable. - // For running large number of tasks you should use AddTask for each task and - // then call wait() on each returned future. - template static void RunTasks(T &&... tasks); - -private: - TaskPool() = delete; - - template struct RunTaskImpl; - - static void AddTaskImpl(std::function &&task_fn); -}; - -template -std::future::type> -TaskPool::AddTask(F &&f, Args &&... args) { - auto task_sp = std::make_shared< - std::packaged_task::type()>>( - std::bind(std::forward(f), std::forward(args)...)); - - AddTaskImpl([task_sp]() { (*task_sp)(); }); - - return task_sp->get_future(); -} - -template void TaskPool::RunTasks(T &&... tasks) { - RunTaskImpl::Run(std::forward(tasks)...); -} - -template -struct TaskPool::RunTaskImpl { - static void Run(Head &&h, Tail &&... t) { - auto f = AddTask(std::forward(h)); - RunTaskImpl::Run(std::forward(t)...); - f.wait(); - } -}; - -template <> struct TaskPool::RunTaskImpl<> { - static void Run() {} -}; - -// Run 'func' on every value from begin .. end-1. Each worker will grab -// 'batch_size' numbers at a time to work on, so for very fast functions, batch -// should be large enough to avoid too much cache line contention. -void TaskMapOverInt(size_t begin, size_t end, - const llvm::function_ref &func); - -unsigned GetHardwareConcurrencyHint(); - -} // namespace lldb_private - -#endif // LLDB_HOST_TASKPOOL_H diff --git a/lldb/include/lldb/module.modulemap b/lldb/include/lldb/module.modulemap index e668abe1c6ae..7feea8ee99c3 100644 --- a/lldb/include/lldb/module.modulemap +++ b/lldb/include/lldb/module.modulemap @@ -49,7 +49,6 @@ module lldb_Host { module SocketAddress { header "Host/SocketAddress.h" export * } module Socket { header "Host/Socket.h" export * } module StringConvert { textual header "Host/StringConvert.h" export * } - module TaskPool { header "Host/TaskPool.h" export * } module Terminal { header "Host/Terminal.h" export * } module ThreadLauncher { header "Host/ThreadLauncher.h" export * } module Time { header "Host/Time.h" export * } diff --git a/lldb/source/Host/CMakeLists.txt b/lldb/source/Host/CMakeLists.txt index 357140432010..2837c0c5e3a1 100644 --- a/lldb/source/Host/CMakeLists.txt +++ b/lldb/source/Host/CMakeLists.txt @@ -30,7 +30,6 @@ add_host_subdirectory(common common/SocketAddress.cpp common/Socket.cpp common/StringConvert.cpp - common/TaskPool.cpp common/TCPSocket.cpp common/Terminal.cpp common/ThreadLauncher.cpp diff --git a/lldb/source/Host/common/TaskPool.cpp b/lldb/source/Host/common/TaskPool.cpp deleted file mode 100644 index 994ca375499f..000000000000 --- a/lldb/source/Host/common/TaskPool.cpp +++ /dev/null @@ -1,126 +0,0 @@ -//===-- TaskPool.cpp ------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "lldb/Host/TaskPool.h" -#include "lldb/Host/ThreadLauncher.h" -#include "lldb/Utility/Log.h" - -#include -#include -#include - -namespace lldb_private { - -namespace { -class TaskPoolImpl { -public: - static TaskPoolImpl &GetInstance(); - - void AddTask(std::function &&task_fn); - -private: - TaskPoolImpl(); - - static lldb::thread_result_t WorkerPtr(void *pool); - - static void Worker(TaskPoolImpl *pool); - - std::queue> m_tasks; - std::mutex m_tasks_mutex; - uint32_t m_thread_count; -}; - -} // end of anonymous namespace - -TaskPoolImpl &TaskPoolImpl::GetInstance() { - static TaskPoolImpl g_task_pool_impl; - return g_task_pool_impl; -} - -void TaskPool::AddTaskImpl(std::function &&task_fn) { - TaskPoolImpl::GetInstance().AddTask(std::move(task_fn)); -} - -TaskPoolImpl::TaskPoolImpl() : m_thread_count(0) {} - -unsigned GetHardwareConcurrencyHint() { - // std::thread::hardware_concurrency may return 0 if the value is not well - // defined or not computable. - static const unsigned g_hardware_concurrency = - std::max(1u, std::thread::hardware_concurrency()); - return g_hardware_concurrency; -} - -void TaskPoolImpl::AddTask(std::function &&task_fn) { - const size_t min_stack_size = 8 * 1024 * 1024; - - std::unique_lock lock(m_tasks_mutex); - m_tasks.emplace(std::move(task_fn)); - if (m_thread_count < GetHardwareConcurrencyHint()) { - m_thread_count++; - // Note that this detach call needs to happen with the m_tasks_mutex held. - // This prevents the thread from exiting prematurely and triggering a linux - // libc bug (https://sourceware.org/bugzilla/show_bug.cgi?id=19951). - llvm::Expected host_thread = - lldb_private::ThreadLauncher::LaunchThread( - "task-pool.worker", WorkerPtr, this, min_stack_size); - if (host_thread) { - host_thread->Release(); - } else { - LLDB_LOG(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_HOST), - "failed to launch host thread: {}", - llvm::toString(host_thread.takeError())); - } - } -} - -lldb::thread_result_t TaskPoolImpl::WorkerPtr(void *pool) { - Worker((TaskPoolImpl *)pool); - return {}; -} - -void TaskPoolImpl::Worker(TaskPoolImpl *pool) { - while (true) { - std::unique_lock lock(pool->m_tasks_mutex); - if (pool->m_tasks.empty()) { - pool->m_thread_count--; - break; - } - - std::function f = std::move(pool->m_tasks.front()); - pool->m_tasks.pop(); - lock.unlock(); - - f(); - } -} - -void TaskMapOverInt(size_t begin, size_t end, - const llvm::function_ref &func) { - const size_t num_workers = std::min(end, GetHardwareConcurrencyHint()); - std::atomic idx{begin}; - - auto wrapper = [&idx, end, &func]() { - while (true) { - size_t i = idx.fetch_add(1); - if (i >= end) - break; - func(i); - } - }; - - std::vector> futures; - futures.reserve(num_workers); - for (size_t i = 0; i < num_workers; i++) - futures.push_back(TaskPool::AddTask(wrapper)); - for (size_t i = 0; i < num_workers; i++) - futures[i].wait(); -} - -} // namespace lldb_private - diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp index f405a2189429..7bf4b52bc783 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp @@ -13,10 +13,10 @@ #include "Plugins/SymbolFile/DWARF/LogChannelDWARF.h" #include "Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h" #include "lldb/Core/Module.h" -#include "lldb/Host/TaskPool.h" #include "lldb/Symbol/ObjectFile.h" #include "lldb/Utility/Stream.h" #include "lldb/Utility/Timer.h" +#include "llvm/Support/ThreadPool.h" using namespace lldb_private; using namespace lldb; @@ -71,20 +71,27 @@ void ManualDWARFIndex::Index() { clear_cu_dies[cu_idx] = units_to_index[cu_idx]->ExtractDIEsScoped(); }; + // Share one thread pool across operations to avoid the overhead of + // recreating the threads. + llvm::ThreadPool pool; + // Create a task runner that extracts dies for each DWARF unit in a - // separate thread + // separate thread. // First figure out which units didn't have their DIEs already // parsed and remember this. If no DIEs were parsed prior to this index // function call, we are going to want to clear the CU dies after we are // done indexing to make sure we don't pull in all DWARF dies, but we need // to wait until all units have been indexed in case a DIE in one // unit refers to another and the indexes accesses those DIEs. - TaskMapOverInt(0, units_to_index.size(), extract_fn); + for (size_t i = 0; i < units_to_index.size(); ++i) + pool.async(extract_fn, i); + pool.wait(); // Now create a task runner that can index each DWARF unit in a // separate thread so we can index quickly. - - TaskMapOverInt(0, units_to_index.size(), parser_fn); + for (size_t i = 0; i < units_to_index.size(); ++i) + pool.async(parser_fn, i); + pool.wait(); auto finalize_fn = [this, &sets](NameToDIE(IndexSet::*index)) { NameToDIE &result = m_set.*index; @@ -93,14 +100,15 @@ void ManualDWARFIndex::Index() { result.Finalize(); }; - TaskPool::RunTasks([&]() { finalize_fn(&IndexSet::function_basenames); }, - [&]() { finalize_fn(&IndexSet::function_fullnames); }, - [&]() { finalize_fn(&IndexSet::function_methods); }, - [&]() { finalize_fn(&IndexSet::function_selectors); }, - [&]() { finalize_fn(&IndexSet::objc_class_selectors); }, - [&]() { finalize_fn(&IndexSet::globals); }, - [&]() { finalize_fn(&IndexSet::types); }, - [&]() { finalize_fn(&IndexSet::namespaces); }); + pool.async(finalize_fn, &IndexSet::function_basenames); + pool.async(finalize_fn, &IndexSet::function_fullnames); + pool.async(finalize_fn, &IndexSet::function_methods); + pool.async(finalize_fn, &IndexSet::function_selectors); + pool.async(finalize_fn, &IndexSet::objc_class_selectors); + pool.async(finalize_fn, &IndexSet::globals); + pool.async(finalize_fn, &IndexSet::types); + pool.async(finalize_fn, &IndexSet::namespaces); + pool.wait(); } void ManualDWARFIndex::IndexUnit(DWARFUnit &unit, SymbolFileDWARFDwo *dwp, diff --git a/lldb/unittests/Host/CMakeLists.txt b/lldb/unittests/Host/CMakeLists.txt index b88aa97a9005..663645c986f0 100644 --- a/lldb/unittests/Host/CMakeLists.txt +++ b/lldb/unittests/Host/CMakeLists.txt @@ -11,7 +11,6 @@ set (FILES SocketAddressTest.cpp SocketTest.cpp SocketTestUtilities.cpp - TaskPoolTest.cpp ) if (CMAKE_SYSTEM_NAME MATCHES "Linux|Android") diff --git a/lldb/unittests/Host/TaskPoolTest.cpp b/lldb/unittests/Host/TaskPoolTest.cpp deleted file mode 100644 index fea544267957..000000000000 --- a/lldb/unittests/Host/TaskPoolTest.cpp +++ /dev/null @@ -1,45 +0,0 @@ -#include "gtest/gtest.h" - -#include "lldb/Host/TaskPool.h" - -using namespace lldb_private; - -TEST(TaskPoolTest, AddTask) { - auto fn = [](int x) { return x * x + 1; }; - - auto f1 = TaskPool::AddTask(fn, 1); - auto f2 = TaskPool::AddTask(fn, 2); - auto f3 = TaskPool::AddTask(fn, 3); - auto f4 = TaskPool::AddTask(fn, 4); - - ASSERT_EQ(10, f3.get()); - ASSERT_EQ(2, f1.get()); - ASSERT_EQ(17, f4.get()); - ASSERT_EQ(5, f2.get()); -} - -TEST(TaskPoolTest, RunTasks) { - std::vector r(4); - - auto fn = [](int x, int &y) { y = x * x + 1; }; - - TaskPool::RunTasks([fn, &r]() { fn(1, r[0]); }, [fn, &r]() { fn(2, r[1]); }, - [fn, &r]() { fn(3, r[2]); }, [fn, &r]() { fn(4, r[3]); }); - - ASSERT_EQ(2, r[0]); - ASSERT_EQ(5, r[1]); - ASSERT_EQ(10, r[2]); - ASSERT_EQ(17, r[3]); -} - -TEST(TaskPoolTest, TaskMap) { - int data[4]; - auto fn = [&data](int x) { data[x] = x * x; }; - - TaskMapOverInt(0, 4, fn); - - ASSERT_EQ(data[0], 0); - ASSERT_EQ(data[1], 1); - ASSERT_EQ(data[2], 4); - ASSERT_EQ(data[3], 9); -} -- GitLab From 1009177d498f45b59a3e6490a5e222cafc7993a7 Mon Sep 17 00:00:00 2001 From: Denis Khalikov Date: Mon, 20 Apr 2020 23:31:24 +0300 Subject: [PATCH 109/910] [mlir][vulkan-runner] Add support for integer types. Summary: Add support for memrefs with element type as integer type and simple test. Differential Revision: https://reviews.llvm.org/D78560 --- ...ConvertGPULaunchFuncToVulkanLaunchFunc.cpp | 8 +- .../ConvertLaunchFuncToVulkanCalls.cpp | 98 +++++++++++-------- mlir/test/mlir-vulkan-runner/addi.mlir | 52 ++++++++++ .../vulkan-runtime-wrappers.cpp | 54 ++++++++++ 4 files changed, 167 insertions(+), 45 deletions(-) create mode 100644 mlir/test/mlir-vulkan-runner/addi.mlir diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp index 26588049b939..d6908680d798 100644 --- a/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp +++ b/mlir/lib/Conversion/GPUToVulkan/ConvertGPULaunchFuncToVulkanLaunchFunc.cpp @@ -54,10 +54,12 @@ private: /// Checks where the given type is supported by Vulkan runtime. bool isSupportedType(Type type) { - // TODO(denis0x0D): Handle other types. - if (auto memRefType = type.dyn_cast_or_null()) + if (auto memRefType = type.dyn_cast_or_null()) { + auto elementType = memRefType.getElementType(); return memRefType.hasRank() && - (memRefType.getRank() >= 1 && memRefType.getRank() <= 3); + (memRefType.getRank() >= 1 && memRefType.getRank() <= 3) && + (elementType.isIntOrFloat()); + } return false; } diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp index 4a481bf959da..bc13d177a62e 100644 --- a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp +++ b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp @@ -30,6 +30,9 @@ using namespace mlir; static constexpr const char *kBindMemRef1DFloat = "bindMemRef1DFloat"; static constexpr const char *kBindMemRef2DFloat = "bindMemRef2DFloat"; static constexpr const char *kBindMemRef3DFloat = "bindMemRef3DFloat"; +static constexpr const char *kBindMemRef1DInt = "bindMemRef1DInt"; +static constexpr const char *kBindMemRef2DInt = "bindMemRef2DInt"; +static constexpr const char *kBindMemRef3DInt = "bindMemRef3DInt"; static constexpr const char *kCInterfaceVulkanLaunch = "_mlir_ciface_vulkanLaunch"; static constexpr const char *kDeinitVulkan = "deinitVulkan"; @@ -73,12 +76,15 @@ private: llvmPointerType = LLVM::LLVMType::getInt8PtrTy(llvmDialect); llvmInt32Type = LLVM::LLVMType::getInt32Ty(llvmDialect); llvmInt64Type = LLVM::LLVMType::getInt64Ty(llvmDialect); - llvmMemRef1DFloat = getMemRefType(1); - llvmMemRef2DFloat = getMemRefType(2); - llvmMemRef3DFloat = getMemRefType(3); + llvmMemRef1DFloat = getMemRefType(1, llvmFloatType); + llvmMemRef2DFloat = getMemRefType(2, llvmFloatType); + llvmMemRef3DFloat = getMemRefType(3, llvmFloatType); + llvmMemRef1DInt = getMemRefType(1, llvmInt32Type); + llvmMemRef2DInt = getMemRefType(2, llvmInt32Type); + llvmMemRef3DInt = getMemRefType(3, llvmInt32Type); } - LLVM::LLVMType getMemRefType(uint32_t rank) { + LLVM::LLVMType getMemRefType(uint32_t rank, LLVM::LLVMType elemenType) { // According to the MLIR doc memref argument is converted into a // pointer-to-struct argument of type: // template @@ -89,15 +95,16 @@ private: // int64_t sizes[Rank]; // omitted when rank == 0 // int64_t strides[Rank]; // omitted when rank == 0 // }; - auto llvmPtrToFloatType = getFloatType().getPointerTo(); + auto llvmPtrToElementType = elemenType.getPointerTo(); auto llvmArrayRankElementSizeType = LLVM::LLVMType::getArrayTy(getInt64Type(), rank); // Create a type - // `!llvm<"{ float*, float*, i64, [`rank` x i64], [`rank` x i64]}">`. + // `!llvm<"{ `element-type`*, `element-type`*, i64, + // [`rank` x i64], [`rank` x i64]}">`. return LLVM::LLVMType::getStructTy( llvmDialect, - {llvmPtrToFloatType, llvmPtrToFloatType, getInt64Type(), + {llvmPtrToElementType, llvmPtrToElementType, getInt64Type(), llvmArrayRankElementSizeType, llvmArrayRankElementSizeType}); } @@ -109,6 +116,9 @@ private: LLVM::LLVMType getMemRef1DFloat() { return llvmMemRef1DFloat; } LLVM::LLVMType getMemRef2DFloat() { return llvmMemRef2DFloat; } LLVM::LLVMType getMemRef3DFloat() { return llvmMemRef3DFloat; } + LLVM::LLVMType getMemRef1DInt() { return llvmMemRef1DInt; } + LLVM::LLVMType getMemRef2DInt() { return llvmMemRef2DInt; } + LLVM::LLVMType getMemRef3DInt() { return llvmMemRef3DInt; } /// Creates a LLVM global for the given `name`. Value createEntryPointNameConstant(StringRef name, Location loc, @@ -142,8 +152,19 @@ private: /// Collects SPIRV attributes from the given `vulkanLaunchCallOp`. void collectSPIRVAttributes(LLVM::CallOp vulkanLaunchCallOp); - /// Deduces a rank from the given 'ptrToMemRefDescriptor`. - LogicalResult deduceMemRefRank(Value ptrToMemRefDescriptor, uint32_t &rank); + /// Deduces a rank and element type from the given 'ptrToMemRefDescriptor`. + LogicalResult deduceMemRefRankAndType(Value ptrToMemRefDescriptor, + uint32_t &rank, LLVM::LLVMType &type); + + /// Returns a string representation from the given `type`. + StringRef stringifyType(LLVM::LLVMType type) { + if (type.isFloatTy()) + return "Float"; + if (type.isIntegerTy()) + return "Int"; + + llvm_unreachable("unsupported type"); + } public: void runOnOperation() override; @@ -158,6 +179,9 @@ private: LLVM::LLVMType llvmMemRef1DFloat; LLVM::LLVMType llvmMemRef2DFloat; LLVM::LLVMType llvmMemRef3DFloat; + LLVM::LLVMType llvmMemRef1DInt; + LLVM::LLVMType llvmMemRef2DInt; + LLVM::LLVMType llvmMemRef3DInt; // TODO: Use an associative array to support multiple vulkan launch calls. std::pair spirvAttributes; @@ -231,13 +255,15 @@ void VulkanLaunchFuncToVulkanCallsPass::createBindMemRefCalls( auto ptrToMemRefDescriptor = en.value(); uint32_t rank = 0; - if (failed(deduceMemRefRank(ptrToMemRefDescriptor, rank))) { + LLVM::LLVMType type; + if (failed(deduceMemRefRankAndType(ptrToMemRefDescriptor, rank, type))) { cInterfaceVulkanLaunchCallOp.emitError() << "invalid memref descriptor " << ptrToMemRefDescriptor.getType(); return signalPassFailure(); } - auto symbolName = llvm::formatv("bindMemRef{0}DFloat", rank).str(); + auto symbolName = + llvm::formatv("bindMemRef{0}D{1}", rank, stringifyType(type)).str(); // Create call to `bindMemRef`. builder.create( loc, ArrayRef{getVoidType()}, @@ -248,9 +274,8 @@ void VulkanLaunchFuncToVulkanCallsPass::createBindMemRefCalls( } } -LogicalResult -VulkanLaunchFuncToVulkanCallsPass::deduceMemRefRank(Value ptrToMemRefDescriptor, - uint32_t &rank) { +LogicalResult VulkanLaunchFuncToVulkanCallsPass::deduceMemRefRankAndType( + Value ptrToMemRefDescriptor, uint32_t &rank, LLVM::LLVMType &type) { auto llvmPtrDescriptorTy = ptrToMemRefDescriptor.getType().dyn_cast(); if (!llvmPtrDescriptorTy) @@ -267,11 +292,12 @@ VulkanLaunchFuncToVulkanCallsPass::deduceMemRefRank(Value ptrToMemRefDescriptor, // }; if (!llvmDescriptorTy || !llvmDescriptorTy.isStructTy()) return failure(); + + type = llvmDescriptorTy.getStructElementType(0).getPointerElementTy(); if (llvmDescriptorTy.getStructNumElements() == 3) { rank = 0; return success(); } - rank = llvmDescriptorTy.getStructElementType(3).getArrayNumElements(); return success(); } @@ -312,35 +338,23 @@ void VulkanLaunchFuncToVulkanCallsPass::declareVulkanFunctions(Location loc) { /*isVarArg=*/false)); } - if (!module.lookupSymbol(kBindMemRef1DFloat)) { - builder.create( - loc, kBindMemRef1DFloat, - LLVM::LLVMType::getFunctionTy(getVoidType(), - {getPointerType(), getInt32Type(), - getInt32Type(), - getMemRef1DFloat().getPointerTo()}, - /*isVarArg=*/false)); +#define CREATE_VULKAN_BIND_FUNC(MemRefType) \ + if (!module.lookupSymbol(kBind##MemRefType)) { \ + builder.create( \ + loc, kBind##MemRefType, \ + LLVM::LLVMType::getFunctionTy(getVoidType(), \ + {getPointerType(), getInt32Type(), \ + getInt32Type(), \ + get##MemRefType().getPointerTo()}, \ + /*isVarArg=*/false)); \ } - if (!module.lookupSymbol(kBindMemRef2DFloat)) { - builder.create( - loc, kBindMemRef2DFloat, - LLVM::LLVMType::getFunctionTy(getVoidType(), - {getPointerType(), getInt32Type(), - getInt32Type(), - getMemRef2DFloat().getPointerTo()}, - /*isVarArg=*/false)); - } - - if (!module.lookupSymbol(kBindMemRef3DFloat)) { - builder.create( - loc, kBindMemRef3DFloat, - LLVM::LLVMType::getFunctionTy(getVoidType(), - {getPointerType(), getInt32Type(), - getInt32Type(), - getMemRef3DFloat().getPointerTo()}, - /*isVarArg=*/false)); - } + CREATE_VULKAN_BIND_FUNC(MemRef1DFloat); + CREATE_VULKAN_BIND_FUNC(MemRef2DFloat); + CREATE_VULKAN_BIND_FUNC(MemRef3DFloat); + CREATE_VULKAN_BIND_FUNC(MemRef1DInt); + CREATE_VULKAN_BIND_FUNC(MemRef2DInt); + CREATE_VULKAN_BIND_FUNC(MemRef3DInt); if (!module.lookupSymbol(kInitVulkan)) { builder.create( diff --git a/mlir/test/mlir-vulkan-runner/addi.mlir b/mlir/test/mlir-vulkan-runner/addi.mlir new file mode 100644 index 000000000000..c690120718b2 --- /dev/null +++ b/mlir/test/mlir-vulkan-runner/addi.mlir @@ -0,0 +1,52 @@ +// RUN: mlir-vulkan-runner %s --shared-libs=%vulkan_wrapper_library_dir/libvulkan-runtime-wrappers%shlibext,%linalg_test_lib_dir/libmlir_runner_utils%shlibext --entry-point-result=void | FileCheck %s + +// CHECK-COUNT-64: [3, 3, 3, 3, 3, 3, 3, 3] +module attributes { + gpu.container_module, + spv.target_env = #spv.target_env< + #spv.vce, + {max_compute_workgroup_invocations = 128 : i32, + max_compute_workgroup_size = dense<[128, 128, 64]> : vector<3xi32>}> +} { + gpu.module @kernels { + gpu.func @kernel_addi(%arg0 : memref<8xi32>, %arg1 : memref<8x8xi32>, %arg2 : memref<8x8x8xi32>) + kernel attributes { spv.entry_point_abi = {local_size = dense<[1, 1, 1]>: vector<3xi32>}} { + %x = "gpu.block_id"() {dimension = "x"} : () -> index + %y = "gpu.block_id"() {dimension = "y"} : () -> index + %z = "gpu.block_id"() {dimension = "z"} : () -> index + %0 = load %arg0[%x] : memref<8xi32> + %1 = load %arg1[%y, %x] : memref<8x8xi32> + %2 = addi %0, %1 : i32 + store %2, %arg2[%z, %y, %x] : memref<8x8x8xi32> + gpu.return + } + } + + func @main() { + %arg0 = alloc() : memref<8xi32> + %arg1 = alloc() : memref<8x8xi32> + %arg2 = alloc() : memref<8x8x8xi32> + %value0 = constant 0 : i32 + %value1 = constant 1 : i32 + %value2 = constant 2 : i32 + %arg3 = memref_cast %arg0 : memref<8xi32> to memref + %arg4 = memref_cast %arg1 : memref<8x8xi32> to memref + %arg5 = memref_cast %arg2 : memref<8x8x8xi32> to memref + call @fillResource1DInt(%arg3, %value1) : (memref, i32) -> () + call @fillResource2DInt(%arg4, %value2) : (memref, i32) -> () + call @fillResource3DInt(%arg5, %value0) : (memref, i32) -> () + + %cst1 = constant 1 : index + %cst8 = constant 8 : index + "gpu.launch_func"(%cst8, %cst8, %cst8, %cst1, %cst1, %cst1, %arg0, %arg1, %arg2) { kernel = @kernels::@kernel_addi } + : (index, index, index, index, index, index, memref<8xi32>, memref<8x8xi32>, memref<8x8x8xi32>) -> () + %arg6 = memref_cast %arg5 : memref to memref<*xi32> + call @print_memref_i32(%arg6) : (memref<*xi32>) -> () + return + } + func @fillResource1DInt(%0 : memref, %1 : i32) + func @fillResource2DInt(%0 : memref, %1 : i32) + func @fillResource3DInt(%0 : memref, %1 : i32) + func @print_memref_i32(%ptr : memref<*xi32>) +} + diff --git a/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp b/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp index 4c428ef0349a..b1848de00690 100644 --- a/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp +++ b/mlir/tools/mlir-vulkan-runner/vulkan-runtime-wrappers.cpp @@ -135,6 +135,41 @@ void bindMemRef3DFloat(void *vkRuntimeManager, DescriptorSetIndex setIndex, ->setResourceData(setIndex, bindIndex, memBuffer); } +/// Binds the given 1D int memref to the given descriptor set and descriptor +/// index. +void bindMemRef1DInt(void *vkRuntimeManager, DescriptorSetIndex setIndex, + BindingIndex bindIndex, + MemRefDescriptor *ptr) { + VulkanHostMemoryBuffer memBuffer{ + ptr->allocated, static_cast(ptr->sizes[0] * sizeof(int32_t))}; + reinterpret_cast(vkRuntimeManager) + ->setResourceData(setIndex, bindIndex, memBuffer); +} + +/// Binds the given 2D int memref to the given descriptor set and descriptor +/// index. +void bindMemRef2DInt(void *vkRuntimeManager, DescriptorSetIndex setIndex, + BindingIndex bindIndex, + MemRefDescriptor *ptr) { + VulkanHostMemoryBuffer memBuffer{ + ptr->allocated, + static_cast(ptr->sizes[0] * ptr->sizes[1] * sizeof(int32_t))}; + reinterpret_cast(vkRuntimeManager) + ->setResourceData(setIndex, bindIndex, memBuffer); +} + +/// Binds the given 3D int memref to the given descriptor set and descriptor +/// index. +void bindMemRef3DInt(void *vkRuntimeManager, DescriptorSetIndex setIndex, + BindingIndex bindIndex, + MemRefDescriptor *ptr) { + VulkanHostMemoryBuffer memBuffer{ + ptr->allocated, static_cast(ptr->sizes[0] * ptr->sizes[1] * + ptr->sizes[2] * sizeof(int32_t))}; + reinterpret_cast(vkRuntimeManager) + ->setResourceData(setIndex, bindIndex, memBuffer); +} + /// Fills the given 1D float memref with the given float value. void _mlir_ciface_fillResource1DFloat(MemRefDescriptor *ptr, // NOLINT float value) { @@ -153,4 +188,23 @@ void _mlir_ciface_fillResource3DFloat(MemRefDescriptor *ptr, // NOLINT std::fill_n(ptr->allocated, ptr->sizes[0] * ptr->sizes[1] * ptr->sizes[2], value); } + +/// Fills the given 1D int memref with the given int value. +void _mlir_ciface_fillResource1DInt(MemRefDescriptor *ptr, // NOLINT + int32_t value) { + std::fill_n(ptr->allocated, ptr->sizes[0], value); +} + +/// Fills the given 2D int memref with the given int value. +void _mlir_ciface_fillResource2DInt(MemRefDescriptor *ptr, // NOLINT + int32_t value) { + std::fill_n(ptr->allocated, ptr->sizes[0] * ptr->sizes[1], value); +} + +/// Fills the given 3D int memref with the given int value. +void _mlir_ciface_fillResource3DInt(MemRefDescriptor *ptr, // NOLINT + int32_t value) { + std::fill_n(ptr->allocated, ptr->sizes[0] * ptr->sizes[1] * ptr->sizes[2], + value); +} } -- GitLab From 4b33c935db15a9880e93e79a10066745aca2d22d Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 22 Apr 2020 18:57:08 +0200 Subject: [PATCH 110/910] [Hexagon] Silence warning llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp:296:11: warning: enumeration value 'ScalableVectorTyID' not handled in switch [-Wswitch] switch (Ty->getTypeID()) { ^ --- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 6f74c6b8a8c1..97aee3a10207 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -307,7 +307,8 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, const ArrayType *ATy = cast(Ty); return getSmallestAddressableSize(ATy->getElementType(), GV, TM); } - case Type::FixedVectorTyID: { + case Type::FixedVectorTyID: + case Type::ScalableVectorTyID: { const VectorType *PTy = cast(Ty); return getSmallestAddressableSize(PTy->getElementType(), GV, TM); } -- GitLab From 6bec6a97552d939e4fb13165bd4a5440d908c6c0 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 22 Apr 2020 19:02:01 +0200 Subject: [PATCH 111/910] Update go bindings for 2dea3f129878e929e5d1f00b91a622eb1ec8be4e --- llvm/bindings/go/llvm/ir.go | 31 ++++++++++++++++--------------- llvm/bindings/go/llvm/string.go | 6 ++++-- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/llvm/bindings/go/llvm/ir.go b/llvm/bindings/go/llvm/ir.go index c1daf829608c..4c350ac66f67 100644 --- a/llvm/bindings/go/llvm/ir.go +++ b/llvm/bindings/go/llvm/ir.go @@ -224,21 +224,22 @@ const ( //------------------------------------------------------------------------- const ( - VoidTypeKind TypeKind = C.LLVMVoidTypeKind - FloatTypeKind TypeKind = C.LLVMFloatTypeKind - DoubleTypeKind TypeKind = C.LLVMDoubleTypeKind - X86_FP80TypeKind TypeKind = C.LLVMX86_FP80TypeKind - FP128TypeKind TypeKind = C.LLVMFP128TypeKind - PPC_FP128TypeKind TypeKind = C.LLVMPPC_FP128TypeKind - LabelTypeKind TypeKind = C.LLVMLabelTypeKind - IntegerTypeKind TypeKind = C.LLVMIntegerTypeKind - FunctionTypeKind TypeKind = C.LLVMFunctionTypeKind - StructTypeKind TypeKind = C.LLVMStructTypeKind - ArrayTypeKind TypeKind = C.LLVMArrayTypeKind - PointerTypeKind TypeKind = C.LLVMPointerTypeKind - VectorTypeKind TypeKind = C.LLVMVectorTypeKind - MetadataTypeKind TypeKind = C.LLVMMetadataTypeKind - TokenTypeKind TypeKind = C.LLVMTokenTypeKind + VoidTypeKind TypeKind = C.LLVMVoidTypeKind + FloatTypeKind TypeKind = C.LLVMFloatTypeKind + DoubleTypeKind TypeKind = C.LLVMDoubleTypeKind + X86_FP80TypeKind TypeKind = C.LLVMX86_FP80TypeKind + FP128TypeKind TypeKind = C.LLVMFP128TypeKind + PPC_FP128TypeKind TypeKind = C.LLVMPPC_FP128TypeKind + LabelTypeKind TypeKind = C.LLVMLabelTypeKind + IntegerTypeKind TypeKind = C.LLVMIntegerTypeKind + FunctionTypeKind TypeKind = C.LLVMFunctionTypeKind + StructTypeKind TypeKind = C.LLVMStructTypeKind + ArrayTypeKind TypeKind = C.LLVMArrayTypeKind + PointerTypeKind TypeKind = C.LLVMPointerTypeKind + MetadataTypeKind TypeKind = C.LLVMMetadataTypeKind + TokenTypeKind TypeKind = C.LLVMTokenTypeKind + FixedVectorTypeKind TypeKind = C.LLVMFixedVectorTypeKind + ScalableVectorTypeKind TypeKind = C.LLVMScalableVectorTypeKind ) //------------------------------------------------------------------------- diff --git a/llvm/bindings/go/llvm/string.go b/llvm/bindings/go/llvm/string.go index bd48d4bc170a..5bd894ea6cac 100644 --- a/llvm/bindings/go/llvm/string.go +++ b/llvm/bindings/go/llvm/string.go @@ -40,10 +40,12 @@ func (t TypeKind) String() string { return "ArrayTypeKind" case PointerTypeKind: return "PointerTypeKind" - case VectorTypeKind: - return "VectorTypeKind" case MetadataTypeKind: return "MetadataTypeKind" + case FixedVectorTypeKind: + return "FixedVectorTypeKind" + case ScalableVectorTypeKind: + return "ScalableVectorTypeKind" } panic("unreachable") } -- GitLab From 02141a17aea0603b89baee14febea6a3b89474d1 Mon Sep 17 00:00:00 2001 From: Victor Huang Date: Wed, 22 Apr 2020 10:55:34 -0500 Subject: [PATCH 112/910] [PowerPC][Future] Remove redundant r2 save and restore for indirect call Currently an indirect call produces the following sequence on PCRelative mode: extern void function( ); extern void (*ptrfunc) ( ); void g() { ptrfunc=function; } void f() { (*ptrfunc) ( ); } Producing paddi 3, 0, .LC0@PCREL, 1 ld 3, 0(3) std 2, 24(1) ld 12, 0(3) mtctr 12 bctrl ld 2, 24(1) Though the caller does not use or preserve r2, it is still saved and restored across a function call. This patch is added to remove these redundant save and restores for indirect calls. Differential Revision: https://reviews.llvm.org/D77749 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 52 ++++++++++--------- .../PowerPC/pcrel-call-linkage-with-calls.ll | 25 --------- .../CodeGen/PowerPC/pcrel-got-indirect.ll | 2 - .../CodeGen/PowerPC/pcrel-indirect-call.ll | 37 +++++++++++++ 4 files changed, 65 insertions(+), 51 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/pcrel-indirect-call.ll diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4f065dfd4f7c..effb1651d045 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -5152,6 +5152,12 @@ static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG, return true; } +// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls. +static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) { + return Subtarget.isAIXABI() || + (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()); +} + static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags, const Function &Caller, const SDValue &Callee, @@ -5168,20 +5174,12 @@ static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags, // pointer is modeled by using a pseudo instruction for the call opcode that // represents the 2 instruction sequence of an indirect branch and link, // immediately followed by a load of the TOC pointer from the the stack save - // slot into gpr2. - if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI()) - return PPCISD::BCTRL_LOAD_TOC; - - // An indirect call that does not need a TOC restore. - return PPCISD::BCTRL; + // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC + // as it is not saved or used. + return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC + : PPCISD::BCTRL; } - // FIXME: At this moment indirect calls are treated ahead of the - // PC Relative condition because binaries can still contain a possible - // mix of functions that use a TOC and functions that do not use a TOC. - // Once the PC Relative feature is complete this condition should be moved - // up ahead of the indirect calls and should return a PPCISD::BCTRL for - // that case. if (Subtarget.isUsingPCRelativeCalls()) { assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."); return PPCISD::CALL_NOTOC; @@ -5439,7 +5437,9 @@ buildCallOperands(SmallVectorImpl &Ops, // pointer from the linkage area. The operand for the TOC restore is an add // of the TOC save offset to the stack pointer. This must be the second // operand: after the chain input but before any other variadic arguments. - if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) { + // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not + // saved or used. + if (isTOCSaveRestoreRequired(Subtarget)) { const MCRegister StackPtrReg = Subtarget.getStackPointerRegister(); SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); @@ -6509,17 +6509,21 @@ SDValue PPCTargetLowering::LowerCall_64SVR4( // See prepareDescriptorIndirectCall and buildCallOperands for more // information about calls through function pointers in the 64-bit SVR4 ABI. if (CFlags.IsIndirect) { - assert(!CFlags.IsTailCall && "Indirect tails calls not supported"); - // Load r2 into a virtual register and store it to the TOC save area. - setUsesTOCBasePtr(DAG); - SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); - // TOC save area offset. - unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); - SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl); - SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); - Chain = DAG.getStore( - Val.getValue(1), dl, Val, AddPtr, - MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset)); + // For 64-bit ELFv2 ABI with PCRel, do not save the TOC of the + // caller in the TOC save area. + if (isTOCSaveRestoreRequired(Subtarget)) { + assert(!CFlags.IsTailCall && "Indirect tails calls not supported"); + // Load r2 into a virtual register and store it to the TOC save area. + setUsesTOCBasePtr(DAG); + SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); + // TOC save area offset. + unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); + SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl); + SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); + Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, + MachinePointerInfo::getStack( + DAG.getMachineFunction(), TOCSaveOffset)); + } // In the ELFv2 ABI, R12 must contain the address of an indirect callee. // This does not mean the MTCTR instruction must use R12; it's easier // to model this as an extra parameter, so do that. diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll index ed96e732b08b..010704f546d0 100644 --- a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll +++ b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll @@ -328,14 +328,10 @@ entry: define dso_local signext i32 @IndirectCall1(i32 signext %a, i32 signext %b) local_unnamed_addr { ; CHECK-ALL-LABEL: IndirectCall1: -; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep13@ha -; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep13@l -; CHECK-S: .localentry IndirectCall1, .Lfunc_lep13-.Lfunc_gep13 ; CHECK-S: # %bb.0: # %entry ; CHECK-S-NEXT: mflr r0 ; CHECK-S-NEXT: std r0, 16(r1) ; CHECK-S-NEXT: stdu r1, -32(r1) -; CHECK-S-NEXT: std r2, 24(r1) ; CHECK-S-NEXT: .cfi_def_cfa_offset 32 ; CHECK-S-NEXT: .cfi_offset lr, 16 ; CHECK-S-NEXT: pld r12, indirectCall@PCREL(0), 1 @@ -343,7 +339,6 @@ define dso_local signext i32 @IndirectCall1(i32 signext %a, i32 signext %b) loca ; CHECK-S-NEXT: extsw r3, r3 ; CHECK-S-NEXT: mtctr r12 ; CHECK-S-NEXT: bctrl -; CHECK-S-NEXT: ld 2, 24(r1) ; CHECK-S-NEXT: plwz r4, globalVar@PCREL(0), 1 ; CHECK-S-NEXT: mullw r3, r4, r3 ; CHECK-S-NEXT: extsw r3, r3 @@ -362,14 +357,10 @@ entry: define dso_local signext i32 @IndirectCall2(i32 signext %a, i32 signext %b) local_unnamed_addr { ; CHECK-ALL-LABEL: IndirectCall2: -; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep14@ha -; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep14@l -; CHECK-S: .localentry IndirectCall2, .Lfunc_lep14-.Lfunc_gep14 ; CHECK-S: # %bb.0: # %entry ; CHECK-S-NEXT: mflr r0 ; CHECK-S-NEXT: std r0, 16(r1) ; CHECK-S-NEXT: stdu r1, -32(r1) -; CHECK-S-NEXT: std r2, 24(r1) ; CHECK-S-NEXT: .cfi_def_cfa_offset 32 ; CHECK-S-NEXT: .cfi_offset lr, 16 ; CHECK-S-NEXT: pld r12, indirectCall@PCREL(0), 1 @@ -377,7 +368,6 @@ define dso_local signext i32 @IndirectCall2(i32 signext %a, i32 signext %b) loca ; CHECK-S-NEXT: extsw r3, r3 ; CHECK-S-NEXT: mtctr r12 ; CHECK-S-NEXT: bctrl -; CHECK-S-NEXT: ld 2, 24(r1) ; CHECK-S-NEXT: pld r4, externGlobalVar@got@pcrel(0), 1 ; CHECK-S-NEXT: lwz r4, 0(r4) ; CHECK-S-NEXT: mullw r3, r4, r3 @@ -397,14 +387,10 @@ entry: define dso_local signext i32 @IndirectCall3(i32 signext %a, i32 signext %b, i32 (i32)* nocapture %call_param) local_unnamed_addr { ; CHECK-ALL-LABEL: IndirectCall3: -; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep15@ha -; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep15@l -; CHECK-S: .localentry IndirectCall3, .Lfunc_lep15-.Lfunc_gep15 ; CHECK-S: # %bb.0: # %entry ; CHECK-S-NEXT: mflr r0 ; CHECK-S-NEXT: std r0, 16(r1) ; CHECK-S-NEXT: stdu r1, -32(r1) -; CHECK-S-NEXT: std r2, 24(r1) ; CHECK-S-NEXT: .cfi_def_cfa_offset 32 ; CHECK-S-NEXT: .cfi_offset lr, 16 ; CHECK-S-NEXT: add r3, r4, r3 @@ -412,7 +398,6 @@ define dso_local signext i32 @IndirectCall3(i32 signext %a, i32 signext %b, i32 ; CHECK-S-NEXT: mtctr r5 ; CHECK-S-NEXT: mr r12, r5 ; CHECK-S-NEXT: bctrl -; CHECK-S-NEXT: ld 2, 24(r1) ; CHECK-S-NEXT: plwz r4, globalVar@PCREL(0), 1 ; CHECK-S-NEXT: mullw r3, r4, r3 ; CHECK-S-NEXT: extsw r3, r3 @@ -430,9 +415,6 @@ entry: define dso_local signext i32 @IndirectCallNoGlobal(i32 signext %a, i32 signext %b, i32 (i32)* nocapture %call_param) local_unnamed_addr { ; CHECK-ALL-LABEL: IndirectCallNoGlobal: -; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep16@ha -; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep16@l -; CHECK-S: .localentry IndirectCallNoGlobal, .Lfunc_lep16-.Lfunc_gep16 ; CHECK-S: # %bb.0: # %entry ; CHECK-S-NEXT: mflr r0 ; CHECK-S-NEXT: .cfi_def_cfa_offset 48 @@ -443,10 +425,8 @@ define dso_local signext i32 @IndirectCallNoGlobal(i32 signext %a, i32 signext % ; CHECK-S-NEXT: stdu r1, -48(r1) ; CHECK-S-NEXT: mtctr r5 ; CHECK-S-NEXT: mr r12, r5 -; CHECK-S-NEXT: std r2, 24(r1) ; CHECK-S-NEXT: mr r30, r4 ; CHECK-S-NEXT: bctrl -; CHECK-S-NEXT: ld 2, 24(r1) ; CHECK-S-NEXT: add r3, r3, r30 ; CHECK-S-NEXT: extsw r3, r3 ; CHECK-S-NEXT: addi r1, r1, 48 @@ -462,20 +442,15 @@ entry: define dso_local signext i32 @IndirectCallOnly(i32 signext %a, i32 (i32)* nocapture %call_param) local_unnamed_addr { ; CHECK-ALL-LABEL: IndirectCallOnly: -; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep17@ha -; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep17@l -; CHECK-S: .localentry IndirectCallOnly, .Lfunc_lep17-.Lfunc_gep17 ; CHECK-S: # %bb.0: # %entry ; CHECK-S-NEXT: mflr r0 ; CHECK-S-NEXT: std r0, 16(r1) ; CHECK-S-NEXT: stdu r1, -32(r1) -; CHECK-S-NEXT: std r2, 24(r1) ; CHECK-S-NEXT: .cfi_def_cfa_offset 32 ; CHECK-S-NEXT: .cfi_offset lr, 16 ; CHECK-S-NEXT: mtctr r4 ; CHECK-S-NEXT: mr r12, r4 ; CHECK-S-NEXT: bctrl -; CHECK-S-NEXT: ld 2, 24(r1) ; CHECK-S-NEXT: addi r1, r1, 32 ; CHECK-S-NEXT: ld r0, 16(r1) ; CHECK-S-NEXT: mtlr r0 diff --git a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll index e9aeccd4ac16..a3404a8951a1 100644 --- a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll +++ b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll @@ -219,14 +219,12 @@ define dso_local void @ReadFuncPtr() local_unnamed_addr { ; CHECK-NEXT: mflr r0 ; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: stdu r1, -32(r1) -; CHECK-NEXT: std r2, 24(r1) ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: pld r3, ptrfunc@got@pcrel(0), 1 ; CHECK-NEXT: ld r12, 0(r3) ; CHECK-NEXT: mtctr r12 ; CHECK-NEXT: bctrl -; CHECK-NEXT: ld 2, 24(r1) ; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: mtlr r0 diff --git a/llvm/test/CodeGen/PowerPC/pcrel-indirect-call.ll b/llvm/test/CodeGen/PowerPC/pcrel-indirect-call.ll new file mode 100644 index 000000000000..7806d691c530 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pcrel-indirect-call.ll @@ -0,0 +1,37 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s + +; The test checks the behavior of PC Relative indirect calls. When using +; PC Relative, TOC save and restore are no longer required. Function pointer +; is passed as a parameter in this test. + +; Function Attrs: noinline +define dso_local void @IndirectCallExternFuncPtr(void ()* nocapture %ptrfunc) { +; CHECK-LABEL: IndirectCallExternFuncPtr: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -32(r1) + +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: .cfi_offset lr, 16 +; CHECK-NEXT: mtctr r3 +; CHECK-NEXT: mr r12, r3 +; CHECK-NEXT: bctrl + +; CHECK-NEXT: addi r1, r1, 32 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: mtlr r0 +; CHECK-NEXT: blr +entry: + tail call void %ptrfunc() + ret void +} + +define dso_local void @FuncPtrPassAsParam() { +entry: + tail call void @IndirectCallExternFuncPtr(void ()* nonnull @Function) + ret void +} + +declare void @Function() -- GitLab From eecba950671629e656e90b5a948a58d3a86a375d Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 22 Apr 2020 16:33:11 +0100 Subject: [PATCH 113/910] [ARM] Replace arm vendor with none. NFC --- clang/test/CodeGen/arm-cde-gpr.c | 2 +- clang/test/CodeGen/arm-cde-reinterpret.c | 2 +- clang/test/CodeGen/arm-cde-vec.c | 2 +- clang/test/CodeGen/arm-cde-vfp.c | 2 +- clang/test/CodeGen/arm-mve-intrinsics/absneg.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/admin.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/compare.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/dup.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/idup.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/load-store.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/predicates.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | 4 ++-- .../test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | 2 +- .../test/CodeGen/arm-mve-intrinsics/scatter-gather.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/ternary.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vadc.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vandq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vclz.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | 4 ++-- .../arm-mve-intrinsics/vector-shift-imm-dyadic.c | 4 ++-- .../CodeGen/arm-mve-intrinsics/vector-shift-imm.c | 4 ++-- .../CodeGen/arm-mve-intrinsics/vector-shift-var.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/veorq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vld24.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vldr.c | 2 +- clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vminq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vornq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vrev.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | 4 ++-- clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | 4 ++-- clang/test/Headers/arm-cde-header.c | 12 ++++++------ clang/test/Sema/arm-cde-immediates.c | 2 +- clang/test/Sema/arm-mve-immediates.c | 2 +- clang/test/Sema/overload-arm-mve.c | 4 ++-- llvm/test/CodeGen/ARM/cmov_fp16.ll | 2 +- llvm/test/CodeGen/Thumb2/csel.ll | 2 +- llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir | 2 +- llvm/test/CodeGen/Thumb2/lsll0.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-abs.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-be.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-bitarith.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-bitcasts.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-bitreverse.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-bswap.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ctlz.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ctpop.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-cttz.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-div-expand.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-extractelt.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-float16regloops.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-float32regloops.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-fma-loops.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-fmas.ll | 6 +++--- llvm/test/CodeGen/Thumb2/mve-fmath.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-frint.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll | 2 +- .../test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll | 2 +- .../test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll | 2 +- .../CodeGen/Thumb2/mve-gather-optimisation-deep.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll | 4 ++-- .../Thumb2/mve-gather-scatter-optimisation.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-halving.ll | 2 +- .../CodeGen/Thumb2/mve-intrinsics/longshift-const.ll | 2 +- .../Thumb2/mve-intrinsics/longshift-demand.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-ldst-regimm.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-loadstore.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-load.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-masked-store.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-minmax.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-neg.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-phireg.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-and.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-ext.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-not.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-or.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-spill.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-xor.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll | 2 +- .../CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll | 2 +- .../CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll | 2 +- .../test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-sext.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-shifts.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-shuffle.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-shuffleext.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-shufflemov.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-simple-arith.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-stack.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-stacksplot.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vaddqr.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vaddv.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vcmp.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vcmpf.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vcmpr.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vcmpz.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vcvt.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vdup.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vector-spill.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vfma.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vld2-post.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vld2.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vld3.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vld4-post.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vld4.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vldst4.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmaxv.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmla.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmovimm.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vmovn.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmull.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmulqr.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll | 4 ++-- llvm/test/CodeGen/Thumb2/mve-vpsel.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir | 2 +- .../test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir | 2 +- .../CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir | 2 +- .../Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir | 2 +- .../CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-blocks.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vst2-post.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vst2.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vst3.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vst4-post.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vst4.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-vsubqr.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll | 2 +- llvm/test/CodeGen/Thumb2/postinc-distribute.mir | 2 +- llvm/test/CodeGen/Thumb2/vqabs.ll | 2 +- llvm/test/CodeGen/Thumb2/vqneg.ll | 2 +- llvm/test/MC/ARM/vscclrm-asm.s | 2 +- .../CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll | 2 +- llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll | 2 +- .../Transforms/HardwareLoops/ARM/calls-codegen.ll | 4 ++-- llvm/test/Transforms/HardwareLoops/ARM/calls.ll | 12 ++++++------ llvm/test/Transforms/HardwareLoops/ARM/counter.ll | 2 +- llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll | 2 +- .../Transforms/HardwareLoops/ARM/fp-emulation.ll | 4 ++-- llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll | 6 +++--- llvm/test/Transforms/HardwareLoops/ARM/structure.ll | 6 +++--- llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll | 2 +- .../Transforms/LoopVectorize/ARM/mve-shiftcost.ll | 2 +- llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll | 2 +- llvm/unittests/Target/ARM/MachineInstrTest.cpp | 10 +++++----- 232 files changed, 343 insertions(+), 343 deletions(-) diff --git a/clang/test/CodeGen/arm-cde-gpr.c b/clang/test/CodeGen/arm-cde-gpr.c index 1e6893d7d2f8..ceb33e8ab974 100644 --- a/clang/test/CodeGen/arm-cde-gpr.c +++ b/clang/test/CodeGen/arm-cde-gpr.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \ +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \ // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ // RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s diff --git a/clang/test/CodeGen/arm-cde-reinterpret.c b/clang/test/CodeGen/arm-cde-reinterpret.c index c169a88bc4e3..bebfc5dee845 100644 --- a/clang/test/CodeGen/arm-cde-reinterpret.c +++ b/clang/test/CodeGen/arm-cde-reinterpret.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \ +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ // RUN: -target-feature +cdecp0 -target-feature +mve.fp \ // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ // RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefixes=CHECK,CHECK-LE diff --git a/clang/test/CodeGen/arm-cde-vec.c b/clang/test/CodeGen/arm-cde-vec.c index ea186a46be00..be4b8bef75ec 100644 --- a/clang/test/CodeGen/arm-cde-vec.c +++ b/clang/test/CodeGen/arm-cde-vec.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \ +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \ // RUN: -target-feature +mve.fp \ // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ diff --git a/clang/test/CodeGen/arm-cde-vfp.c b/clang/test/CodeGen/arm-cde-vfp.c index fffcb716359d..41fef605860d 100644 --- a/clang/test/CodeGen/arm-cde-vfp.c +++ b/clang/test/CodeGen/arm-cde-vfp.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \ +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi \ // RUN: -target-feature +cdecp0 -target-feature +cdecp1 \ // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ // RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s diff --git a/clang/test/CodeGen/arm-mve-intrinsics/absneg.c b/clang/test/CodeGen/arm-mve-intrinsics/absneg.c index 4f888093d8b8..b63135bc450a 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/absneg.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/absneg.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/admin.c b/clang/test/CodeGen/arm-mve-intrinsics/admin.c index 710f99b3b83f..137231557011 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/admin.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/admin.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c b/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c index de1bdee41eb3..c41e0265c8fd 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/compare.c b/clang/test/CodeGen/arm-mve-intrinsics/compare.c index c58003768cab..6db60bfb0971 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/compare.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/compare.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp b/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp index 47df53839d15..f0455eb31e84 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp +++ b/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/dup.c b/clang/test/CodeGen/arm-mve-intrinsics/dup.c index 3bcec9d2549e..46d0606e3307 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/dup.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/dup.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c b/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c index 6eaf0f8a71f5..9810e71e1308 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/idup.c b/clang/test/CodeGen/arm-mve-intrinsics/idup.c index 9fae90d6c712..ac3ab3e632bd 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/idup.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/idup.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/load-store.c b/clang/test/CodeGen/arm-mve-intrinsics/load-store.c index e7a92bc26128..5a676ebb5924 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/load-store.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/load-store.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/predicates.c b/clang/test/CodeGen/arm-mve-intrinsics/predicates.c index 5761849d094b..fc36fdb80d43 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/predicates.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/predicates.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c b/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c index 790312e89e88..36f70be1cb0d 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE // RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=BE // RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=BE diff --git a/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c b/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c index a6425e7d93f3..ef544291c562 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c b/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c index 564965acc04d..a7d1a1c96663 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c index 77eb8d41fe58..1f54d6618b4c 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c b/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c index e1362760bb8f..3f5adb7d8db9 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c b/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c index d972fb78b503..eda67d48a5dc 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vadc.c b/clang/test/CodeGen/arm-mve-intrinsics/vadc.c index f5e6c7d33983..5e428efd1b29 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vadc.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vadc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c index 1904c6e835c7..15f96d8524f8 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c b/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c index 6bacc2775881..48655dcaf364 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py - // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s - // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vandq.c b/clang/test/CodeGen/arm-mve-intrinsics/vandq.c index 9c88b67085fe..c56c7e7d3b48 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vandq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vandq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c b/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c index 22ff5d5e739c..941fb5e35865 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c b/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c index e1fd5993cc74..0c2c1dd82533 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c index f23751a3526a..bdfba6d394a5 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vclz.c b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c index b39ac36eb340..490bafcd74c3 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vclz.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c b/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c index f470a3bd1888..ed2ef56d7bc1 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c b/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c index 08d6a606efce..142e909a1f0e 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c b/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c index d03ac31a8024..1cbcbe823ef8 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c b/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c index e5dbd4c8f68b..8563245a9f32 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c index c5591392e373..7cbaf4001c7e 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c index e86f78b659c0..4eec660a2f05 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c index 680c2e48fb8c..f83808d77aca 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/veorq.c b/clang/test/CodeGen/arm-mve-intrinsics/veorq.c index 9025da9feefd..68f40dce9eb6 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/veorq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/veorq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c index cd61bc782c7d..b3c34dee1503 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c index 62335bf9af2e..1f4efd634e9b 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c b/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c index 529936998b37..0b01a5f0b05b 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vld24.c b/clang/test/CodeGen/arm-mve-intrinsics/vld24.c index a0f37fe65d3d..98abd277c995 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vld24.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vld24.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vldr.c b/clang/test/CodeGen/arm-mve-intrinsics/vldr.c index e394ed13ad74..d6deb754cc67 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vldr.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vldr.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c index 27b5812a9605..03ab37474ba0 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c index b7e85ff2a584..20c22056d52a 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c index 539508127ca7..5caf8d6421fe 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c index 93fb24d339b3..d0ddc7a99e9f 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c index 45c38e814102..b23dc1a27be8 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c index 955e8feab52a..b13d851aec79 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c index f951afe61b87..7ebcf45d8833 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminq.c index 105c5d6a3614..d4186858b121 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vminq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c index 0d484bf98f7a..efa999891870 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c b/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c index 60339ff8db56..913b56346913 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c b/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c index 8bc1e2531e98..52941229ac21 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c b/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c index e66e67c49976..746678f61d57 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c b/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c index ed414b52ade8..48935303809f 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=LE %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=LE %s // RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=BE %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=LE %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=LE %s // RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck --check-prefix=BE %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c index 816a0df0111f..4f018da3f97b 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c index 2634d63019f9..bf3dce8a34a9 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c index a56d2e3d8c6c..515960ba5fb4 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c index 3619dabb81e1..026e1681f685 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vornq.c b/clang/test/CodeGen/arm-mve-intrinsics/vornq.c index 8505bfed6047..eabb8aea9f90 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vornq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vornq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c b/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c index 3ddc8629dd4e..ccdd1e0768f5 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c index 8ed34dd752f3..1b0d20ea8737 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c b/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c index cd59e6ccdfb7..20b6745800ff 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c index bab911f385e7..b8a24e8d8f82 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c index c7aa5a3c17b5..b38d20b6c206 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c index 0a03e2e963df..095ec60f64a3 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c b/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c index 24c3fd550bf4..a24306340f34 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c index 919074e7fddb..b90a00102646 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c b/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c index 28ced90ef0f7..a50c1ba33b10 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrev.c b/clang/test/CodeGen/arm-mve-intrinsics/vrev.c index 73675cc005b2..cec1e7077c44 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vrev.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrev.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c index eb28d239741d..17fb58b8dabf 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c b/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c index 4f65f002b017..f9f76f54d691 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c b/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c index 8ad5f48b5856..6df91cfbbc7e 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c b/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c index 1a53a90f26fa..2cbaccd0ed3a 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c b/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c index 7231ae966306..313c42e2c875 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s #include diff --git a/clang/test/Headers/arm-cde-header.c b/clang/test/Headers/arm-cde-header.c index b2f721a6ff9c..694483e66960 100644 --- a/clang/test/Headers/arm-cde-header.c +++ b/clang/test/Headers/arm-cde-header.c @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -std=c89 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -std=c17 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -xc++ -std=c++98 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -xc++ -std=c++20 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -xc++ -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -std=c89 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -std=c17 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -std=c++98 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -std=c++20 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s // Check that the headers don't conflict with each other #include diff --git a/clang/test/Sema/arm-cde-immediates.c b/clang/test/Sema/arm-cde-immediates.c index bdf582e98146..7e5725e44660 100644 --- a/clang/test/Sema/arm-cde-immediates.c +++ b/clang/test/Sema/arm-cde-immediates.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -verify -fsyntax-only %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -verify -fsyntax-only %s #include #include diff --git a/clang/test/Sema/arm-mve-immediates.c b/clang/test/Sema/arm-mve-immediates.c index 41cff7e3852f..508513ee6156 100644 --- a/clang/test/Sema/arm-mve-immediates.c +++ b/clang/test/Sema/arm-mve-immediates.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -verify -fsyntax-only %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -verify -fsyntax-only %s #include diff --git a/clang/test/Sema/overload-arm-mve.c b/clang/test/Sema/overload-arm-mve.c index 0ce2dac0aded..4b1f66d803a9 100644 --- a/clang/test/Sema/overload-arm-mve.c +++ b/clang/test/Sema/overload-arm-mve.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -flax-vector-conversions=all -Werror -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -flax-vector-conversions=all -verify -fsyntax-only -DERROR_CHECK %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -flax-vector-conversions=all -Werror -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -flax-vector-conversions=all -verify -fsyntax-only -DERROR_CHECK %s typedef signed short int16_t; typedef signed int int32_t; diff --git a/llvm/test/CodeGen/ARM/cmov_fp16.ll b/llvm/test/CodeGen/ARM/cmov_fp16.ll index 925fed582811..2c368d1a41bc 100644 --- a/llvm/test/CodeGen/ARM/cmov_fp16.ll +++ b/llvm/test/CodeGen/ARM/cmov_fp16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-THUMB,CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-THUMB,CHECK ; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-ARM,CHECK define i32 @test_ne(i32 %x, i32 %y, i32 %a, i32 %b) { diff --git a/llvm/test/CodeGen/Thumb2/csel.ll b/llvm/test/CodeGen/Thumb2/csel.ll index 4ff2fe512e02..f2cf3e839a80 100644 --- a/llvm/test/CodeGen/Thumb2/csel.ll +++ b/llvm/test/CodeGen/Thumb2/csel.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -verify-machineinstrs -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -verify-machineinstrs -o - | FileCheck %s define i32 @csinc_const_65(i32 %a) { ; CHECK-LABEL: csinc_const_65: diff --git a/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir b/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir index 1e87efa0847e..687c64d9ebff 100644 --- a/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir +++ b/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s +# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s --- name: func0 tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Thumb2/lsll0.ll b/llvm/test/CodeGen/Thumb2/lsll0.ll index 58949cbbbf81..a56451f36121 100644 --- a/llvm/test/CodeGen/Thumb2/lsll0.ll +++ b/llvm/test/CodeGen/Thumb2/lsll0.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define void @_Z4loopPxS_iS_i(i64* %d) { ; CHECK-LABEL: _Z4loopPxS_iS_i: diff --git a/llvm/test/CodeGen/Thumb2/mve-abs.ll b/llvm/test/CodeGen/Thumb2/mve-abs.ll index 90c9206dd933..29878063a8ca 100644 --- a/llvm/test/CodeGen/Thumb2/mve-abs.ll +++ b/llvm/test/CodeGen/Thumb2/mve-abs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) { ; CHECK-LABEL: abs_v16i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-be.ll b/llvm/test/CodeGen/Thumb2/mve-be.ll index 3db11f1e4293..9dee871bf6a8 100644 --- a/llvm/test/CodeGen/Thumb2/mve-be.ll +++ b/llvm/test/CodeGen/Thumb2/mve-be.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @load_load_add_store(<4 x i32> *%src1, <4 x i32> *%src2) { diff --git a/llvm/test/CodeGen/Thumb2/mve-bitarith.ll b/llvm/test/CodeGen/Thumb2/mve-bitarith.ll index 309818169229..e159e2df40e1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-bitarith.ll +++ b/llvm/test/CodeGen/Thumb2/mve-bitarith.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @and_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: and_int8_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-bitcasts.ll b/llvm/test/CodeGen/Thumb2/mve-bitcasts.ll index bbb505abc8d1..0c57cd4c02df 100644 --- a/llvm/test/CodeGen/Thumb2/mve-bitcasts.ll +++ b/llvm/test/CodeGen/Thumb2/mve-bitcasts.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @bitcast_i64_i64(<2 x i64> %src) { ; CHECK-LABEL: bitcast_i64_i64: diff --git a/llvm/test/CodeGen/Thumb2/mve-bitreverse.ll b/llvm/test/CodeGen/Thumb2/mve-bitreverse.ll index 99f9506c3a9d..6ba505978ff6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-bitreverse.ll +++ b/llvm/test/CodeGen/Thumb2/mve-bitreverse.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @brv_2i64_t(<2 x i64> %src){ ; CHECK-LABEL: brv_2i64_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-bswap.ll b/llvm/test/CodeGen/Thumb2/mve-bswap.ll index c7d3f844fd7e..f12869834023 100644 --- a/llvm/test/CodeGen/Thumb2/mve-bswap.ll +++ b/llvm/test/CodeGen/Thumb2/mve-bswap.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @bswap_4i32_t(<4 x i32> %src){ ; CHECK-LABEL: bswap_4i32_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll index 5e866a1b0b8c..9750b888804c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ ; CHECK-LABEL: ctlz_2i64_0_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll index d6d215cc7ed7..6a795c415d62 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){ ; CHECK-LABEL: ctpop_2i64_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-cttz.ll b/llvm/test/CodeGen/Thumb2/mve-cttz.ll index 3a77883babf2..e17107cf66cf 100644 --- a/llvm/test/CodeGen/Thumb2/mve-cttz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-cttz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){ ; CHECK-LABEL: cttz_2i64_0_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-div-expand.ll b/llvm/test/CodeGen/Thumb2/mve-div-expand.ll index 41e5a27d2657..d72495b215bc 100644 --- a/llvm/test/CodeGen/Thumb2/mve-div-expand.ll +++ b/llvm/test/CodeGen/Thumb2/mve-div-expand.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x i32> @udiv_i32(<4 x i32> %in1, <4 x i32> %in2) { ; CHECK-LABEL: udiv_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-extractelt.ll b/llvm/test/CodeGen/Thumb2/mve-extractelt.ll index e0f1e9468c5e..f9359c83884d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-extractelt.ll +++ b/llvm/test/CodeGen/Thumb2/mve-extractelt.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc i32 @u8_explicit_extend(<16 x i8> %a) { ; CHECK-LABEL: u8_explicit_extend: diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll index 38083b7edcc2..17b0077c0e86 100644 --- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @test_fadd(half* noalias nocapture readonly %A, half *%BB, half* noalias nocapture %C, i32 %n) { ; CHECK-LABEL: test_fadd: diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll index e86d3606f27f..da082719f45e 100644 --- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @test_fadd(float* noalias nocapture readonly %A, float %B, float* noalias nocapture %C, i32 %n) { ; CHECK-LABEL: test_fadd: diff --git a/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll index 9438a0d39033..6d530b91754a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false %s -o - | FileCheck %s define arm_aapcs_vfpcc void @fmas1(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z, float %a, i32 %n) { ; CHECK-LABEL: fmas1: diff --git a/llvm/test/CodeGen/Thumb2/mve-fmas.ll b/llvm/test/CodeGen/Thumb2/mve-fmas.ll index 789e06a01146..ecfdbc71457a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-fmas.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fmas.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi, -mattr=+mve.fp -fp-contract=fast -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE-VMLA +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE define arm_aapcs_vfpcc <8 x half> @vfma16_v1(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { ; CHECK-MVE-FP-LABEL: vfma16_v1: diff --git a/llvm/test/CodeGen/Thumb2/mve-fmath.ll b/llvm/test/CodeGen/Thumb2/mve-fmath.ll index 6fece1ac0c77..d93f31c9e217 100644 --- a/llvm/test/CodeGen/Thumb2/mve-fmath.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fmath.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) { ; CHECK-LABEL: sqrt_float32_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll index 9b295d3117a8..50d8752176a1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) { ; CHECK-MVE-LABEL: fneg_float16_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-frint.ll b/llvm/test/CodeGen/Thumb2/mve-frint.ll index 6d936a375dd1..410c4f18bd00 100644 --- a/llvm/test/CodeGen/Thumb2/mve-frint.ll +++ b/llvm/test/CodeGen/Thumb2/mve-frint.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) { ; CHECK-MVE-LABEL: fceil_float32_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll index 948f030a84da..30ce13b85073 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @scaled_v8i16_i16(i16* %base, <8 x i16>* %offptr) { ; CHECK-LABEL: scaled_v8i16_i16: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll index ee2667614556..7e96a213e5c3 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ind16-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @zext_unscaled_i8_i16(i8* %base, <8 x i16>* %offptr) { ; CHECK-LABEL: zext_unscaled_i8_i16: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll index 0cbfb8961eb9..c674ffbf51bd 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ind32-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @zext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) { ; CHECK-LABEL: zext_scaled_i16_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll index ac365ab23f7e..1b6acbd8338f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ind32-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr) { ; CHECK-LABEL: zext_unscaled_i8_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll index deb3be28ddb6..60bffc5a31db 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ind8-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @unscaled_v16i8_i8(i8* %base, <16 x i8>* %offptr) { ; CHECK-LABEL: unscaled_v16i8_i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll b/llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll index a86a89972cf7..22f6cd6bc3d0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt --mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s +; RUN: opt --mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s define arm_aapcs_vfpcc void @push_out_add_sub_block(i32* noalias nocapture readonly %data, i32* noalias nocapture %dst, i32 %n.vec) { ; CHECK-LABEL: @push_out_add_sub_block( diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll index c44668c7f5b3..78e3ced1ceb6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll index c9bb6660c856..7f4bdbb0f93f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=-mve -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=-mve -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32_gather(i8* %base, <4 x i32>* %offptr) { ; NOGATSCAT-LABEL: unscaled_i32_i32_gather: diff --git a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll index e70696761101..e3c8761722fa 100644 --- a/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll +++ b/llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s !0 = !{i32 1, !"wchar_size", i32 4} !1 = !{i32 1, !"min_enum_size", i32 4} diff --git a/llvm/test/CodeGen/Thumb2/mve-halving.ll b/llvm/test/CodeGen/Thumb2/mve-halving.ll index 08877d4fc250..69e714f8eb5a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-halving.ll +++ b/llvm/test/CodeGen/Thumb2/mve-halving.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vhadds_v16i8(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: vhadds_v16i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll index 2a6a4a36c920..1fbf4e6734ff 100644 --- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s declare {i32, i32} @llvm.arm.mve.asrl(i32, i32, i32) declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32) diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll index df945cd7d504..03da11269501 100644 --- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s declare {i32, i32} @llvm.arm.mve.asrl(i32, i32, i32) declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32) diff --git a/llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll b/llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll index 54befb26d16c..b81ee3541407 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll b/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll index 3d0634c0ca85..486ee9692489 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll b/llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll index bf732c628eed..edcadf30426c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y) { diff --git a/llvm/test/CodeGen/Thumb2/mve-ldst-regimm.ll b/llvm/test/CodeGen/Thumb2/mve-ldst-regimm.ll index e57708d1ea3e..43564017f35a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-ldst-regimm.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ldst-regimm.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s %struct.s_int8_t = type { [16 x i8], [16 x i8] } %struct.s_int16_t = type { [8 x i16], [8 x i16] } diff --git a/llvm/test/CodeGen/Thumb2/mve-loadstore.ll b/llvm/test/CodeGen/Thumb2/mve-loadstore.ll index 20fce95d6d96..3e0c345932d7 100644 --- a/llvm/test/CodeGen/Thumb2/mve-loadstore.ll +++ b/llvm/test/CodeGen/Thumb2/mve-loadstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @load_4xi32_a4(<4 x i32>* %vp) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll index 5e2e85017e23..96181701f3b2 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-offset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll index f80372209e3f..2b84d1b09ee1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-postinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll index 424e16d22dc9..bb671ed57e8d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst-preinc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define i8* @ldrwu32_4(i8* %x, i8* %y, <4 x i32> *%m) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll index 3814b0b2766c..d1829f705407 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @foo_v4i32_v4i32(<4 x i32> *%dest, <4 x i32> *%mask, <4 x i32> *%src) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-load.ll b/llvm/test/CodeGen/Thumb2/mve-masked-load.ll index ca51edb92a2a..2c941d42a4b8 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-load.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-load.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @masked_v4i32_align4_zero(<4 x i32> *%dest, <4 x i32> %a) { diff --git a/llvm/test/CodeGen/Thumb2/mve-masked-store.ll b/llvm/test/CodeGen/Thumb2/mve-masked-store.ll index 215fe12334e9..018c87a87b99 100644 --- a/llvm/test/CodeGen/Thumb2/mve-masked-store.ll +++ b/llvm/test/CodeGen/Thumb2/mve-masked-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc void @masked_v4i32(<4 x i32> *%dest, <4 x i32> %a) { diff --git a/llvm/test/CodeGen/Thumb2/mve-minmax.ll b/llvm/test/CodeGen/Thumb2/mve-minmax.ll index 14b1f466bf66..c533216127bb 100644 --- a/llvm/test/CodeGen/Thumb2/mve-minmax.ll +++ b/llvm/test/CodeGen/Thumb2/mve-minmax.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) { ; CHECK-LABEL: smin_v16i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll b/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll index 6ff6d718ed77..a24637870b31 100644 --- a/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll +++ b/llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s declare void @external_function() diff --git a/llvm/test/CodeGen/Thumb2/mve-neg.ll b/llvm/test/CodeGen/Thumb2/mve-neg.ll index 602ce3d5f9be..2d8d0f4ac519 100644 --- a/llvm/test/CodeGen/Thumb2/mve-neg.ll +++ b/llvm/test/CodeGen/Thumb2/mve-neg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @neg_v16i8(<16 x i8> %s1) { ; CHECK-LABEL: neg_v16i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-phireg.ll b/llvm/test/CodeGen/Thumb2/mve-phireg.ll index bc2ef68a8eb5..e7d6a7323bc1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-phireg.ll +++ b/llvm/test/CodeGen/Thumb2/mve-phireg.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads. diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll index 5be3f722a0e4..fe9e7d197ca2 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s ; Check some loop postinc's for properly distributed post-incs diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir index d69037a952eb..5fc89549ec92 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s --- | define i32* @MVE_VLDRWU32(i32* %x) { unreachable } diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll index 789b6604b484..a9c9bb9cba68 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s ; Check some LSR loop postinc diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll index 4567f60b4baf..9848a56b9f33 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-and.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-and.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll index 61a78eb722e0..955f48184c3c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @bitcast_to_v4i1(i4 %b, <4 x i32> %a) { diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll b/llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll index 959b162add39..86634db14b34 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @build_true_v4i1(<4 x i32> %a, <4 x i32> %b) { diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll index ae2ee6a94e10..4d0568a675be 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) { diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll index 99bd003c8fc5..b88576a22cc2 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) { ; CHECK-LABEL: sext_v4i1_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll index 21af261170e6..0dbbe3f663c3 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define arm_aapcs_vfpcc <4 x i32> @load_v4i1(<4 x i1> *%src, <4 x i32> %a) { diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll index a16fce870cb9..e4f9b1e1bd51 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-not.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-not.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll index 26ff81c6f394..4e9e074083f5 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-or.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-or.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll index 1b00b708db3e..d325138a0b82 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define <4 x i32> @shuffle1_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: shuffle1_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll index ccbe5033514f..6ae083dd297c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE declare arm_aapcs_vfpcc <4 x i32> @ext_i32(<4 x i32> %c) diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll b/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll index df211f1efebc..0ba0e8a6c409 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @thres_i32(i32* %data, i16 zeroext %N, i32 %T) { ; CHECK-LABEL: thres_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll index 07821a29e547..f92a4bd958f9 100644 --- a/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-xor.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: cmpeqz_v4i1: diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll index d01ef0095a60..d89c24014646 100644 --- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @ssatmul_s_q31(i32* nocapture readonly %pSrcA, i32* nocapture readonly %pSrcB, i32* noalias nocapture %pDst, i32 %N) { ; CHECK-LABEL: ssatmul_s_q31: diff --git a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll index 3610c2a65653..8457a3ab7a16 100644 --- a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll +++ b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @sadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: sadd_int8_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll index 82f357d28a69..2d9e2047e08c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRH.16 Qd, [base, offs, uxtw #1] define arm_aapcs_vfpcc void @scaled_v8i16_i16(i16* %base, <8 x i16>* %offptr, <8 x i16> %input) { diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll index 156bf9826952..0993a61912a5 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRB.u16 Qd, [base, offs] define arm_aapcs_vfpcc void @ext_unscaled_i8_i16(i8* %base, <8 x i16>* %offptr, <8 x i16> %input) { diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll index 8dc00bcbd76d..25a9cea5f5be 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-scaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s ; VLDRH.u32 Qd, [base, offs, #uxtw #1] define arm_aapcs_vfpcc void @ext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr, <4 x i32> %input) { diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll index 48c7b547e1b4..a4ec18a2e2b1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o 2>/dev/null - | FileCheck %s ; VLDRB.u32 Qd, [base, offs] define arm_aapcs_vfpcc void @ext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr, <4 x i32> %input) { diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll index 878765c0a862..d84066cdc5bd 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -o - | FileCheck %s ; VLDRB.8 define arm_aapcs_vfpcc void @unscaled_v16i8_i8(i8* %base, <16 x i8>* %offptr, <16 x i8> %input) { diff --git a/llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll b/llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll index a317bcd0745a..11aaba9b5526 100644 --- a/llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll +++ b/llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -enable-arm-maskedgatscat %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-sext.ll b/llvm/test/CodeGen/Thumb2/mve-sext.ll index f351e6dc01f5..26f524d7aed8 100644 --- a/llvm/test/CodeGen/Thumb2/mve-sext.ll +++ b/llvm/test/CodeGen/Thumb2/mve-sext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @sext_v4i32_v4i32_v4i1(<4 x i32> %m) { ; CHECK-LABEL: sext_v4i32_v4i32_v4i1: diff --git a/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll b/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll index 2cc875fe0bc1..33b3d0ed0b90 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s --verify-machineinstrs -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s --verify-machineinstrs -o - | FileCheck %s define dso_local arm_aapcs_vfpcc void @sink_shl_i32(i32* nocapture readonly %in, i32* noalias nocapture %out, i32 %shift, i32 %N) { ; CHECK-LABEL: sink_shl_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-shifts.ll b/llvm/test/CodeGen/Thumb2/mve-shifts.ll index 69e91a54c9ab..8243e0df2059 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shifts.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shifts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @shl_qq_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: shl_qq_int8_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll index 2f6541b7be11..ce9abf80b9de 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x i32> @shuffle1_i32(<4 x i32> %src) { ; CHECK-LABEL: shuffle1_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll index bd4cf69e7a8e..c1a306a92718 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) { ; CHECK-LABEL: sext_0246: diff --git a/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll b/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll index 164d42f15152..4bde0e4d14de 100644 --- a/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll +++ b/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; i16 diff --git a/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll index 92b6ae5337f9..dc04c5e75837 100644 --- a/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll +++ b/llvm/test/CodeGen/Thumb2/mve-simple-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <16 x i8> @add_int8_t(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: add_int8_t: diff --git a/llvm/test/CodeGen/Thumb2/mve-stack.ll b/llvm/test/CodeGen/Thumb2/mve-stack.ll index 41cc1162ee92..ea272e19b23f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-stack.ll +++ b/llvm/test/CodeGen/Thumb2/mve-stack.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @vstrw32() { ; CHECK-LABEL: vstrw32: diff --git a/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir b/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir index f101783d7f0a..a2c3bdc894eb 100644 --- a/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir +++ b/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s +# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s --- name: func0 tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Thumb2/mve-vaddqr.ll b/llvm/test/CodeGen/Thumb2/mve-vaddqr.ll index dd97bd52dfd1..da07cd676946 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vaddqr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vaddqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vaddqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vaddqr_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vaddv.ll b/llvm/test/CodeGen/Thumb2/mve-vaddv.ll index 1244fc7716be..e3f236bedc04 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vaddv.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vaddv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>) declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>) diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll index 87f0e66fe30e..a40beb4b0eba 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmp.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, <4 x i32> %srcb, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eq_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll index 9e793caac3dd..7c60eeadbfb0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll index c9325c282893..1c6c0ff9c2d9 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll index b6c28c3e1016..20837421e971 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll index c832c241e67c..06361d952120 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eq_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eq_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll index 6d08abc72302..e9b717494234 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcmpz.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vcmp_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vcmp_eqz_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll index a2d8b582ad47..0cfe5cc80c1f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP define arm_aapcs_vfpcc <4 x float> @foo_float_int32(<4 x i32> %src) { ; CHECK-MVE-LABEL: foo_float_int32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vdup.ll b/llvm/test/CodeGen/Thumb2/mve-vdup.ll index 829319ba7c07..f855b121590c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vdup.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vdup.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vdup_i32(i32 %src) { ; CHECK-LABEL: vdup_i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll index 7ea29277cc46..2f483b391c14 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x) { ; CHECK-LABEL: add_v4i32_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll index 9d02a1c817cf..d8d40e5b5186 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP define arm_aapcs_vfpcc float @fadd_v2f32(<2 x float> %x, float %y) { ; CHECK-LABEL: fadd_v2f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll index 0b6f18d28d40..a2ab4af918bf 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP ; FIXME minnum nonan X, +Inf -> X ? define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) { diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll index 1f98979d480f..e4ac03e9b3c8 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP define arm_aapcs_vfpcc float @fmul_v2f32(<2 x float> %x, float %y) { ; CHECK-LABEL: fmul_v2f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll index dea70df68773..0716f585baf6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: add_v4i32_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vector-spill.ll b/llvm/test/CodeGen/Thumb2/mve-vector-spill.ll index f7a0a04af79e..3a33825a0b0d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vector-spill.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vector-spill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s declare void @external_function() diff --git a/llvm/test/CodeGen/Thumb2/mve-vfma.ll b/llvm/test/CodeGen/Thumb2/mve-vfma.ll index 8ed8b81201e7..1b071c709ce7 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vfma.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vfma.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) { ; CHECK-LABEL: fma_v4f32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll b/llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll index d70dff938ec1..08e76ec185f1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vhaddsub.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @add_ashr_v16i8(<16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: add_ashr_v16i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll index 11bf7b5900c7..0a5f21058687 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld2-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vld2.ll b/llvm/test/CodeGen/Thumb2/mve-vld2.ll index 24e69c12a34d..7c8c0bae6bec 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld2.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vld3.ll b/llvm/test/CodeGen/Thumb2/mve-vld3.ll index 3b49d77ba6ff..02e90a78dae9 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld3.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld3.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll index 7a9d20c5c952..e8f336871326 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld4-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vld4.ll b/llvm/test/CodeGen/Thumb2/mve-vld4.ll index 9a1320986940..233082a14a9e 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vld4.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vld4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll index a1b47029e4aa..5c4d982d66ad 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vldst4.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vldst4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 { ; CHECK-LABEL: vldst4: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll b/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll index 4c705b75fd78..f96c2f422a3f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>) declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>) diff --git a/llvm/test/CodeGen/Thumb2/mve-vmla.ll b/llvm/test/CodeGen/Thumb2/mve-vmla.ll index 5b0bdebfa88a..9c5b405dbc3f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmla.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmla.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vmlau32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind { ; CHECK-LABEL: vmlau32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll index aad885b9b18a..4dd2470d1b3f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKLE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKBE define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() { diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovn.ll b/llvm/test/CodeGen/Thumb2/mve-vmovn.ll index 0a48179a21d5..a70491a05c18 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmovn.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmovn.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECKBE define arm_aapcs_vfpcc <8 x i16> @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2) { diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll b/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll index 566e79780a44..b9856298defc 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc void @vmovn32_trunc1(<4 x i32> %src1, <4 x i32> %src2, <8 x i16> *%dest) { ; CHECK-LABEL: vmovn32_trunc1: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll b/llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll index 927a91233d5b..ecb119888c86 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc void @test32(i32* noalias nocapture readonly %x, i32* noalias nocapture readonly %y, i32* nocapture %z, i32 %n) { ; CHECK-LABEL: test32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmull.ll b/llvm/test/CodeGen/Thumb2/mve-vmull.ll index 6d0b6622b8a4..9d71df8dcca0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmull.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmull.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK define arm_aapcs_vfpcc <2 x i64> @sext_02(<4 x i32> %src1, <4 x i32> %src2) { ; CHECK-LABEL: sext_02: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmulqr.ll b/llvm/test/CodeGen/Thumb2/mve-vmulqr.ll index 5c5c39c15545..b2eaf455ebe1 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmulqr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmulqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vmulqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vmulqr_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll index 8f6ea13befc0..a54d005444f7 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <8 x i16> @mov_int16_511() { ; CHECK-LABEL: mov_int16_511: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpsel.ll b/llvm/test/CodeGen/Thumb2/mve-vpsel.ll index 5da0aa518c08..fa897c5fe9d9 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpsel.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vpsel.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vpsel_i8(<16 x i8> %mask, <16 x i8> %src1, <16 x i8> %src2) { ; CHECK-LABEL: vpsel_i8: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir index 1aa281841fd3..f1495509df6d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_1_pred(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir index a8b0edefe390..506b8d2687c6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_2_preds(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir index 4ac7f1152d60..391b74ee0dac 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_ctrl_flow(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir index 8747eda183d0..ee26f56b605c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_non_consecutive_ins(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir index a6414fbffda8..594df5969595 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir index 7401d771d1b6..a60c217404be 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_3_blocks_kill_vpr(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir index 6f73c3535d41..858bb6a15627 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_1_ins(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir index b87edd64e921..eb47791e4f80 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_2_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir index 9fb071b0e18a..8504ad0814c2 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_4_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir index 93bf2e6f4510..94cad7477345 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_else(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir index ffc072bccbb6..91643e5ccfab 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-blocks.ll b/llvm/test/CodeGen/Thumb2/mve-vpt-blocks.ll index 94374308e7d6..1c26ddd27f56 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-blocks.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-blocks.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir index 496774335438..7e14d074604b 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" ; Functions are intentionally left blank - see the MIR sequences below. diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir index e49a870bced2..fe6f4a3f595d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir @@ -3,7 +3,7 @@ --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main-none-none-eabi" define arm_aapcs_vfpcc <4 x float> @vpt_preuse(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) #0 { entry: diff --git a/llvm/test/CodeGen/Thumb2/mve-vqmovn.ll b/llvm/test/CodeGen/Thumb2/mve-vqmovn.ll index f8d70fcd4494..0478ae199330 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vqmovn.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vqmovn.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vqmovni32_smaxmin(<4 x i32> %s0) { ; CHECK-LABEL: vqmovni32_smaxmin: diff --git a/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll index e6bbf4d7e775..ebaeae88af71 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst2-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst2.ll b/llvm/test/CodeGen/Thumb2/mve-vst2.ll index 5eea2531ee0d..9b68f7d4c074 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst2.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst3.ll b/llvm/test/CodeGen/Thumb2/mve-vst3.ll index 614db5ff829c..167076e5c114 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst3.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst3.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll index d8f674ac9c19..4c939fc09e59 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst4-post.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vst4.ll b/llvm/test/CodeGen/Thumb2/mve-vst4.ll index 9aeda4087208..bc5415566424 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vst4.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vst4.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; i32 diff --git a/llvm/test/CodeGen/Thumb2/mve-vsubqr.ll b/llvm/test/CodeGen/Thumb2/mve-vsubqr.ll index ec2f7c11b522..946b2ed4978a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vsubqr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vsubqr.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x i32> @vsubqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: vsubqr_v4i32: diff --git a/llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll b/llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll index 4c3b4d3e1b37..033a07125047 100644 --- a/llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll +++ b/llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc -mtriple=thumbebv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE define void @foo_int8_int32(<4 x i8>* %dest, <4 x i32>* readonly %src, i32 %n) { diff --git a/llvm/test/CodeGen/Thumb2/postinc-distribute.mir b/llvm/test/CodeGen/Thumb2/postinc-distribute.mir index 77b401fba1f2..af39cced110a 100644 --- a/llvm/test/CodeGen/Thumb2/postinc-distribute.mir +++ b/llvm/test/CodeGen/Thumb2/postinc-distribute.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-prera-ldst-opt %s -o - | FileCheck %s --- | define i32* @t2LDRi12(i32* %x, i32 %y) { unreachable } diff --git a/llvm/test/CodeGen/Thumb2/vqabs.ll b/llvm/test/CodeGen/Thumb2/vqabs.ll index 7a366ea5ed05..3525413f9c4f 100644 --- a/llvm/test/CodeGen/Thumb2/vqabs.ll +++ b/llvm/test/CodeGen/Thumb2/vqabs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vqabs_test16(<16 x i8> %A) nounwind { ; CHECK-LABEL: vqabs_test16: diff --git a/llvm/test/CodeGen/Thumb2/vqneg.ll b/llvm/test/CodeGen/Thumb2/vqneg.ll index b92a7ab270fa..6c702f3839b3 100644 --- a/llvm/test/CodeGen/Thumb2/vqneg.ll +++ b/llvm/test/CodeGen/Thumb2/vqneg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @vqneg_test16(<16 x i8> %A) nounwind { ; CHECK-LABEL: vqneg_test16: diff --git a/llvm/test/MC/ARM/vscclrm-asm.s b/llvm/test/MC/ARM/vscclrm-asm.s index 3f679c7fdd09..0989b38b07c0 100644 --- a/llvm/test/MC/ARM/vscclrm-asm.s +++ b/llvm/test/MC/ARM/vscclrm-asm.s @@ -4,7 +4,7 @@ // RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \ // RUN: | FileCheck --check-prefix=CHECK %s // RUN: FileCheck --check-prefix=ERROR < %t %s -// RUN: not llvm-mc -triple=thumbv8.1m.main-arm-none-eabi -mattr=-8msecext < %s 2>%t +// RUN: not llvm-mc -triple=thumbv8.1m.main-none-none-eabi -mattr=-8msecext < %s 2>%t // RUN: FileCheck --check-prefix=NOSEC < %t %s // CHECK: vscclrm {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a] diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll index cb0737ffaeb6..54988e69c29f 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s define void @sink_add_mul(i32* %s1, i32 %x, i32* %d, i32 %n) { ; CHECK-LABEL: @sink_add_mul( diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll index c0da3eb56660..470a9f201790 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s ; Sink the shufflevector/insertelement pair, followed by the trunc. The sunk instruction end up dead. define signext i8 @dead(i16* noalias nocapture readonly %s1, i16 zeroext %x, i8* noalias nocapture %d, i32 %n) { diff --git a/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll b/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll index 2771235d576e..72b5bb0c7be2 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+lob,+mve.fp -disable-arm-loloops=true %s -o - | FileCheck %s --check-prefix=DISABLED -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+lob,+mve.fp %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+lob,+mve.fp -disable-arm-loloops=true %s -o - | FileCheck %s --check-prefix=DISABLED +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+lob,+mve.fp %s -o - | FileCheck %s ; DISABLED-NOT: dls lr, diff --git a/llvm/test/Transforms/HardwareLoops/ARM/calls.ll b/llvm/test/Transforms/HardwareLoops/ARM/calls.ll index 43c6d06a108a..feb6b6574a1b 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/calls.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/calls.ll @@ -1,9 +1,9 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAIN -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fp-armv8,+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP64 -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MAIN +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8,+fullfp16 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP64 +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED ; DISABLED-NOT: call i32 @llvm.loop.decrement diff --git a/llvm/test/Transforms/HardwareLoops/ARM/counter.ll b/llvm/test/Transforms/HardwareLoops/ARM/counter.ll index edb635464285..fd216d9f356a 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/counter.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/counter.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -o - | FileCheck %s @g = common local_unnamed_addr global i32* null, align 4 diff --git a/llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll b/llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll index c3e0d88d8df4..ed89a5ad475d 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll @@ -1,4 +1,4 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s @g = common local_unnamed_addr global i32* null, align 4 diff --git a/llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll b/llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll index 4bf76b6cdc84..66a97b2321e7 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll @@ -1,5 +1,5 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+fp-armv8 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+soft-float -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SOFT +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8 -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+soft-float -hardware-loops %s -S -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SOFT ; CHECK-LABEL: test_fptosi ; CHECK-SOFT-NOT: call void @llvm.set.loop.iterations diff --git a/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll b/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll index 8d5cdc1a3fe1..780098049b2f 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll @@ -1,6 +1,6 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | FileCheck %s -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-LLC +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | FileCheck %s +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops -disable-arm-loloops=true %s -S -o - | FileCheck %s --check-prefix=DISABLED +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-LLC ; DISABLED-NOT: llvm.{{.*}}.loop.iterations ; DISABLED-NOT: llvm.loop.decrement diff --git a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll index fbc09a175f8a..1a6688640039 100644 --- a/llvm/test/Transforms/HardwareLoops/ARM/structure.ll +++ b/llvm/test/Transforms/HardwareLoops/ARM/structure.ll @@ -1,10 +1,10 @@ -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops %s -S -o - | \ +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops %s -S -o - | \ ; RUN: FileCheck %s -; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -o - | \ +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -o - | \ ; RUN: FileCheck %s --check-prefix=CHECK-LLC ; RUN: opt -mtriple=thumbv8.1m.main -loop-unroll -unroll-remainder=false -S < %s | \ ; RUN: llc -mtriple=thumbv8.1m.main | FileCheck %s --check-prefix=CHECK-UNROLL -; RUN: opt -mtriple=thumbv8.1m.main-arm-none-eabi -hardware-loops \ +; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -hardware-loops \ ; RUN: -pass-remarks-analysis=hardware-loops %s -S -o - 2>&1 | \ ; RUN: FileCheck %s --check-prefix=CHECK-REMARKS diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll index e1a4c9ea6c53..807de5614b87 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-reduce.ll @@ -1,7 +1,7 @@ ; RUN: opt -loop-vectorize < %s -S -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: check4 ; CHECK: call i32 @llvm.experimental.vector.reduce.add.v4i32 diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll index 7195e61c280f..15c8483685b1 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-shiftcost.ll @@ -3,7 +3,7 @@ ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: test ; CHECK-COST: LV: Found an estimated cost of 0 for VF 1 For instruction: %and515 = shl i32 %l41, 3 diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll index 353e725580a4..49d13f7fc014 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-vldn.ll @@ -4,7 +4,7 @@ ; RUN: opt -loop-vectorize -mve-max-interleave-factor=4 < %s -S -o - | FileCheck %s --check-prefixes=CHECK,CHECK-2,CHECK-4 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m.main-arm-none-eabi" +target triple = "thumbv8.1m.main-none-none-eabi" ; CHECK-LABEL: vld2 ; CHECK-2: vector.body diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp index 6cf8493666bc..51c9d739f916 100644 --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -74,7 +74,7 @@ TEST(MachineInstructionDoubleWidthResult, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -231,7 +231,7 @@ TEST(MachineInstructionHorizontalReduction, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -331,7 +331,7 @@ TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -932,7 +932,7 @@ TEST(MachineInstrValidTailPredication, IsCorrect) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { @@ -986,7 +986,7 @@ TEST(MachineInstr, HasSideEffects) { LLVMInitializeARMTarget(); LLVMInitializeARMTargetMC(); - auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi")); + auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi")); std::string Error; const Target *T = TargetRegistry::lookupTarget(TT, Error); if (!T) { -- GitLab From 089fbe69193364fee14ed94a58c530d8417dc391 Mon Sep 17 00:00:00 2001 From: Mikhail Maltsev Date: Wed, 22 Apr 2020 18:25:22 +0100 Subject: [PATCH 114/910] [Docs] Fixed formatting in release notes, NFC --- clang/docs/ReleaseNotes.rst | 4 ++-- llvm/docs/ReleaseNotes.rst | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 1f4bc0f0d0da..88edf0092dc5 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -61,8 +61,8 @@ Non-comprehensive list of changes in this release v8.1-M MVE instruction set. ```` supports the complete API defined in the Arm C Language Extensions. -- For the ARM target, C-language intrinsics for the CDE instruction - set are now provided. +- For the ARM target, C-language intrinsics ```` for the CDE + instruction set are now provided. * clang adds support for a set of extended integer types (``_ExtInt(N)``) that permit non-power of 2 integers, exposing the LLVM integer types. Since a major diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 3afdce296fcd..e0ff25622704 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -79,7 +79,7 @@ During this release ... * Added support for assembly for the optional Custom Datapath Extension (CDE) for Arm M-profile targets. -* Implemented C-language intrinsics for the CDE instruction set. +* Implemented C-language intrinsics ```` for the CDE instruction set. Changes to the MIPS Target -------------------------- -- GitLab From fa6b68a404d94a80b53c43dbfa79d6464249ea43 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 15:52:19 +0100 Subject: [PATCH 115/910] BPFMCTargetDesc.h - remove unused raw_ostream forward declaration. NFC. --- llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h index 4d05aad0695d..a426a132cf47 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -28,7 +28,6 @@ class MCRegisterInfo; class MCSubtargetInfo; class MCTargetOptions; class Target; -class raw_ostream; MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, -- GitLab From 1b154ec0d03cda87e346ae431ef1f50f416f2da3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 15:53:06 +0100 Subject: [PATCH 116/910] [AVR] Remove unused forward declarations. NFC. --- llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h | 3 --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h index 62054c04d7d6..9e150f120dd4 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h @@ -22,9 +22,6 @@ namespace llvm { class MCAssembler; -class MCObjectWriter; -class Target; - struct MCFixupKindInfo; /// Utilities for manipulating generated AVR machine code. diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h index 470db01ff468..ef116793d326 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h @@ -27,10 +27,7 @@ class MCObjectTargetWriter; class MCRegisterInfo; class MCSubtargetInfo; class MCTargetOptions; -class StringRef; class Target; -class Triple; -class raw_pwrite_stream; MCInstrInfo *createAVRMCInstrInfo(); -- GitLab From f8a5e746c674c7a57b01855d262423b818b47a28 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 16:35:19 +0100 Subject: [PATCH 117/910] [Hexagon] Remove unused forward declarations. NFC. --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h | 1 - llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h | 1 - llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h | 3 --- 3 files changed, 5 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 7b5e7634ebf6..d60de4cfc2ee 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -25,7 +25,6 @@ namespace llvm { class MachineFunction; class HexagonInstrInfo; class HexagonRegisterInfo; -class HexagonTargetLowering; class HexagonDAGToDAGISel : public SelectionDAGISel { const HexagonSubtarget *HST; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h index 59b1326adf0c..e88f46a04dae 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h @@ -12,7 +12,6 @@ #include "llvm/MC/MCExpr.h" namespace llvm { -class MCInst; class HexagonMCExpr : public MCTargetExpr { public: static HexagonMCExpr *create(MCExpr const *Expr, MCContext &Ctx); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index a089abc3bd0c..5bf7c9a1a908 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -47,7 +47,6 @@ namespace llvm { -struct InstrItinerary; struct InstrStage; class FeatureBitset; class MCAsmBackend; @@ -61,8 +60,6 @@ class MCTargetOptions; class Target; class Triple; class StringRef; -class raw_ostream; -class raw_pwrite_stream; extern cl::opt HexagonDisableCompound; extern cl::opt HexagonDisableDuplex; -- GitLab From dc869d5aadcde9b750e7305896721da10482bb65 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 22 Apr 2020 16:36:02 +0100 Subject: [PATCH 118/910] [Lanai] Remove unused forward declarations. NFC. --- llvm/lib/Target/Lanai/Lanai.h | 3 --- llvm/lib/Target/Lanai/LanaiMCInstLower.h | 2 -- llvm/lib/Target/Lanai/LanaiTargetMachine.h | 1 - llvm/lib/Target/Lanai/LanaiTargetObjectFile.h | 1 - 4 files changed, 7 deletions(-) diff --git a/llvm/lib/Target/Lanai/Lanai.h b/llvm/lib/Target/Lanai/Lanai.h index 2f06ea91ab03..2bd266b1b96e 100644 --- a/llvm/lib/Target/Lanai/Lanai.h +++ b/llvm/lib/Target/Lanai/Lanai.h @@ -19,9 +19,6 @@ namespace llvm { class FunctionPass; class LanaiTargetMachine; -class MachineFunctionPass; -class TargetMachine; -class formatted_raw_ostream; // createLanaiISelDag - This pass converts a legalized DAG into a // Lanai-specific DAG, ready for instruction scheduling. diff --git a/llvm/lib/Target/Lanai/LanaiMCInstLower.h b/llvm/lib/Target/Lanai/LanaiMCInstLower.h index 00d3ebb05045..6323319fae43 100644 --- a/llvm/lib/Target/Lanai/LanaiMCInstLower.h +++ b/llvm/lib/Target/Lanai/LanaiMCInstLower.h @@ -18,9 +18,7 @@ class MCInst; class MCOperand; class MCSymbol; class MachineInstr; -class MachineModuleInfoMachO; class MachineOperand; -class Mangler; // LanaiMCInstLower - This class is used to lower an MachineInstr // into an MCInst. diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index d2ac40007e24..fb2bc0644fe8 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -22,7 +22,6 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class formatted_raw_ostream; class LanaiTargetMachine : public LLVMTargetMachine { LanaiSubtarget Subtarget; diff --git a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h index 938a1e675b6a..25c0eadb9782 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h +++ b/llvm/lib/Target/Lanai/LanaiTargetObjectFile.h @@ -12,7 +12,6 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" namespace llvm { -class LanaiTargetMachine; class LanaiTargetObjectFile : public TargetLoweringObjectFileELF { MCSection *SmallDataSection; MCSection *SmallBSSSection; -- GitLab From 3616e851f66e41b3c8b9f97d26e711069d56e752 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 21 Apr 2020 15:30:50 -0700 Subject: [PATCH 119/910] scudo: Change the macro used to check whether we're targeting the platform. Differential Revision: https://reviews.llvm.org/D78594 --- compiler-rt/lib/scudo/standalone/combined.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index 51e0c5d1966c..b44753a4373a 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -32,10 +32,9 @@ extern "C" inline void EmptyCallback() {} -#if SCUDO_ANDROID && __ANDROID_API__ == 10000 +#ifdef HAVE_ANDROID_UNSAFE_FRAME_POINTER_CHASE // This function is not part of the NDK so it does not appear in any public -// header files. We only declare/use it when targeting the platform (i.e. API -// level 10000). +// header files. We only declare/use it when targeting the platform. extern "C" size_t android_unsafe_frame_pointer_chase(scudo::uptr *buf, size_t num_entries); #endif @@ -232,7 +231,7 @@ public: } NOINLINE u32 collectStackTrace() { -#if SCUDO_ANDROID && __ANDROID_API__ == 10000 +#ifdef HAVE_ANDROID_UNSAFE_FRAME_POINTER_CHASE // Discard collectStackTrace() frame and allocator function frame. constexpr uptr DiscardFrames = 2; uptr Stack[MaxTraceSize + DiscardFrames]; -- GitLab From 3f1c2bf1712c7496a80a0f89036ab1625ff347a5 Mon Sep 17 00:00:00 2001 From: Sam McCall Date: Mon, 2 Mar 2020 22:45:25 +0100 Subject: [PATCH 120/910] [clangd] go-to-def on names in comments etc that are used nearby. Summary: This is intended as a companion to (and is inspired by) D72874 which attempts to resolve these cases using the index. The intent is we'd try this strategy after the AST-based approach but before the index-based (I think local usages would be more reliable than index matches). Reviewers: nridge Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D75479 --- clang-tools-extra/clangd/SourceCode.cpp | 90 ++++++++ clang-tools-extra/clangd/SourceCode.h | 29 +++ clang-tools-extra/clangd/XRefs.cpp | 202 +++++++++++------- clang-tools-extra/clangd/XRefs.h | 29 ++- .../clangd/unittests/SourceCodeTests.cpp | 96 +++++++++ .../clangd/unittests/XRefsTests.cpp | 114 +++++++++- 6 files changed, 467 insertions(+), 93 deletions(-) diff --git a/clang-tools-extra/clangd/SourceCode.cpp b/clang-tools-extra/clangd/SourceCode.cpp index 1943784bfd18..dd4c863cb96a 100644 --- a/clang-tools-extra/clangd/SourceCode.cpp +++ b/clang-tools-extra/clangd/SourceCode.cpp @@ -855,6 +855,96 @@ llvm::StringSet<> collectWords(llvm::StringRef Content) { return Result; } +static bool isLikelyIdentifier(llvm::StringRef Word, llvm::StringRef Before, + llvm::StringRef After) { + // `foo` is an identifier. + if (Before.endswith("`") && After.startswith("`")) + return true; + // In foo::bar, both foo and bar are identifiers. + if (Before.endswith("::") || After.startswith("::")) + return true; + // Doxygen tags like \c foo indicate identifiers. + // Don't search too far back. + // This duplicates clang's doxygen parser, revisit if it gets complicated. + Before = Before.take_back(100); // Don't search too far back. + auto Pos = Before.find_last_of("\\@"); + if (Pos != llvm::StringRef::npos) { + llvm::StringRef Tag = Before.substr(Pos + 1).rtrim(' '); + if (Tag == "p" || Tag == "c" || Tag == "class" || Tag == "tparam" || + Tag == "param" || Tag == "param[in]" || Tag == "param[out]" || + Tag == "param[in,out]" || Tag == "retval" || Tag == "throw" || + Tag == "throws" || Tag == "link") + return true; + } + + // Word contains underscore. + // This handles things like snake_case and MACRO_CASE. + if (Word.contains('_')) { + return true; + } + // Word contains capital letter other than at beginning. + // This handles things like lowerCamel and UpperCamel. + // The check for also containing a lowercase letter is to rule out + // initialisms like "HTTP". + bool HasLower = Word.find_if(clang::isLowercase) != StringRef::npos; + bool HasUpper = Word.substr(1).find_if(clang::isUppercase) != StringRef::npos; + if (HasLower && HasUpper) { + return true; + } + // FIXME: consider mid-sentence Capitalization? + return false; +} + +llvm::Optional SpelledWord::touching(SourceLocation SpelledLoc, + const syntax::TokenBuffer &TB, + const LangOptions &LangOpts) { + const auto &SM = TB.sourceManager(); + auto Touching = syntax::spelledTokensTouching(SpelledLoc, TB); + for (const auto &T : Touching) { + // If the token is an identifier or a keyword, don't use any heuristics. + if (tok::isAnyIdentifier(T.kind()) || tok::getKeywordSpelling(T.kind())) { + SpelledWord Result; + Result.Location = T.location(); + Result.Text = T.text(SM); + Result.LikelyIdentifier = tok::isAnyIdentifier(T.kind()); + Result.PartOfSpelledToken = &T; + Result.SpelledToken = &T; + auto Expanded = + TB.expandedTokens(SM.getMacroArgExpandedLocation(T.location())); + if (Expanded.size() == 1 && Expanded.front().text(SM) == Result.Text) + Result.ExpandedToken = &Expanded.front(); + return Result; + } + } + FileID File; + unsigned Offset; + std::tie(File, Offset) = SM.getDecomposedLoc(SpelledLoc); + bool Invalid = false; + llvm::StringRef Code = SM.getBufferData(File, &Invalid); + if (Invalid) + return llvm::None; + unsigned B = Offset, E = Offset; + while (B > 0 && isIdentifierBody(Code[B - 1])) + --B; + while (E < Code.size() && isIdentifierBody(Code[E])) + ++E; + if (B == E) + return llvm::None; + + SpelledWord Result; + Result.Location = SM.getComposedLoc(File, B); + Result.Text = Code.slice(B, E); + Result.LikelyIdentifier = + isLikelyIdentifier(Result.Text, Code.substr(0, B), Code.substr(E)) && + // should not be a keyword + tok::isAnyIdentifier( + IdentifierTable(LangOpts).get(Result.Text).getTokenID()); + for (const auto &T : Touching) + if (T.location() <= Result.Location) + Result.PartOfSpelledToken = &T; + return Result; +} + llvm::Optional locateMacroAt(const syntax::Token &SpelledTok, Preprocessor &PP) { SourceLocation Loc = SpelledTok.location(); diff --git a/clang-tools-extra/clangd/SourceCode.h b/clang-tools-extra/clangd/SourceCode.h index dfa685fdd795..d1e5aa5f7c2b 100644 --- a/clang-tools-extra/clangd/SourceCode.h +++ b/clang-tools-extra/clangd/SourceCode.h @@ -216,6 +216,35 @@ std::vector collectIdentifierRanges(llvm::StringRef Identifier, /// - drops stopwords like "get" and "for" llvm::StringSet<> collectWords(llvm::StringRef Content); +// Something that looks like a word in the source code. +// Could be a "real" token that's "live" in the AST, a spelled token consumed by +// the preprocessor, or part of a spelled token (e.g. word in a comment). +struct SpelledWord { + // (Spelling) location of the start of the word. + SourceLocation Location; + // The range of the word itself, excluding any quotes. + // This is a subrange of the file buffer. + llvm::StringRef Text; + // Whether this word is likely to refer to an identifier. True if: + // - the word is a spelled identifier token + // - Text is identifier-like (e.g. "foo_bar") + // - Text is surrounded by backticks (e.g. Foo in "// returns `Foo`") + bool LikelyIdentifier = false; + // Set if the word is contained in a token spelled in the file. + // (This should always be true, but comments aren't retained by TokenBuffer). + const syntax::Token *PartOfSpelledToken = nullptr; + // Set if the word is exactly a token spelled in the file. + const syntax::Token *SpelledToken = nullptr; + // Set if the word is a token spelled in the file, and that token survives + // preprocessing to emit an expanded token spelled the same way. + const syntax::Token *ExpandedToken = nullptr; + + // Find the unique word that contains SpelledLoc or starts/ends there. + static llvm::Optional touching(SourceLocation SpelledLoc, + const syntax::TokenBuffer &TB, + const LangOptions &LangOpts); +}; + /// Heuristically determine namespaces visible at a point, without parsing Code. /// This considers using-directives and enclosing namespace-declarations that /// are visible (and not obfuscated) in the file itself (not headers). diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp index 2e2e6602c8d3..d17fa52bd82c 100644 --- a/clang-tools-extra/clangd/XRefs.cpp +++ b/clang-tools-extra/clangd/XRefs.cpp @@ -34,6 +34,7 @@ #include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" +#include "clang/Basic/TokenKinds.h" #include "clang/Index/IndexDataConsumer.h" #include "clang/Index/IndexSymbol.h" #include "clang/Index/IndexingAction.h" @@ -48,6 +49,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Error.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/Path.h" #include "llvm/Support/raw_ostream.h" @@ -315,93 +317,44 @@ locateASTReferent(SourceLocation CurLoc, const syntax::Token *TouchedIdentifier, return Result; } -llvm::StringRef wordTouching(llvm::StringRef Code, unsigned Offset) { - unsigned B = Offset, E = Offset; - while (B > 0 && isIdentifierBody(Code[B - 1])) - --B; - while (E < Code.size() && isIdentifierBody(Code[E])) - ++E; - return Code.slice(B, E); +bool tokenSpelledAt(SourceLocation SpellingLoc, const syntax::TokenBuffer &TB) { + auto ExpandedTokens = TB.expandedTokens( + TB.sourceManager().getMacroArgExpandedLocation(SpellingLoc)); + return !ExpandedTokens.empty(); } -bool isLikelyToBeIdentifier(StringRef Word) { - // Word contains underscore. - // This handles things like snake_case and MACRO_CASE. - if (Word.contains('_')) { - return true; - } - // Word contains capital letter other than at beginning. - // This handles things like lowerCamel and UpperCamel. - // The check for also containing a lowercase letter is to rule out - // initialisms like "HTTP". - bool HasLower = Word.find_if(clang::isLowercase) != StringRef::npos; - bool HasUpper = Word.substr(1).find_if(clang::isUppercase) != StringRef::npos; - if (HasLower && HasUpper) { - return true; - } - // FIXME: There are other signals we could listen for. - // Some of these require inspecting the surroundings of the word as well. - // - mid-sentence Capitalization - // - markup like quotes / backticks / brackets / "\p" - // - word has a qualifier (foo::bar) - return false; -} - -bool tokenSurvivedPreprocessing(SourceLocation Loc, - const syntax::TokenBuffer &TB) { - auto WordExpandedTokens = - TB.expandedTokens(TB.sourceManager().getMacroArgExpandedLocation(Loc)); - return !WordExpandedTokens.empty(); +llvm::StringRef sourcePrefix(SourceLocation Loc, const SourceManager &SM) { + auto D = SM.getDecomposedLoc(Loc); + bool Invalid = false; + llvm::StringRef Buf = SM.getBufferData(D.first, &Invalid); + if (Invalid || D.second > Buf.size()) + return ""; + return Buf.substr(0, D.second); } } // namespace std::vector -locateSymbolNamedTextuallyAt(ParsedAST &AST, const SymbolIndex *Index, - SourceLocation Loc, - const std::string &MainFilePath) { - const auto &SM = AST.getSourceManager(); - - // Get the raw word at the specified location. - unsigned Pos; - FileID File; - std::tie(File, Pos) = SM.getDecomposedLoc(Loc); - llvm::StringRef Code = SM.getBufferData(File); - llvm::StringRef Word = wordTouching(Code, Pos); - if (Word.empty()) - return {}; - unsigned WordOffset = Word.data() - Code.data(); - SourceLocation WordStart = SM.getComposedLoc(File, WordOffset); - - // Attempt to determine the kind of token that contains the word, - // and bail if it's a string literal. Note that we cannot always - // determine the token kind (e.g. comments, for which we do want - // to activate, are not retained by TokenBuffer). - for (syntax::Token T : - syntax::spelledTokensTouching(WordStart, AST.getTokens())) { - if (T.range(AST.getSourceManager()).touches(WordOffset + Word.size())) { - if (isStringLiteral(T.kind())) - return {}; - } - } - - // Do not consider tokens that survived preprocessing. - // We are erring on the safe side here, as a user may expect to get - // accurate (as opposed to textual-heuristic) results for such tokens. - // FIXME: Relax this for dependent code. - if (tokenSurvivedPreprocessing(WordStart, AST.getTokens())) +locateSymbolTextually(const SpelledWord &Word, ParsedAST &AST, + const SymbolIndex *Index, + const std::string &MainFilePath) { + // Don't use heuristics if this is a real identifier, or not an identifier. + if (Word.ExpandedToken || !Word.LikelyIdentifier || !Index) return {}; - - // Additionally filter for signals that the word is likely to be an - // identifier. This avoids triggering on e.g. random words in a comment. - if (!isLikelyToBeIdentifier(Word)) + // We don't want to handle words in string literals. It'd be nice to whitelist + // comments instead, but they're not retained in TokenBuffer. + if (Word.PartOfSpelledToken && + isStringLiteral(Word.PartOfSpelledToken->kind())) return {}; + const auto &SM = AST.getSourceManager(); // Look up the selected word in the index. FuzzyFindRequest Req; - Req.Query = Word.str(); + Req.Query = Word.Text.str(); Req.ProximityPaths = {MainFilePath}; - Req.Scopes = visibleNamespaces(Code.take_front(Pos), AST.getLangOpts()); + // Find the namespaces to query by lexing the file. + Req.Scopes = + visibleNamespaces(sourcePrefix(Word.Location, SM), AST.getLangOpts()); // FIXME: For extra strictness, consider AnyScope=false. Req.AnyScope = true; // We limit the results to 3 further below. This limit is to avoid fetching @@ -416,7 +369,7 @@ locateSymbolNamedTextuallyAt(ParsedAST &AST, const SymbolIndex *Index, // This is to avoid too many false positives. // We could relax this in the future (e.g. to allow for typos) if we make // the query more accurate by other means. - if (Sym.Name != Word) + if (Sym.Name != Word.Text) return; // Exclude constructor results. They have the same name as the class, @@ -481,6 +434,82 @@ locateSymbolNamedTextuallyAt(ParsedAST &AST, const SymbolIndex *Index, return Results; } +const syntax::Token *findNearbyIdentifier(const SpelledWord &Word, + const syntax::TokenBuffer &TB) { + // Don't use heuristics if this is a real identifier. + // Unlikely identifiers are OK if they were used as identifiers nearby. + if (Word.ExpandedToken) + return nullptr; + // We don't want to handle words in string literals. It'd be nice to whitelist + // comments instead, but they're not retained in TokenBuffer. + if (Word.PartOfSpelledToken && + isStringLiteral(Word.PartOfSpelledToken->kind())) + return {}; + + const SourceManager &SM = TB.sourceManager(); + // We prefer the closest possible token, line-wise. Backwards is penalized. + // Ties are implicitly broken by traversal order (first-one-wins). + auto File = SM.getFileID(Word.Location); + unsigned WordLine = SM.getSpellingLineNumber(Word.Location); + auto Cost = [&](SourceLocation Loc) -> unsigned { + assert(SM.getFileID(Loc) == File && "spelled token in wrong file?"); + unsigned Line = SM.getSpellingLineNumber(Loc); + if (Line > WordLine) + return 1 + llvm::Log2_64(Line - WordLine); + if (Line < WordLine) + return 2 + llvm::Log2_64(WordLine - Line); + return 0; + }; + const syntax::Token *BestTok = nullptr; + // Search bounds are based on word length: 2^N lines forward. + unsigned BestCost = Word.Text.size() + 1; + + // Updates BestTok and BestCost if Tok is a good candidate. + // May return true if the cost is too high for this token. + auto Consider = [&](const syntax::Token &Tok) { + if (!(Tok.kind() == tok::identifier && Tok.text(SM) == Word.Text)) + return false; + // No point guessing the same location we started with. + if (Tok.location() == Word.Location) + return false; + // We've done cheap checks, compute cost so we can break the caller's loop. + unsigned TokCost = Cost(Tok.location()); + if (TokCost >= BestCost) + return true; // causes the outer loop to break. + // Allow locations that might be part of the AST, and macros (even if empty) + // but not things like disabled preprocessor sections. + if (!(tokenSpelledAt(Tok.location(), TB) || TB.expansionStartingAt(&Tok))) + return false; + // We already verified this token is an improvement. + BestCost = TokCost; + BestTok = &Tok; + return false; + }; + auto SpelledTokens = TB.spelledTokens(File); + // Find where the word occurred in the token stream, to search forward & back. + auto *I = llvm::partition_point(SpelledTokens, [&](const syntax::Token &T) { + assert(SM.getFileID(T.location()) == SM.getFileID(Word.Location)); + return T.location() >= Word.Location; // Comparison OK: same file. + }); + // Search for matches after the cursor. + for (const syntax::Token &Tok : llvm::makeArrayRef(I, SpelledTokens.end())) + if (Consider(Tok)) + break; // costs of later tokens are greater... + // Search for matches before the cursor. + for (const syntax::Token &Tok : + llvm::reverse(llvm::makeArrayRef(SpelledTokens.begin(), I))) + if (Consider(Tok)) + break; + + if (BestTok) + vlog( + "Word {0} under cursor {1} isn't a token (after PP), trying nearby {2}", + Word.Text, Word.Location.printToString(SM), + BestTok->location().printToString(SM)); + + return BestTok; +} + std::vector locateSymbolAt(ParsedAST &AST, Position Pos, const SymbolIndex *Index) { const auto &SM = AST.getSourceManager(); @@ -516,7 +545,28 @@ std::vector locateSymbolAt(ParsedAST &AST, Position Pos, if (!ASTResults.empty()) return ASTResults; - return locateSymbolNamedTextuallyAt(AST, Index, *CurLoc, *MainFilePath); + // If the cursor can't be resolved directly, try fallback strategies. + auto Word = + SpelledWord::touching(*CurLoc, AST.getTokens(), AST.getLangOpts()); + if (Word) { + // Is the same word nearby a real identifier that might refer to something? + if (const syntax::Token *NearbyIdent = + findNearbyIdentifier(*Word, AST.getTokens())) { + if (auto Macro = locateMacroReferent(*NearbyIdent, AST, *MainFilePath)) + return {*std::move(Macro)}; + ASTResults = locateASTReferent(NearbyIdent->location(), NearbyIdent, AST, + *MainFilePath, Index); + if (!ASTResults.empty()) + return ASTResults; + } + // No nearby word, or it didn't refer to anything either. Try the index. + auto TextualResults = + locateSymbolTextually(*Word, AST, Index, *MainFilePath); + if (!TextualResults.empty()) + return TextualResults; + } + + return {}; } std::vector getDocumentLinks(ParsedAST &AST) { diff --git a/clang-tools-extra/clangd/XRefs.h b/clang-tools-extra/clangd/XRefs.h index 8f42ca8d3265..af78ec780c5a 100644 --- a/clang-tools-extra/clangd/XRefs.h +++ b/clang-tools-extra/clangd/XRefs.h @@ -16,6 +16,7 @@ #include "FormattedString.h" #include "Path.h" #include "Protocol.h" +#include "SourceCode.h" #include "index/Index.h" #include "index/SymbolLocation.h" #include "clang/AST/Type.h" @@ -26,6 +27,10 @@ #include namespace clang { +namespace syntax { +class Token; +class TokenBuffer; +} // namespace syntax namespace clangd { class ParsedAST; @@ -49,20 +54,22 @@ llvm::raw_ostream &operator<<(llvm::raw_ostream &, const LocatedSymbol &); std::vector locateSymbolAt(ParsedAST &AST, Position Pos, const SymbolIndex *Index = nullptr); -// Tries to provide a textual fallback for locating a symbol referenced at -// a location, by looking up the word under the cursor as a symbol name in the -// index. The aim is to pick up references to symbols in contexts where +// Tries to provide a textual fallback for locating a symbol by looking up the +// word under the cursor as a symbol name in the index. +// The aim is to pick up references to symbols in contexts where // AST-based resolution does not work, such as comments, strings, and PP -// disabled regions. The implementation takes a number of measures to avoid -// false positives, such as looking for some signal that the word at the -// given location is likely to be an identifier. The function does not -// currently return results for locations that end up as real expanded -// tokens, although this may be relaxed for e.g. dependent code in the future. +// disabled regions. // (This is for internal use by locateSymbolAt, and is exposed for testing). std::vector -locateSymbolNamedTextuallyAt(ParsedAST &AST, const SymbolIndex *Index, - SourceLocation Loc, - const std::string &MainFilePath); +locateSymbolTextually(const SpelledWord &Word, ParsedAST &AST, + const SymbolIndex *Index, + const std::string &MainFilePath); + +// Try to find a proximate occurrence of `Word` as an identifier, which can be +// used to resolve it. +// (This is for internal use by locateSymbolAt, and is exposed for testing). +const syntax::Token *findNearbyIdentifier(const SpelledWord &Word, + const syntax::TokenBuffer &TB); /// Get all document links std::vector getDocumentLinks(ParsedAST &AST); diff --git a/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp b/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp index 76a3a3cac267..71721fe81cd9 100644 --- a/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp +++ b/clang-tools-extra/clangd/unittests/SourceCodeTests.cpp @@ -12,6 +12,7 @@ #include "TestTU.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/SourceLocation.h" +#include "clang/Basic/TokenKinds.h" #include "clang/Format/Format.h" #include "llvm/Support/Error.h" #include "llvm/Support/raw_os_ostream.h" @@ -328,6 +329,101 @@ TEST(SourceCodeTests, CollectWords) { EXPECT_EQ(ActualWords, ExpectedWords); } +class SpelledWordsTest : public ::testing::Test { + llvm::Optional AST; + + llvm::Optional tryWord(const char *Text) { + llvm::Annotations A(Text); + auto TU = TestTU::withCode(A.code()); + AST = TU.build(); + auto SW = SpelledWord::touching( + AST->getSourceManager().getComposedLoc( + AST->getSourceManager().getMainFileID(), A.point()), + AST->getTokens(), AST->getLangOpts()); + if (A.ranges().size()) { + llvm::StringRef Want = A.code().slice(A.range().Begin, A.range().End); + EXPECT_EQ(Want, SW->Text) << Text; + } + return SW; + } + +protected: + SpelledWord word(const char *Text) { + auto Result = tryWord(Text); + EXPECT_TRUE(Result) << Text; + return Result.getValueOr(SpelledWord()); + } + + void noWord(const char *Text) { EXPECT_FALSE(tryWord(Text)) << Text; } +}; + +TEST_F(SpelledWordsTest, HeuristicBoundaries) { + word("// [[^foo]] "); + word("// [[f^oo]] "); + word("// [[foo^]] "); + word("// [[foo^]]+bar "); + noWord("//^ foo "); + noWord("// foo ^"); +} + +TEST_F(SpelledWordsTest, LikelyIdentifier) { + EXPECT_FALSE(word("// ^foo ").LikelyIdentifier); + EXPECT_TRUE(word("// [[^foo_bar]] ").LikelyIdentifier); + EXPECT_TRUE(word("// [[^fooBar]] ").LikelyIdentifier); + EXPECT_FALSE(word("// H^TTP ").LikelyIdentifier); + EXPECT_TRUE(word("// \\p [[^foo]] ").LikelyIdentifier); + EXPECT_TRUE(word("// @param[in] [[^foo]] ").LikelyIdentifier); + EXPECT_TRUE(word("// `[[f^oo]]` ").LikelyIdentifier); + EXPECT_TRUE(word("// bar::[[f^oo]] ").LikelyIdentifier); + EXPECT_TRUE(word("// [[f^oo]]::bar ").LikelyIdentifier); +} + +TEST_F(SpelledWordsTest, Comment) { + auto W = word("// [[^foo]]"); + EXPECT_FALSE(W.PartOfSpelledToken); + EXPECT_FALSE(W.SpelledToken); + EXPECT_FALSE(W.ExpandedToken); +} + +TEST_F(SpelledWordsTest, PartOfString) { + auto W = word(R"( auto str = "foo [[^bar]] baz"; )"); + ASSERT_TRUE(W.PartOfSpelledToken); + EXPECT_EQ(W.PartOfSpelledToken->kind(), tok::string_literal); + EXPECT_FALSE(W.SpelledToken); + EXPECT_FALSE(W.ExpandedToken); +} + +TEST_F(SpelledWordsTest, DisabledSection) { + auto W = word(R"cpp( + #if 0 + foo [[^bar]] baz + #endif + )cpp"); + ASSERT_TRUE(W.SpelledToken); + EXPECT_EQ(W.SpelledToken->kind(), tok::identifier); + EXPECT_EQ(W.SpelledToken, W.PartOfSpelledToken); + EXPECT_FALSE(W.ExpandedToken); +} + +TEST_F(SpelledWordsTest, Macros) { + auto W = word(R"cpp( + #define ID(X) X + ID(int [[^i]]); + )cpp"); + ASSERT_TRUE(W.SpelledToken); + EXPECT_EQ(W.SpelledToken->kind(), tok::identifier); + EXPECT_EQ(W.SpelledToken, W.PartOfSpelledToken); + ASSERT_TRUE(W.ExpandedToken); + EXPECT_EQ(W.ExpandedToken->kind(), tok::identifier); + + W = word(R"cpp( + #define OBJECT Expansion; + int [[^OBJECT]]; + )cpp"); + EXPECT_TRUE(W.SpelledToken); + EXPECT_FALSE(W.ExpandedToken) << "Expanded token is spelled differently"; +} + TEST(SourceCodeTests, VisibleNamespaces) { std::vector>> Cases = { { diff --git a/clang-tools-extra/clangd/unittests/XRefsTests.cpp b/clang-tools-extra/clangd/unittests/XRefsTests.cpp index ce7f76ccf4f4..027939e15f77 100644 --- a/clang-tools-extra/clangd/unittests/XRefsTests.cpp +++ b/clang-tools-extra/clangd/unittests/XRefsTests.cpp @@ -685,10 +685,15 @@ TEST(LocateSymbol, Textual) { auto AST = TU.build(); auto Index = TU.index(); - auto Results = locateSymbolNamedTextuallyAt( - AST, Index.get(), + auto Word = SpelledWord::touching( cantFail(sourceLocationInMainFile(AST.getSourceManager(), T.point())), - testPath(TU.Filename)); + AST.getTokens(), AST.getLangOpts()); + if (!Word) { + ADD_FAILURE() << "No word touching point!" << Test; + continue; + } + auto Results = + locateSymbolTextually(*Word, AST, Index.get(), testPath(TU.Filename)); if (!WantDecl) { EXPECT_THAT(Results, IsEmpty()) << Test; @@ -788,10 +793,12 @@ TEST(LocateSymbol, TextualAmbiguous) { auto TU = TestTU::withCode(T.code()); auto AST = TU.build(); auto Index = TU.index(); - auto Results = locateSymbolNamedTextuallyAt( - AST, Index.get(), + auto Word = SpelledWord::touching( cantFail(sourceLocationInMainFile(AST.getSourceManager(), T.point())), - testPath(TU.Filename)); + AST.getTokens(), AST.getLangOpts()); + ASSERT_TRUE(Word); + auto Results = + locateSymbolTextually(*Word, AST, Index.get(), testPath(TU.Filename)); EXPECT_THAT(Results, UnorderedElementsAre(Sym("uniqueMethodName", T.range("FooLoc")), Sym("uniqueMethodName", T.range("BarLoc")))); @@ -985,6 +992,101 @@ TEST(LocateSymbol, WithPreamble) { ElementsAre(Sym("foo", FooWithoutHeader.range()))); } +TEST(LocateSymbol, NearbyTokenSmoke) { + auto T = Annotations(R"cpp( + // prints e^rr and crashes + void die(const char* [[err]]); + )cpp"); + auto AST = TestTU::withCode(T.code()).build(); + // We don't pass an index, so can't hit index-based fallback. + EXPECT_THAT(locateSymbolAt(AST, T.point()), + ElementsAre(Sym("err", T.range()))); +} + +TEST(LocateSymbol, NearbyIdentifier) { + const char *Tests[] = { + R"cpp( + // regular identifiers (won't trigger) + int hello; + int y = he^llo; + )cpp", + R"cpp( + // disabled preprocessor sections + int [[hello]]; + #if 0 + int y = ^hello; + #endif + )cpp", + R"cpp( + // comments + // he^llo, world + int [[hello]]; + )cpp", + R"cpp( + // not triggered by string literals + int hello; + const char* greeting = "h^ello, world"; + )cpp", + + R"cpp( + // can refer to macro invocations + #define INT int + [[INT]] x; + // I^NT + )cpp", + + R"cpp( + // can refer to macro invocations (even if they expand to nothing) + #define EMPTY + [[EMPTY]] int x; + // E^MPTY + )cpp", + + R"cpp( + // prefer nearest occurrence, backwards is worse than forwards + int hello; + int x = hello; + // h^ello + int y = [[hello]]; + int z = hello; + )cpp", + + R"cpp( + // short identifiers find near results + int [[hi]]; + // h^i + )cpp", + R"cpp( + // short identifiers don't find far results + int hi; + + + + // h^i + )cpp", + }; + for (const char *Test : Tests) { + Annotations T(Test); + auto AST = TestTU::withCode(T.code()).build(); + const auto &SM = AST.getSourceManager(); + llvm::Optional Nearby; + auto Word = + SpelledWord::touching(cantFail(sourceLocationInMainFile(SM, T.point())), + AST.getTokens(), AST.getLangOpts()); + if (!Word) { + ADD_FAILURE() << "No word at point! " << Test; + continue; + } + if (const auto *Tok = findNearbyIdentifier(*Word, AST.getTokens())) + Nearby = halfOpenToRange(SM, CharSourceRange::getCharRange( + Tok->location(), Tok->endLocation())); + if (T.ranges().empty()) + EXPECT_THAT(Nearby, Eq(llvm::None)) << Test; + else + EXPECT_EQ(Nearby, T.range()) << Test; + } +} + TEST(FindReferences, WithinAST) { const char *Tests[] = { R"cpp(// Local variable -- GitLab From 2d0c9bf55ea659b426d212ec4757754af5fbe0fb Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 22 Apr 2020 13:54:36 -0400 Subject: [PATCH 121/910] [libc++] Update the cache for building libc++/libc++abi on Apple --- libcxx/cmake/caches/Apple.cmake | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/libcxx/cmake/caches/Apple.cmake b/libcxx/cmake/caches/Apple.cmake index 588635645045..5ccc53aeee0d 100644 --- a/libcxx/cmake/caches/Apple.cmake +++ b/libcxx/cmake/caches/Apple.cmake @@ -3,15 +3,14 @@ set(CMAKE_POSITION_INDEPENDENT_CODE OFF CACHE BOOL "") set(LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") set(LIBCXX_ENABLE_ASSERTIONS OFF CACHE BOOL "") - set(LIBCXX_ABI_VERSION "1" CACHE STRING "") - set(LIBCXX_ENABLE_EXPERIMENTAL_LIBRARY OFF CACHE BOOL "") set(LIBCXX_ENABLE_STATIC OFF CACHE BOOL "") set(LIBCXX_ENABLE_SHARED ON CACHE BOOL "") set(LIBCXX_CXX_ABI libcxxabi CACHE STRING "") - set(LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") -set(LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") - set(LIBCXX_HIDE_FROM_ABI_PER_TU_BY_DEFAULT ON CACHE BOOL "") + +set(LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") +set(LIBCXXABI_ENABLE_PIC OFF CACHE BOOL "") +set(LIBCXXABI_ENABLE_ASSERTIONS OFF CACHE BOOL "") -- GitLab From 1b3f1f443670f202a0490ccf9d1f7b28e949bfe7 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 22 Apr 2020 14:28:15 -0400 Subject: [PATCH 122/910] Rename warning identifiers from cxx2a to cxx20; NFC. --- .../include/clang/Basic/DiagnosticLexKinds.td | 4 +-- .../clang/Basic/DiagnosticParseKinds.td | 2 +- .../clang/Basic/DiagnosticSemaKinds.td | 30 +++++++++---------- clang/lib/Lex/Lexer.cpp | 2 +- clang/lib/Lex/Preprocessor.cpp | 2 +- clang/lib/Parse/ParseDecl.cpp | 2 +- clang/lib/Sema/SemaDeclAttr.cpp | 2 +- clang/lib/Sema/SemaDeclCXX.cpp | 4 +-- clang/lib/Sema/SemaExpr.cpp | 14 ++++----- clang/lib/Sema/SemaInit.cpp | 4 +-- clang/lib/Sema/SemaLambda.cpp | 2 +- 11 files changed, 34 insertions(+), 34 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticLexKinds.td b/clang/include/clang/Basic/DiagnosticLexKinds.td index 9e0449d34104..ef90bdf84c8a 100644 --- a/clang/include/clang/Basic/DiagnosticLexKinds.td +++ b/clang/include/clang/Basic/DiagnosticLexKinds.td @@ -33,7 +33,7 @@ def warn_cxx98_compat_less_colon_colon : Warning< def warn_cxx17_compat_spaceship : Warning< "'<=>' operator is incompatible with C++ standards before C++20">, InGroup, DefaultIgnore; -def warn_cxx2a_compat_spaceship : Warning< +def warn_cxx20_compat_spaceship : Warning< "'<=>' is a single token in C++20; " "add a space to avoid a change in behavior">, InGroup; @@ -78,7 +78,7 @@ def ext_token_used : Extension<"extension used">, def warn_cxx11_keyword : Warning<"'%0' is a keyword in C++11">, InGroup, DefaultIgnore; -def warn_cxx2a_keyword : Warning<"'%0' is a keyword in C++20">, +def warn_cxx20_keyword : Warning<"'%0' is a keyword in C++20">, InGroup, DefaultIgnore; def ext_unterminated_char_or_string : ExtWarn< diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 29497f9c8296..337614c33661 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -676,7 +676,7 @@ def err_ms_property_expected_comma_or_rparen : Error< def err_ms_property_initializer : Error< "property declaration cannot have an in-class initializer">; -def warn_cxx2a_compat_explicit_bool : Warning< +def warn_cxx20_compat_explicit_bool : Warning< "this expression will be parsed as explicit(bool) in C++20">, InGroup, DefaultIgnore; def warn_cxx17_compat_explicit_bool : Warning< diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 014ee1c2f2d7..1101bd5a4bb6 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -2009,7 +2009,7 @@ def err_reference_bind_init_list : Error< def err_init_list_bad_dest_type : Error< "%select{|non-aggregate }0type %1 cannot be initialized with an initializer " "list">; -def warn_cxx2a_compat_aggregate_init_with_ctors : Warning< +def warn_cxx20_compat_aggregate_init_with_ctors : Warning< "aggregate initialization of type %0 with user-declared constructors " "is incompatible with C++20">, DefaultIgnore, InGroup; @@ -2530,7 +2530,7 @@ def warn_cxx11_compat_constexpr_body_invalid_stmt : Warning< "use of this statement in a constexpr %select{function|constructor}0 " "is incompatible with C++ standards before C++14">, InGroup, DefaultIgnore; -def ext_constexpr_body_invalid_stmt_cxx2a : ExtWarn< +def ext_constexpr_body_invalid_stmt_cxx20 : ExtWarn< "use of this statement in a constexpr %select{function|constructor}0 " "is a C++20 extension">, InGroup; def warn_cxx17_compat_constexpr_body_invalid_stmt : Warning< @@ -2593,7 +2593,7 @@ def note_constexpr_body_previous_return : Note< "previous return statement is here">; // C++20 function try blocks in constexpr -def ext_constexpr_function_try_block_cxx2a : ExtWarn< +def ext_constexpr_function_try_block_cxx20 : ExtWarn< "function try block in constexpr %select{function|constructor}0 is " "a C++20 extension">, InGroup; def warn_cxx17_compat_constexpr_function_try_block : Warning< @@ -6294,10 +6294,10 @@ def note_array_init_plain_string_into_char8_t : Note< def err_array_init_utf8_string_into_char : Error< "%select{|ISO C++20 does not permit }0initialization of char array with " "UTF-8 string literal%select{ is not permitted by '-fchar8_t'|}0">; -def warn_cxx2a_compat_utf8_string : Warning< +def warn_cxx20_compat_utf8_string : Warning< "type of UTF-8 string literal will change from array of const char to " "array of const char8_t in C++20">, InGroup, DefaultIgnore; -def note_cxx2a_compat_utf8_string_remove_u8 : Note< +def note_cxx20_compat_utf8_string_remove_u8 : Note< "remove 'u8' prefix to avoid a change of behavior; " "Clang encodes unprefixed narrow string literals as UTF-8">; def err_array_init_different_type : Error< @@ -6438,7 +6438,7 @@ def warn_arith_conv_enum_float : Warning< "%plural{2:with|4:from|:and}0 " "%select{enumeration|floating-point}1 type %3">, InGroup, DefaultIgnore; -def warn_arith_conv_enum_float_cxx2a : Warning< +def warn_arith_conv_enum_float_cxx20 : Warning< "%sub{select_arith_conv_kind}0 " "%select{floating-point|enumeration}1 type %2 " "%plural{2:with|4:from|:and}0 " @@ -6448,27 +6448,27 @@ def warn_arith_conv_mixed_enum_types : Warning< "%sub{select_arith_conv_kind}0 " "different enumeration types%diff{ ($ and $)|}1,2">, InGroup, DefaultIgnore; -def warn_arith_conv_mixed_enum_types_cxx2a : Warning< +def warn_arith_conv_mixed_enum_types_cxx20 : Warning< "%sub{select_arith_conv_kind}0 " "different enumeration types%diff{ ($ and $)|}1,2 is deprecated">, InGroup; def warn_arith_conv_mixed_anon_enum_types : Warning< warn_arith_conv_mixed_enum_types.Text>, InGroup, DefaultIgnore; -def warn_arith_conv_mixed_anon_enum_types_cxx2a : Warning< - warn_arith_conv_mixed_enum_types_cxx2a.Text>, +def warn_arith_conv_mixed_anon_enum_types_cxx20 : Warning< + warn_arith_conv_mixed_enum_types_cxx20.Text>, InGroup; def warn_conditional_mixed_enum_types : Warning< warn_arith_conv_mixed_enum_types.Text>, InGroup, DefaultIgnore; -def warn_conditional_mixed_enum_types_cxx2a : Warning< - warn_arith_conv_mixed_enum_types_cxx2a.Text>, +def warn_conditional_mixed_enum_types_cxx20 : Warning< + warn_arith_conv_mixed_enum_types_cxx20.Text>, InGroup; def warn_comparison_mixed_enum_types : Warning< warn_arith_conv_mixed_enum_types.Text>, InGroup; -def warn_comparison_mixed_enum_types_cxx2a : Warning< - warn_arith_conv_mixed_enum_types_cxx2a.Text>, +def warn_comparison_mixed_enum_types_cxx20 : Warning< + warn_arith_conv_mixed_enum_types_cxx20.Text>, InGroup; def warn_comparison_of_mixed_enum_types_switch : Warning< "comparison of different enumeration types in switch statement" @@ -7253,7 +7253,7 @@ let CategoryName = "Lambda Issue" in { def warn_cxx17_compat_equals_this_lambda_capture : Warning< "explicit capture of 'this' with a capture default of '=' is incompatible " "with C++ standards before C++20">, InGroup, DefaultIgnore; - def ext_equals_this_lambda_capture_cxx2a : ExtWarn< + def ext_equals_this_lambda_capture_cxx20 : ExtWarn< "explicit capture of 'this' with a capture default of '=' " "is a C++20 extension">, InGroup; def warn_deprecated_this_capture : Warning< @@ -8129,7 +8129,7 @@ def ext_cxx14_attr : Extension< "use of the %0 attribute is a C++14 extension">, InGroup; def ext_cxx17_attr : Extension< "use of the %0 attribute is a C++17 extension">, InGroup; -def ext_cxx2a_attr : Extension< +def ext_cxx20_attr : Extension< "use of the %0 attribute is a C++20 extension">, InGroup; def warn_unused_comparison : Warning< diff --git a/clang/lib/Lex/Lexer.cpp b/clang/lib/Lex/Lexer.cpp index c9d99352f1f4..016263108602 100644 --- a/clang/lib/Lex/Lexer.cpp +++ b/clang/lib/Lex/Lexer.cpp @@ -3711,7 +3711,7 @@ LexNextToken: // Suggest adding a space between the '<=' and the '>' to avoid a // change in semantics if this turns up in C++ <=17 mode. if (getLangOpts().CPlusPlus && !isLexingRawMode()) { - Diag(BufferPtr, diag::warn_cxx2a_compat_spaceship) + Diag(BufferPtr, diag::warn_cxx20_compat_spaceship) << FixItHint::CreateInsertion( getSourceLocation(CurPtr + SizeTmp, SizeTmp2), " "); } diff --git a/clang/lib/Lex/Preprocessor.cpp b/clang/lib/Lex/Preprocessor.cpp index b29f0684df5d..961b55c9387d 100644 --- a/clang/lib/Lex/Preprocessor.cpp +++ b/clang/lib/Lex/Preprocessor.cpp @@ -772,7 +772,7 @@ static diag::kind getFutureCompatDiagKind(const IdentifierInfo &II, #define CXX11_KEYWORD(NAME, FLAGS) \ .Case(#NAME, diag::warn_cxx11_keyword) #define CXX20_KEYWORD(NAME, FLAGS) \ - .Case(#NAME, diag::warn_cxx2a_keyword) + .Case(#NAME, diag::warn_cxx20_keyword) #include "clang/Basic/TokenKinds.def" ; diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index a5c126188bf0..864b7b12fbab 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -3730,7 +3730,7 @@ void Parser::ParseDeclarationSpecifiers(DeclSpec &DS, } else Tracker.skipToEnd(); } else { - Diag(Tok.getLocation(), diag::warn_cxx2a_compat_explicit_bool); + Diag(Tok.getLocation(), diag::warn_cxx20_compat_explicit_bool); } } isInvalid = DS.setFunctionSpecExplicit(ExplicitLoc, PrevSpec, DiagID, diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 45bea5d0474e..29c3b8d8567b 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -2840,7 +2840,7 @@ static void handleWarnUnusedResult(Sema &S, Decl *D, const ParsedAttr &AL) { const LangOptions &LO = S.getLangOpts(); if (AL.getNumArgs() == 1) { if (LO.CPlusPlus && !LO.CPlusPlus20) - S.Diag(AL.getLoc(), diag::ext_cxx2a_attr) << AL; + S.Diag(AL.getLoc(), diag::ext_cxx20_attr) << AL; // Since this this is spelled [[nodiscard]], get the optional string // literal. If in C++ mode, but not in C++2a mode, diagnose as an diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 9bb37a9b1336..e827fe3b1ace 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -2139,7 +2139,7 @@ static bool CheckConstexprFunctionBody(Sema &SemaRef, const FunctionDecl *Dcl, case Sema::CheckConstexprKind::Diagnose: SemaRef.Diag(Body->getBeginLoc(), !SemaRef.getLangOpts().CPlusPlus20 - ? diag::ext_constexpr_function_try_block_cxx2a + ? diag::ext_constexpr_function_try_block_cxx20 : diag::warn_cxx17_compat_constexpr_function_try_block) << isa(Dcl); break; @@ -2169,7 +2169,7 @@ static bool CheckConstexprFunctionBody(Sema &SemaRef, const FunctionDecl *Dcl, SemaRef.Diag(Cxx2aLoc, SemaRef.getLangOpts().CPlusPlus20 ? diag::warn_cxx17_compat_constexpr_body_invalid_stmt - : diag::ext_constexpr_body_invalid_stmt_cxx2a) + : diag::ext_constexpr_body_invalid_stmt_cxx20) << isa(Dcl); } else if (Cxx1yLoc.isValid()) { SemaRef.Diag(Cxx1yLoc, diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index b4072f04f724..5a0b67f0cd4a 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -1392,7 +1392,7 @@ static void checkEnumArithmeticConversions(Sema &S, Expr *LHS, Expr *RHS, if ((!IsCompAssign && LEnum && R->isFloatingType()) || (REnum && L->isFloatingType())) { S.Diag(Loc, S.getLangOpts().CPlusPlus20 - ? diag::warn_arith_conv_enum_float_cxx2a + ? diag::warn_arith_conv_enum_float_cxx20 : diag::warn_arith_conv_enum_float) << LHS->getSourceRange() << RHS->getSourceRange() << (int)ACK << LEnum << L << R; @@ -1405,23 +1405,23 @@ static void checkEnumArithmeticConversions(Sema &S, Expr *LHS, Expr *RHS, // user cares about this, but this situation is still deprecated in // C++2a. Use a different warning group. DiagID = S.getLangOpts().CPlusPlus20 - ? diag::warn_arith_conv_mixed_anon_enum_types_cxx2a + ? diag::warn_arith_conv_mixed_anon_enum_types_cxx20 : diag::warn_arith_conv_mixed_anon_enum_types; } else if (ACK == Sema::ACK_Conditional) { // Conditional expressions are separated out because they have // historically had a different warning flag. DiagID = S.getLangOpts().CPlusPlus20 - ? diag::warn_conditional_mixed_enum_types_cxx2a + ? diag::warn_conditional_mixed_enum_types_cxx20 : diag::warn_conditional_mixed_enum_types; } else if (ACK == Sema::ACK_Comparison) { // Comparison expressions are separated out because they have // historically had a different warning flag. DiagID = S.getLangOpts().CPlusPlus20 - ? diag::warn_comparison_mixed_enum_types_cxx2a + ? diag::warn_comparison_mixed_enum_types_cxx20 : diag::warn_comparison_mixed_enum_types; } else { DiagID = S.getLangOpts().CPlusPlus20 - ? diag::warn_arith_conv_mixed_enum_types_cxx2a + ? diag::warn_arith_conv_mixed_enum_types_cxx20 : diag::warn_arith_conv_mixed_enum_types; } S.Diag(Loc, DiagID) << LHS->getSourceRange() << RHS->getSourceRange() @@ -1773,13 +1773,13 @@ Sema::ActOnStringLiteral(ArrayRef StringToks, Scope *UDLScope) { // becomes ill-formed in C++2a. if (getLangOpts().CPlusPlus && !getLangOpts().CPlusPlus20 && !getLangOpts().Char8 && Kind == StringLiteral::UTF8) { - Diag(StringTokLocs.front(), diag::warn_cxx2a_compat_utf8_string); + Diag(StringTokLocs.front(), diag::warn_cxx20_compat_utf8_string); // Create removals for all 'u8' prefixes in the string literal(s). This // ensures C++2a compatibility (but may change the program behavior when // built by non-Clang compilers for which the execution character set is // not always UTF-8). - auto RemovalDiag = PDiag(diag::note_cxx2a_compat_utf8_string_remove_u8); + auto RemovalDiag = PDiag(diag::note_cxx20_compat_utf8_string_remove_u8); SourceLocation RemovalDiagLoc; for (const Token &Tok : StringToks) { if (Tok.getKind() == tok::utf8_string_literal) { diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 1df4e81b99ec..9c6c9f103af2 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -1093,7 +1093,7 @@ void InitListChecker::CheckImplicitInitList(const InitializedEntity &Entity, auto *CXXRD = T->getAsCXXRecordDecl(); if (!VerifyOnly && CXXRD && CXXRD->hasUserDeclaredConstructor()) { SemaRef.Diag(StructuredSubobjectInitList->getBeginLoc(), - diag::warn_cxx2a_compat_aggregate_init_with_ctors) + diag::warn_cxx20_compat_aggregate_init_with_ctors) << StructuredSubobjectInitList->getSourceRange() << T; } } @@ -1236,7 +1236,7 @@ void InitListChecker::CheckExplicitInitList(const InitializedEntity &Entity, if (!HasEquivCtor) { SemaRef.Diag(IList->getBeginLoc(), - diag::warn_cxx2a_compat_aggregate_init_with_ctors) + diag::warn_cxx20_compat_aggregate_init_with_ctors) << IList->getSourceRange() << T; } } diff --git a/clang/lib/Sema/SemaLambda.cpp b/clang/lib/Sema/SemaLambda.cpp index 8b3c971d079d..b4336aa430eb 100644 --- a/clang/lib/Sema/SemaLambda.cpp +++ b/clang/lib/Sema/SemaLambda.cpp @@ -1054,7 +1054,7 @@ void Sema::ActOnStartOfLambdaDefinition(LambdaIntroducer &Intro, // redundant but accepted for compatibility with ISO C++14. --end note ] if (Intro.Default == LCD_ByCopy && C->Kind != LCK_StarThis) Diag(C->Loc, !getLangOpts().CPlusPlus20 - ? diag::ext_equals_this_lambda_capture_cxx2a + ? diag::ext_equals_this_lambda_capture_cxx20 : diag::warn_cxx17_compat_equals_this_lambda_capture); // C++11 [expr.prim.lambda]p12: -- GitLab From c19c3293d3b14b2366d7bd36737b9a1517031f6e Mon Sep 17 00:00:00 2001 From: Alexander Shaposhnikov Date: Wed, 22 Apr 2020 11:50:55 -0700 Subject: [PATCH 123/910] [ObjectYAML][MachO] Add support for relocations Add support for relocations for MachO to ObjectYAML / yaml2obj / obj2yaml. Test plan: make check-all Differential revision: https://reviews.llvm.org/D77844 --- llvm/include/llvm/ObjectYAML/MachOYAML.h | 20 + llvm/lib/ObjectYAML/MachOEmitter.cpp | 68 +- llvm/lib/ObjectYAML/MachOYAML.cpp | 13 + .../ObjectYAML/MachO/relocations_arm64.yaml | 590 +++++++++++++ .../ObjectYAML/MachO/relocations_armv7.yaml | 642 +++++++++++++++ .../ObjectYAML/MachO/relocations_empty.yaml | 65 ++ .../MachO/relocations_ppc_big_endian.yaml | 777 ++++++++++++++++++ .../ObjectYAML/MachO/relocations_x86_64.yaml | 494 +++++++++++ .../ObjectYAML/MachO/virtual_section.yaml | 8 +- llvm/tools/obj2yaml/macho2yaml.cpp | 108 ++- 10 files changed, 2744 insertions(+), 41 deletions(-) create mode 100644 llvm/test/ObjectYAML/MachO/relocations_arm64.yaml create mode 100644 llvm/test/ObjectYAML/MachO/relocations_armv7.yaml create mode 100644 llvm/test/ObjectYAML/MachO/relocations_empty.yaml create mode 100644 llvm/test/ObjectYAML/MachO/relocations_ppc_big_endian.yaml create mode 100644 llvm/test/ObjectYAML/MachO/relocations_x86_64.yaml diff --git a/llvm/include/llvm/ObjectYAML/MachOYAML.h b/llvm/include/llvm/ObjectYAML/MachOYAML.h index 327c3b9f892b..fb6780b6d0ed 100644 --- a/llvm/include/llvm/ObjectYAML/MachOYAML.h +++ b/llvm/include/llvm/ObjectYAML/MachOYAML.h @@ -27,6 +27,20 @@ namespace llvm { namespace MachOYAML { +struct Relocation { + // Offset in the section to what is being relocated. + llvm::yaml::Hex32 address; + // Symbol index if r_extern == 1 else section index. + uint32_t symbolnum; + bool is_pcrel; + // Real length = 2 ^ length. + uint8_t length; + bool is_extern; + uint8_t type; + bool is_scattered; + int32_t value; +}; + struct Section { char sectname[16]; char segname[16]; @@ -41,6 +55,7 @@ struct Section { llvm::yaml::Hex32 reserved2; llvm::yaml::Hex32 reserved3; Optional content; + std::vector relocations; }; struct FileHeader { @@ -143,6 +158,7 @@ struct UniversalBinary { } // end namespace llvm LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::MachOYAML::LoadCommand) +LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::MachOYAML::Relocation) LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::MachOYAML::Section) LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::MachOYAML::RebaseOpcode) LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::MachOYAML::BindOpcode) @@ -198,6 +214,10 @@ template <> struct MappingTraits { static void mapping(IO &IO, MachOYAML::ExportEntry &ExportEntry); }; +template <> struct MappingTraits { + static void mapping(IO &IO, MachOYAML::Relocation &R); +}; + template <> struct MappingTraits { static void mapping(IO &IO, MachOYAML::Section &Section); static StringRef validate(IO &io, MachOYAML::Section &Section); diff --git a/llvm/lib/ObjectYAML/MachOEmitter.cpp b/llvm/lib/ObjectYAML/MachOEmitter.cpp index bda4aed885b4..3cf6dc067e70 100644 --- a/llvm/lib/ObjectYAML/MachOEmitter.cpp +++ b/llvm/lib/ObjectYAML/MachOEmitter.cpp @@ -39,6 +39,7 @@ private: void writeHeader(raw_ostream &OS); void writeLoadCommands(raw_ostream &OS); void writeSectionData(raw_ostream &OS); + void writeRelocations(raw_ostream &OS); void writeLinkEditData(raw_ostream &OS); void writeBindOpcodes(raw_ostream &OS, @@ -58,8 +59,11 @@ private: MachOYAML::Object &Obj; bool is64Bit; uint64_t fileStart; - MachO::mach_header_64 Header; + + // Old PPC Object Files didn't have __LINKEDIT segments, the data was just + // stuck at the end of the file. + bool FoundLinkEditSeg = false; }; void MachOWriter::writeMachO(raw_ostream &OS) { @@ -67,6 +71,9 @@ void MachOWriter::writeMachO(raw_ostream &OS) { writeHeader(OS); writeLoadCommands(OS); writeSectionData(OS); + writeRelocations(OS); + if (!FoundLinkEditSeg) + writeLinkEditData(OS); } void MachOWriter::writeHeader(raw_ostream &OS) { @@ -255,7 +262,6 @@ void MachOWriter::writeLoadCommands(raw_ostream &OS) { } void MachOWriter::writeSectionData(raw_ostream &OS) { - bool FoundLinkEditSeg = false; for (auto &LC : Obj.LoadCommands) { switch (LC.Data.load_command_data.cmd) { case MachO::LC_SEGMENT: @@ -315,10 +321,60 @@ void MachOWriter::writeSectionData(raw_ostream &OS) { break; } } - // Old PPC Object Files didn't have __LINKEDIT segments, the data was just - // stuck at the end of the file. - if (!FoundLinkEditSeg) - writeLinkEditData(OS); +} + +// The implementation of makeRelocationInfo and makeScatteredRelocationInfo is +// consistent with how libObject parses MachO binary files. For the reference +// see getStruct, getRelocation, getPlainRelocationPCRel, +// getPlainRelocationLength and related methods in MachOObjectFile.cpp +static MachO::any_relocation_info +makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { + assert(!R.is_scattered && "non-scattered relocation expected"); + MachO::any_relocation_info MRE; + MRE.r_word0 = R.address; + if (IsLE) + MRE.r_word1 = ((unsigned)R.symbolnum << 0) | ((unsigned)R.is_pcrel << 24) | + ((unsigned)R.length << 25) | ((unsigned)R.is_extern << 27) | + ((unsigned)R.type << 28); + else + MRE.r_word1 = ((unsigned)R.symbolnum << 8) | ((unsigned)R.is_pcrel << 7) | + ((unsigned)R.length << 5) | ((unsigned)R.is_extern << 4) | + ((unsigned)R.type << 0); + return MRE; +} + +static MachO::any_relocation_info +makeScatteredRelocationInfo(const MachOYAML::Relocation &R) { + assert(R.is_scattered && "scattered relocation expected"); + MachO::any_relocation_info MRE; + MRE.r_word0 = (((unsigned)R.address << 0) | ((unsigned)R.type << 24) | + ((unsigned)R.length << 28) | ((unsigned)R.is_pcrel << 30) | + MachO::R_SCATTERED); + MRE.r_word1 = R.value; + return MRE; +} + +void MachOWriter::writeRelocations(raw_ostream &OS) { + for (const MachOYAML::LoadCommand &LC : Obj.LoadCommands) { + switch (LC.Data.load_command_data.cmd) { + case MachO::LC_SEGMENT: + case MachO::LC_SEGMENT_64: + for (const MachOYAML::Section &Sec : LC.Sections) { + if (Sec.relocations.empty()) + continue; + ZeroToOffset(OS, Sec.reloff); + for (const MachOYAML::Relocation &R : Sec.relocations) { + MachO::any_relocation_info MRE = + R.is_scattered ? makeScatteredRelocationInfo(R) + : makeRelocationInfo(R, Obj.IsLittleEndian); + if (Obj.IsLittleEndian != sys::IsLittleEndianHost) + MachO::swapStruct(MRE); + OS.write(reinterpret_cast(&MRE), + sizeof(MachO::any_relocation_info)); + } + } + } + } } void MachOWriter::writeBindOpcodes( diff --git a/llvm/lib/ObjectYAML/MachOYAML.cpp b/llvm/lib/ObjectYAML/MachOYAML.cpp index 0f7cd1e1495c..a5341383e8a8 100644 --- a/llvm/lib/ObjectYAML/MachOYAML.cpp +++ b/llvm/lib/ObjectYAML/MachOYAML.cpp @@ -273,6 +273,18 @@ void MappingTraits::mapping( IO.mapRequired("export_size", LoadCommand.export_size); } +void MappingTraits::mapping( + IO &IO, MachOYAML::Relocation &Relocation) { + IO.mapRequired("address", Relocation.address); + IO.mapRequired("symbolnum", Relocation.symbolnum); + IO.mapRequired("pcrel", Relocation.is_pcrel); + IO.mapRequired("length", Relocation.length); + IO.mapRequired("extern", Relocation.is_extern); + IO.mapRequired("type", Relocation.type); + IO.mapRequired("scattered", Relocation.is_scattered); + IO.mapRequired("value", Relocation.value); +} + void MappingTraits::mapping(IO &IO, MachOYAML::Section &Section) { IO.mapRequired("sectname", Section.sectname); @@ -288,6 +300,7 @@ void MappingTraits::mapping(IO &IO, IO.mapRequired("reserved2", Section.reserved2); IO.mapOptional("reserved3", Section.reserved3); IO.mapOptional("content", Section.content); + IO.mapOptional("relocations", Section.relocations); } StringRef diff --git a/llvm/test/ObjectYAML/MachO/relocations_arm64.yaml b/llvm/test/ObjectYAML/MachO/relocations_arm64.yaml new file mode 100644 index 000000000000..208b26fa3246 --- /dev/null +++ b/llvm/test/ObjectYAML/MachO/relocations_arm64.yaml @@ -0,0 +1,590 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --macho --reloc %t | FileCheck %s --check-prefix=OBJDUMP-VERIFY + +# OBJDUMP-VERIFY: Relocation information (__TEXT,__text) 4 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000018 False long True PAGOF12 False _w +# OBJDUMP-VERIFY-NEXT: 00000014 True long True PAGE21 False _w +# OBJDUMP-VERIFY-NEXT: 0000000c False long True PAGOF12 False _z +# OBJDUMP-VERIFY-NEXT: 00000008 True long True PAGE21 False _z +# OBJDUMP-VERIFY-NEXT: Relocation information (__TEXT,__StaticInit) 7 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 0000002c True long True BR26 False ___cxx_global_var_init +# OBJDUMP-VERIFY-NEXT: 00000018 False long True PAGOF12 False _w +# OBJDUMP-VERIFY-NEXT: 00000014 True long True PAGE21 False _w +# OBJDUMP-VERIFY-NEXT: 0000000c False long True PAGOF12 False _y +# OBJDUMP-VERIFY-NEXT: 00000008 True long True PAGE21 False _y +# OBJDUMP-VERIFY-NEXT: 00000004 False long True PAGOF12 False _x +# OBJDUMP-VERIFY-NEXT: 00000000 True long True PAGE21 False _x +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__data) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000008 False ?( 3) True UNSIGND False _x +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__mod_init_func) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000000 False ?( 3) True UNSIGND False __GLOBAL__sub_I_main.cpp +# OBJDUMP-VERIFY-NEXT: Relocation information (__LD,__compact_unwind) 3 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000040 False ?( 3) False UNSIGND False 2 (__TEXT,__StaticInit) +# OBJDUMP-VERIFY-NEXT: 00000020 False ?( 3) False UNSIGND False 1 (__TEXT,__text) +# OBJDUMP-VERIFY-NEXT: 00000000 False ?( 3) False UNSIGND False 2 (__TEXT,__StaticInit) + +# RUN: obj2yaml %t | FileCheck %s +# CHECK: Sections: +# CHECK-NEXT: - sectname: __text +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000000 +# CHECK-NEXT: size: 48 +# CHECK-NEXT: offset: 0x000002C0 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x000003A0 +# CHECK-NEXT: nreloc: 4 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000018 +# CHECK-NEXT: symbolnum: 9 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 4 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000014 +# CHECK-NEXT: symbolnum: 9 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000000C +# CHECK-NEXT: symbolnum: 12 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 4 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 12 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __StaticInit +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000030 +# CHECK-NEXT: size: 56 +# CHECK-NEXT: offset: 0x000002F0 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x000003C0 +# CHECK-NEXT: nreloc: 7 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x0000002C +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 2 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000018 +# CHECK-NEXT: symbolnum: 9 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 4 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000014 +# CHECK-NEXT: symbolnum: 9 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000000C +# CHECK-NEXT: symbolnum: 11 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 4 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 11 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000004 +# CHECK-NEXT: symbolnum: 10 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 4 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 10 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __data +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000068 +# CHECK-NEXT: size: 16 +# CHECK-NEXT: offset: 0x00000328 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x000003F8 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 10 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __common +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x00000000000000E0 +# CHECK-NEXT: size: 8 +# CHECK-NEXT: offset: 0x00000000 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x00000001 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: - sectname: __mod_init_func +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000078 +# CHECK-NEXT: size: 8 +# CHECK-NEXT: offset: 0x00000338 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000400 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000009 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 3 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __compact_unwind +# CHECK-NEXT: segname: __LD +# CHECK-NEXT: addr: 0x0000000000000080 +# CHECK-NEXT: size: 96 +# CHECK-NEXT: offset: 0x00000340 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000408 +# CHECK-NEXT: nreloc: 3 +# CHECK-NEXT: flags: 0x02000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000040 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000020 +# CHECK-NEXT: symbolnum: 1 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x0100000C + cpusubtype: 0x00000000 + filetype: 0x00000001 + ncmds: 4 + sizeofcmds: 672 + flags: 0x00002000 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 552 + segname: '' + vmaddr: 0 + vmsize: 232 + fileoff: 704 + filesize: 224 + maxprot: 7 + initprot: 7 + nsects: 6 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000000 + size: 48 + offset: 0x000002C0 + align: 2 + reloff: 0x000003A0 + nreloc: 4 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: FF4300D1FF0F00B90800009008010091080140F90900009029010091290140F90801098BE00308AAFF430091C0035FD6 + relocations: + - address: 0x00000018 + symbolnum: 9 + pcrel: false + length: 2 + extern: true + type: 4 + scattered: false + value: 0 + - address: 0x00000014 + symbolnum: 9 + pcrel: true + length: 2 + extern: true + type: 3 + scattered: false + value: 0 + - address: 0x0000000C + symbolnum: 12 + pcrel: false + length: 2 + extern: true + type: 4 + scattered: false + value: 0 + - address: 0x00000008 + symbolnum: 12 + pcrel: true + length: 2 + extern: true + type: 3 + scattered: false + value: 0 + - sectname: __StaticInit + segname: __TEXT + addr: 0x0000000000000030 + size: 56 + offset: 0x000002F0 + align: 2 + reloff: 0x000003C0 + nreloc: 7 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 08000090080100910900009029010091080109EB0900009029010091280100F9C0035FD6FD7BBFA9FD03009100000094FD7BC1A8C0035FD6 + relocations: + - address: 0x0000002C + symbolnum: 2 + pcrel: true + length: 2 + extern: true + type: 2 + scattered: false + value: 0 + - address: 0x00000018 + symbolnum: 9 + pcrel: false + length: 2 + extern: true + type: 4 + scattered: false + value: 0 + - address: 0x00000014 + symbolnum: 9 + pcrel: true + length: 2 + extern: true + type: 3 + scattered: false + value: 0 + - address: 0x0000000C + symbolnum: 11 + pcrel: false + length: 2 + extern: true + type: 4 + scattered: false + value: 0 + - address: 0x00000008 + symbolnum: 11 + pcrel: true + length: 2 + extern: true + type: 3 + scattered: false + value: 0 + - address: 0x00000004 + symbolnum: 10 + pcrel: false + length: 2 + extern: true + type: 4 + scattered: false + value: 0 + - address: 0x00000000 + symbolnum: 10 + pcrel: true + length: 2 + extern: true + type: 3 + scattered: false + value: 0 + - sectname: __data + segname: __DATA + addr: 0x0000000000000068 + size: 16 + offset: 0x00000328 + align: 3 + reloff: 0x000003F8 + nreloc: 1 + flags: 0x00000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '01000000020000000000000000000000' + relocations: + - address: 0x00000008 + symbolnum: 10 + pcrel: false + length: 3 + extern: true + type: 0 + scattered: false + value: 0 + - sectname: __common + segname: __DATA + addr: 0x00000000000000E0 + size: 8 + offset: 0x00000000 + align: 3 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000001 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + - sectname: __mod_init_func + segname: __DATA + addr: 0x0000000000000078 + size: 8 + offset: 0x00000338 + align: 3 + reloff: 0x00000400 + nreloc: 1 + flags: 0x00000009 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '0000000000000000' + relocations: + - address: 0x00000000 + symbolnum: 3 + pcrel: false + length: 3 + extern: true + type: 0 + scattered: false + value: 0 + - sectname: __compact_unwind + segname: __LD + addr: 0x0000000000000080 + size: 96 + offset: 0x00000340 + align: 3 + reloff: 0x00000408 + nreloc: 3 + flags: 0x02000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '300000000000000024000000000000020000000000000000000000000000000000000000000000003000000000100002000000000000000000000000000000005400000000000000140000000000000400000000000000000000000000000000' + relocations: + - address: 0x00000040 + symbolnum: 2 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - address: 0x00000020 + symbolnum: 1 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - address: 0x00000000 + symbolnum: 2 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - cmd: LC_VERSION_MIN_IPHONEOS + cmdsize: 16 + version: 655360 + sdk: 0 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 1056 + nsyms: 13 + stroff: 1264 + strsize: 104 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 8 + iextdefsym: 8 + nextdefsym: 5 + iundefsym: 13 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 +LinkEditData: + NameList: + - n_strx: 97 + n_type: 0x0E + n_sect: 1 + n_desc: 0 + n_value: 0 + - n_strx: 91 + n_type: 0x0E + n_sect: 2 + n_desc: 0 + n_value: 48 + - n_strx: 13 + n_type: 0x0E + n_sect: 2 + n_desc: 0 + n_value: 48 + - n_strx: 36 + n_type: 0x0E + n_sect: 2 + n_desc: 0 + n_value: 84 + - n_strx: 85 + n_type: 0x0E + n_sect: 3 + n_desc: 0 + n_value: 104 + - n_strx: 79 + n_type: 0x0E + n_sect: 4 + n_desc: 0 + n_value: 224 + - n_strx: 73 + n_type: 0x0E + n_sect: 5 + n_desc: 0 + n_value: 120 + - n_strx: 67 + n_type: 0x0E + n_sect: 6 + n_desc: 0 + n_value: 128 + - n_strx: 61 + n_type: 0x0F + n_sect: 1 + n_desc: 0 + n_value: 0 + - n_strx: 10 + n_type: 0x0F + n_sect: 4 + n_desc: 0 + n_value: 224 + - n_strx: 7 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 104 + - n_strx: 4 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 108 + - n_strx: 1 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 112 + StringTable: + - '' + - _z + - _y + - _x + - _w + - ___cxx_global_var_init + - __GLOBAL__sub_I_main.cpp + - _main + - ltmp5 + - ltmp4 + - ltmp3 + - ltmp2 + - ltmp1 + - ltmp0 + - '' +... diff --git a/llvm/test/ObjectYAML/MachO/relocations_armv7.yaml b/llvm/test/ObjectYAML/MachO/relocations_armv7.yaml new file mode 100644 index 000000000000..f1c2842e7cd5 --- /dev/null +++ b/llvm/test/ObjectYAML/MachO/relocations_armv7.yaml @@ -0,0 +1,642 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --macho --reloc %t | FileCheck %s --check-prefix=OBJDUMP-VERIFY + +# OBJDUMP-VERIFY: Relocation information (__TEXT,__text) 8 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000016 False hi/thm n/a HALFDIF True 0x00000064 +# OBJDUMP-VERIFY-NEXT: False hi/thm n/a PAIR True 0x0000001a half = 0x0046 +# OBJDUMP-VERIFY-NEXT: 00000012 False lo/arm n/a HALFDIF True 0x00000064 +# OBJDUMP-VERIFY-NEXT: False lo/arm n/a PAIR True 0x0000001a half = 0x0000 +# OBJDUMP-VERIFY-NEXT: 0000000a False hi/thm n/a HALFDIF True 0x0000005c +# OBJDUMP-VERIFY-NEXT: False hi/thm n/a PAIR True 0x0000000e half = 0x004a +# OBJDUMP-VERIFY-NEXT: 00000006 False lo/arm n/a HALFDIF True 0x0000005c +# OBJDUMP-VERIFY-NEXT: False lo/arm n/a PAIR True 0x0000000e half = 0x0000 +# OBJDUMP-VERIFY-NEXT: Relocation information (__TEXT,__StaticInit) 13 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000028 True long False T_BR22 False 2 (__TEXT,__StaticInit) +# OBJDUMP-VERIFY-NEXT: 0000001a False hi/thm n/a HALFDIF True 0x00000064 +# OBJDUMP-VERIFY-NEXT: False hi/thm n/a PAIR True 0x00000042 half = 0x001e +# OBJDUMP-VERIFY-NEXT: 00000016 False lo/arm n/a HALFDIF True 0x00000064 +# OBJDUMP-VERIFY-NEXT: False lo/arm n/a PAIR True 0x00000042 half = 0x0000 +# OBJDUMP-VERIFY-NEXT: 0000000e False hi/thm n/a HALFDIF True 0x00000054 +# OBJDUMP-VERIFY-NEXT: False hi/thm n/a PAIR True 0x00000036 half = 0x001a +# OBJDUMP-VERIFY-NEXT: 0000000a False lo/arm n/a HALFDIF True 0x00000054 +# OBJDUMP-VERIFY-NEXT: False lo/arm n/a PAIR True 0x00000036 half = 0x0000 +# OBJDUMP-VERIFY-NEXT: 00000004 False hi/thm n/a HALFDIF True 0x00000058 +# OBJDUMP-VERIFY-NEXT: False hi/thm n/a PAIR True 0x0000002c half = 0x0028 +# OBJDUMP-VERIFY-NEXT: 00000000 False lo/arm n/a HALFDIF True 0x00000058 +# OBJDUMP-VERIFY-NEXT: False lo/arm n/a PAIR True 0x0000002c half = 0x0000 +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__data) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000008 False long False VANILLA False 3 (__DATA,__data) +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__mod_init_func) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000000 False long False VANILLA False 2 (__TEXT,__StaticInit) + +# RUN: obj2yaml %t | FileCheck %s +# CHECK: Sections: +# CHECK-NEXT: - sectname: __text +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000000 +# CHECK-NEXT: size: 36 +# CHECK-NEXT: offset: 0x00000220 +# CHECK-NEXT: align: 1 +# CHECK-NEXT: reloff: 0x00000284 +# CHECK-NEXT: nreloc: 8 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000016 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 100 +# CHECK-NEXT: - address: 0x00000046 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 26 +# CHECK-NEXT: - address: 0x00000012 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 100 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 26 +# CHECK-NEXT: - address: 0x0000000A +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 92 +# CHECK-NEXT: - address: 0x0000004A +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 14 +# CHECK-NEXT: - address: 0x00000006 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 92 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 14 +# CHECK-NEXT: - sectname: __StaticInit +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000024 +# CHECK-NEXT: size: 46 +# CHECK-NEXT: offset: 0x00000244 +# CHECK-NEXT: align: 1 +# CHECK-NEXT: reloff: 0x000002C4 +# CHECK-NEXT: nreloc: 13 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000028 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 6 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000001A +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 100 +# CHECK-NEXT: - address: 0x0000001E +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 66 +# CHECK-NEXT: - address: 0x00000016 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 100 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 66 +# CHECK-NEXT: - address: 0x0000000E +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 84 +# CHECK-NEXT: - address: 0x0000001A +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 54 +# CHECK-NEXT: - address: 0x0000000A +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 84 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 54 +# CHECK-NEXT: - address: 0x00000004 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 88 +# CHECK-NEXT: - address: 0x00000028 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 44 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 9 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 88 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 44 +# CHECK-NEXT: - sectname: __data +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000054 +# CHECK-NEXT: size: 12 +# CHECK-NEXT: offset: 0x00000274 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x0000032C +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 3 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __common +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000064 +# CHECK-NEXT: size: 4 +# CHECK-NEXT: offset: 0x00000000 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x00000001 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: - sectname: __mod_init_func +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000060 +# CHECK-NEXT: size: 4 +# CHECK-NEXT: offset: 0x00000280 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x00000334 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000009 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: '48000000' +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 + +--- !mach-o +FileHeader: + magic: 0xFEEDFACE + cputype: 0x0000000C + cpusubtype: 0x00000009 + filetype: 0x00000001 + ncmds: 4 + sizeofcmds: 516 + flags: 0x00002000 +LoadCommands: + - cmd: LC_SEGMENT + cmdsize: 396 + segname: '' + vmaddr: 0 + vmsize: 104 + fileoff: 544 + filesize: 100 + maxprot: 7 + initprot: 7 + nsects: 5 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000000 + size: 36 + offset: 0x00000220 + align: 1 + reloff: 0x00000284 + nreloc: 8 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 81B00020009040F24A00C0F200007844006840F24601C0F2000179440968084401B07047 + relocations: + - address: 0x00000016 + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 9 + scattered: true + value: 100 + - address: 0x00000046 + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 1 + scattered: true + value: 26 + - address: 0x00000012 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 9 + scattered: true + value: 100 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 26 + - address: 0x0000000A + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 9 + scattered: true + value: 92 + - address: 0x0000004A + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 1 + scattered: true + value: 14 + - address: 0x00000006 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 9 + scattered: true + value: 92 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 14 + - sectname: __StaticInit + segname: __TEXT + addr: 0x0000000000000024 + size: 46 + offset: 0x00000244 + align: 1 + reloff: 0x000002C4 + nreloc: 13 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 40F22800C0F20000784440F21A01C0F200017944081A40F21E01C0F2000179440860704780B56F46FFF7EAFF80BD + relocations: + - address: 0x00000028 + symbolnum: 2 + pcrel: true + length: 2 + extern: false + type: 6 + scattered: false + value: 0 + - address: 0x0000001A + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 9 + scattered: true + value: 100 + - address: 0x0000001E + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 1 + scattered: true + value: 66 + - address: 0x00000016 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 9 + scattered: true + value: 100 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 66 + - address: 0x0000000E + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 9 + scattered: true + value: 84 + - address: 0x0000001A + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 1 + scattered: true + value: 54 + - address: 0x0000000A + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 9 + scattered: true + value: 84 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 54 + - address: 0x00000004 + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 9 + scattered: true + value: 88 + - address: 0x00000028 + symbolnum: 0 + pcrel: false + length: 3 + extern: false + type: 1 + scattered: true + value: 44 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 9 + scattered: true + value: 88 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 44 + - sectname: __data + segname: __DATA + addr: 0x0000000000000054 + size: 12 + offset: 0x00000274 + align: 2 + reloff: 0x0000032C + nreloc: 1 + flags: 0x00000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '010000000200000054000000' + relocations: + - address: 0x00000008 + symbolnum: 3 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: false + value: 0 + - sectname: __common + segname: __DATA + addr: 0x0000000000000064 + size: 4 + offset: 0x00000000 + align: 2 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000001 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + - sectname: __mod_init_func + segname: __DATA + addr: 0x0000000000000060 + size: 4 + offset: 0x00000280 + align: 2 + reloff: 0x00000334 + nreloc: 1 + flags: 0x00000009 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '48000000' + relocations: + - address: 0x00000000 + symbolnum: 2 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: false + value: 0 + - cmd: LC_VERSION_MIN_IPHONEOS + cmdsize: 16 + version: 589824 + sdk: 0 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 828 + nsyms: 7 + stroff: 912 + strsize: 68 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 2 + iextdefsym: 2 + nextdefsym: 5 + iundefsym: 7 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 +LinkEditData: + NameList: + - n_strx: 13 + n_type: 0x0E + n_sect: 2 + n_desc: 8 + n_value: 36 + - n_strx: 36 + n_type: 0x0E + n_sect: 2 + n_desc: 8 + n_value: 72 + - n_strx: 61 + n_type: 0x0F + n_sect: 1 + n_desc: 8 + n_value: 0 + - n_strx: 10 + n_type: 0x0F + n_sect: 4 + n_desc: 0 + n_value: 100 + - n_strx: 7 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 84 + - n_strx: 4 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 88 + - n_strx: 1 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 92 + StringTable: + - '' + - _z + - _y + - _x + - _w + - ___cxx_global_var_init + - __GLOBAL__sub_I_main.cpp + - _main + - '' +... diff --git a/llvm/test/ObjectYAML/MachO/relocations_empty.yaml b/llvm/test/ObjectYAML/MachO/relocations_empty.yaml new file mode 100644 index 000000000000..8a6a031da479 --- /dev/null +++ b/llvm/test/ObjectYAML/MachO/relocations_empty.yaml @@ -0,0 +1,65 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --macho --reloc %t | FileCheck %s --check-prefix=OBJDUMP-VERIFY + +# OBJDUMP-VERIFY-NOT: Relocation information + +# RUN: obj2yaml %t | FileCheck %s + +# CHECK: Sections: +# CHECK-NEXT: - sectname: __text +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000000 +# CHECK-NEXT: size: 0 +# CHECK-NEXT: offset: 0x000000C8 +# CHECK-NEXT: align: 0 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x80000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: '' +# CHECK-NOT: relocations: + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x01000007 + cpusubtype: 0x00000003 + filetype: 0x00000001 + ncmds: 2 + sizeofcmds: 168 + flags: 0x00002000 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: '' + vmaddr: 0 + vmsize: 0 + fileoff: 200 + filesize: 0 + maxprot: 7 + initprot: 7 + nsects: 1 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000000 + size: 0 + offset: 0x000000C8 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x80000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '' + relocations: [] + - cmd: LC_VERSION_MIN_MACOSX + cmdsize: 16 + version: 658944 + sdk: 0 +... diff --git a/llvm/test/ObjectYAML/MachO/relocations_ppc_big_endian.yaml b/llvm/test/ObjectYAML/MachO/relocations_ppc_big_endian.yaml new file mode 100644 index 000000000000..bfeed67a59e2 --- /dev/null +++ b/llvm/test/ObjectYAML/MachO/relocations_ppc_big_endian.yaml @@ -0,0 +1,777 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --macho --reloc %t | FileCheck %s --check-prefix=OBJDUMP-VERIFY + +# OBJDUMP-VERIFY: Relocation information (__TEXT,__text) 8 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000030 False long n/a 11 True 0x00000144 +# OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000018 +# OBJDUMP-VERIFY-NEXT: 0000002c False long n/a 12 True 0x00000144 +# OBJDUMP-VERIFY-NEXT: 0000012c False long n/a 1 True 0x00000018 +# OBJDUMP-VERIFY-NEXT: 00000028 False long n/a 11 True 0x000000d4 +# OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000018 +# OBJDUMP-VERIFY-NEXT: 00000024 False long n/a 12 True 0x000000d4 +# OBJDUMP-VERIFY-NEXT: 000000bc False long n/a 1 True 0x00000018 +# OBJDUMP-VERIFY-NEXT: Relocation information (__TEXT,__StaticInit) 13 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000064 True long False 3 False 4 (__TEXT,__StaticInit) +# OBJDUMP-VERIFY-NEXT: 00000034 False long n/a 11 True 0x00000144 +# OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: 00000030 False long n/a 12 True 0x00000144 +# OBJDUMP-VERIFY-NEXT: 000000dc False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: 00000028 False long n/a 11 True 0x000000d0 +# OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: 00000024 False long n/a 12 True 0x000000d0 +# OBJDUMP-VERIFY-NEXT: 00000068 False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: 00000020 False long n/a 11 True 0x000000cc +# OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: 0000001c False long n/a 12 True 0x000000cc +# OBJDUMP-VERIFY-NEXT: 00000064 False long n/a 1 True 0x00000068 +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__data) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000008 False long False 0 False 5 (__DATA,__data) +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__mod_init_func) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000000 False long False 0 False 4 (__TEXT,__StaticInit) +# OBJDUMP-VERIFY-NEXT: Relocation information (__TEXT,__eh_frame) 3 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000054 False long n/a 0 True 0x000000a0 +# OBJDUMP-VERIFY-NEXT: 00000038 False long n/a 0 True 0x00000000 +# OBJDUMP-VERIFY-NEXT: 0000001c False long n/a 0 True 0x00000050 + +# RUN: obj2yaml %t | FileCheck %s + +# CHECK: Sections: +# CHECK-NEXT: - sectname: __text +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000000 +# CHECK-NEXT: size: 76 +# CHECK-NEXT: offset: 0x000002EC +# CHECK-NEXT: align: 4 +# CHECK-NEXT: reloff: 0x00000430 +# CHECK-NEXT: nreloc: 8 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000030 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 11 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 324 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 24 +# CHECK-NEXT: - address: 0x0000002C +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 12 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 324 +# CHECK-NEXT: - address: 0x0000012C +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 24 +# CHECK-NEXT: - address: 0x00000028 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 11 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 212 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 24 +# CHECK-NEXT: - address: 0x00000024 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 12 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 212 +# CHECK-NEXT: - address: 0x000000BC +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 24 +# CHECK-NEXT: - sectname: __textcoal_nt +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x000000000000004C +# CHECK-NEXT: size: 0 +# CHECK-NEXT: offset: 0x00000338 +# CHECK-NEXT: align: 0 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x8000000B +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: '' +# CHECK-NEXT: - sectname: __picsymbolstub1 +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x000000000000004C +# CHECK-NEXT: size: 0 +# CHECK-NEXT: offset: 0x00000338 +# CHECK-NEXT: align: 0 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x80000008 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000020 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: '' +# CHECK-NEXT: - sectname: __StaticInit +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000050 +# CHECK-NEXT: size: 124 +# CHECK-NEXT: offset: 0x0000033C +# CHECK-NEXT: align: 4 +# CHECK-NEXT: reloff: 0x00000470 +# CHECK-NEXT: nreloc: 13 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000064 +# CHECK-NEXT: symbolnum: 4 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 3 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000034 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 11 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 324 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - address: 0x00000030 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 12 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 324 +# CHECK-NEXT: - address: 0x000000DC +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - address: 0x00000028 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 11 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 208 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - address: 0x00000024 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 12 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 208 +# CHECK-NEXT: - address: 0x00000068 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - address: 0x00000020 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 11 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 204 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - address: 0x0000001C +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 12 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 204 +# CHECK-NEXT: - address: 0x00000064 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 104 +# CHECK-NEXT: - sectname: __data +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x00000000000000CC +# CHECK-NEXT: size: 12 +# CHECK-NEXT: offset: 0x000003B8 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x000004D8 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 5 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __common +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000144 +# CHECK-NEXT: size: 4 +# CHECK-NEXT: offset: 0x00000000 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x00000001 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: - sectname: __mod_init_func +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x00000000000000D8 +# CHECK-NEXT: size: 4 +# CHECK-NEXT: offset: 0x000003C4 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x000004E0 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000009 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: 000000A0 +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 4 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __eh_frame +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x00000000000000DC +# CHECK-NEXT: size: 104 +# CHECK-NEXT: offset: 0x000003C8 +# CHECK-NEXT: align: 2 +# CHECK-NEXT: reloff: 0x000004E8 +# CHECK-NEXT: nreloc: 3 +# CHECK-NEXT: flags: 0x6800000B +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000054 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 160 +# CHECK-NEXT: - address: 0x00000038 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000001C +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: true +# CHECK-NEXT: value: 80 + +--- !mach-o +IsLittleEndian: false +FileHeader: + magic: 0xFEEDFACE + cputype: 0x00000012 + cpusubtype: 0x00000000 + filetype: 0x00000001 + ncmds: 4 + sizeofcmds: 720 + flags: 0x00002000 +LoadCommands: + - cmd: LC_SEGMENT + cmdsize: 600 + segname: '' + vmaddr: 0 + vmsize: 328 + fileoff: 748 + filesize: 324 + maxprot: 7 + initprot: 7 + nsects: 8 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000000 + size: 76 + offset: 0x000002EC + align: 4 + reloff: 0x00000430 + nreloc: 8 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 7C0802A693E1FFFC900100089421FFE07C3F0B78480000057C4802A638600000907F00183C620000806300BC3C4200008042012C7C631214382100208001000883E1FFFC7C0803A64E800020 + relocations: + - address: 0x00000030 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 11 + scattered: true + value: 324 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 24 + - address: 0x0000002C + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 12 + scattered: true + value: 324 + - address: 0x0000012C + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 24 + - address: 0x00000028 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 11 + scattered: true + value: 212 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 24 + - address: 0x00000024 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 12 + scattered: true + value: 212 + - address: 0x000000BC + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 24 + - sectname: __textcoal_nt + segname: __TEXT + addr: 0x000000000000004C + size: 0 + offset: 0x00000338 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x8000000B + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '' + - sectname: __picsymbolstub1 + segname: __TEXT + addr: 0x000000000000004C + size: 0 + offset: 0x00000338 + align: 0 + reloff: 0x00000000 + nreloc: 0 + flags: 0x80000008 + reserved1: 0x00000000 + reserved2: 0x00000020 + reserved3: 0x00000000 + content: '' + - sectname: __StaticInit + segname: __TEXT + addr: 0x0000000000000050 + size: 124 + offset: 0x0000033C + align: 4 + reloff: 0x00000470 + nreloc: 13 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 7C0802A693E1FFFC900100089421FFE07C3F0B78480000057C4802A63C620000386300643C820000388400687C6418503C420000906200DC382100208001000883E1FFFC7C0803A64E800020600000007C0802A693E1FFFC900100089421FFC07C3F0B784BFFFF9D382100408001000883E1FFFC7C0803A64E800020 + relocations: + - address: 0x00000064 + symbolnum: 4 + pcrel: true + length: 2 + extern: false + type: 3 + scattered: false + value: 0 + - address: 0x00000034 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 11 + scattered: true + value: 324 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - address: 0x00000030 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 12 + scattered: true + value: 324 + - address: 0x000000DC + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - address: 0x00000028 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 11 + scattered: true + value: 208 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - address: 0x00000024 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 12 + scattered: true + value: 208 + - address: 0x00000068 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - address: 0x00000020 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 11 + scattered: true + value: 204 + - address: 0x00000000 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - address: 0x0000001C + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 12 + scattered: true + value: 204 + - address: 0x00000064 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 1 + scattered: true + value: 104 + - sectname: __data + segname: __DATA + addr: 0x00000000000000CC + size: 12 + offset: 0x000003B8 + align: 2 + reloff: 0x000004D8 + nreloc: 1 + flags: 0x00000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 0000000100000002000000CC + relocations: + - address: 0x00000008 + symbolnum: 5 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: false + value: 0 + - sectname: __common + segname: __DATA + addr: 0x0000000000000144 + size: 4 + offset: 0x00000000 + align: 2 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000001 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + - sectname: __mod_init_func + segname: __DATA + addr: 0x00000000000000D8 + size: 4 + offset: 0x000003C4 + align: 2 + reloff: 0x000004E0 + nreloc: 1 + flags: 0x00000009 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 000000A0 + relocations: + - address: 0x00000000 + symbolnum: 4 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: false + value: 0 + - sectname: __eh_frame + segname: __TEXT + addr: 0x00000000000000DC + size: 104 + offset: 0x000003C8 + align: 2 + reloff: 0x000004E8 + nreloc: 3 + flags: 0x6800000B + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 0000001000000000017A5200017C4101100C01000000001800000018FFFFFF580000004C00500E209F0111417E440D1F0000001800000034FFFFFEEC0000004C00500E209F0111417E440D1F0000001800000050FFFFFF700000002C00500E409F0111417E440D1F + relocations: + - address: 0x00000054 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: true + value: 160 + - address: 0x00000038 + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: true + value: 0 + - address: 0x0000001C + symbolnum: 0 + pcrel: false + length: 2 + extern: false + type: 0 + scattered: true + value: 80 + - cmd: LC_VERSION_MIN_MACOSX + cmdsize: 16 + version: 656384 + sdk: 0 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 1280 + nsyms: 7 + stroff: 1364 + strsize: 68 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 2 + iextdefsym: 2 + nextdefsym: 5 + iundefsym: 7 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 +LinkEditData: + NameList: + - n_strx: 13 + n_type: 0x0E + n_sect: 4 + n_desc: 0 + n_value: 80 + - n_strx: 36 + n_type: 0x0E + n_sect: 4 + n_desc: 0 + n_value: 160 + - n_strx: 61 + n_type: 0x0F + n_sect: 1 + n_desc: 0 + n_value: 0 + - n_strx: 10 + n_type: 0x0F + n_sect: 6 + n_desc: 0 + n_value: 324 + - n_strx: 7 + n_type: 0x0F + n_sect: 5 + n_desc: 0 + n_value: 204 + - n_strx: 4 + n_type: 0x0F + n_sect: 5 + n_desc: 0 + n_value: 208 + - n_strx: 1 + n_type: 0x0F + n_sect: 5 + n_desc: 0 + n_value: 212 + StringTable: + - '' + - _z + - _y + - _x + - _w + - ___cxx_global_var_init + - __GLOBAL__sub_I_main.cpp + - _main + - '' +... diff --git a/llvm/test/ObjectYAML/MachO/relocations_x86_64.yaml b/llvm/test/ObjectYAML/MachO/relocations_x86_64.yaml new file mode 100644 index 000000000000..9c5ba88d70d5 --- /dev/null +++ b/llvm/test/ObjectYAML/MachO/relocations_x86_64.yaml @@ -0,0 +1,494 @@ +# RUN: yaml2obj %s -o %t +# RUN: llvm-objdump --macho --reloc %t | FileCheck %s --check-prefix=OBJDUMP-VERIFY + +# OBJDUMP-VERIFY: Relocation information (__TEXT,__text) 2 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000015 True long True SIGNED False _w +# OBJDUMP-VERIFY-NEXT: 0000000e True long True SIGNED False _z +# OBJDUMP-VERIFY-NEXT: Relocation information (__TEXT,__StaticInit) 4 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000025 True long True BRANCH False ___cxx_global_var_init +# OBJDUMP-VERIFY-NEXT: 00000018 True long True SIGNED False _w +# OBJDUMP-VERIFY-NEXT: 0000000e True long True SIGNED False _x +# OBJDUMP-VERIFY-NEXT: 00000007 True long True SIGNED False _y +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__data) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000008 False quad True UNSIGND False _x +# OBJDUMP-VERIFY-NEXT: Relocation information (__DATA,__mod_init_func) 1 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000000 False quad True UNSIGND False __GLOBAL__sub_I_main.cpp +# OBJDUMP-VERIFY-NEXT: Relocation information (__LD,__compact_unwind) 3 entries +# OBJDUMP-VERIFY-NEXT: address pcrel length extern type scattered symbolnum/value +# OBJDUMP-VERIFY-NEXT: 00000040 False quad False UNSIGND False 2 (__TEXT,__StaticInit) +# OBJDUMP-VERIFY-NEXT: 00000020 False quad False UNSIGND False 1 (__TEXT,__text) +# OBJDUMP-VERIFY-NEXT: 00000000 False quad False UNSIGND False 2 (__TEXT,__StaticInit) + +# RUN: obj2yaml %t | FileCheck %s +# CHECK: Sections: +# CHECK-NEXT: - sectname: __text +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000000 +# CHECK-NEXT: size: 27 +# CHECK-NEXT: offset: 0x00000310 +# CHECK-NEXT: align: 4 +# CHECK-NEXT: reloff: 0x00000468 +# CHECK-NEXT: nreloc: 2 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000015 +# CHECK-NEXT: symbolnum: 3 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000000E +# CHECK-NEXT: symbolnum: 6 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __StaticInit +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x0000000000000020 +# CHECK-NEXT: size: 43 +# CHECK-NEXT: offset: 0x00000330 +# CHECK-NEXT: align: 4 +# CHECK-NEXT: reloff: 0x00000478 +# CHECK-NEXT: nreloc: 4 +# CHECK-NEXT: flags: 0x80000400 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000025 +# CHECK-NEXT: symbolnum: 0 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 2 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000018 +# CHECK-NEXT: symbolnum: 3 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x0000000E +# CHECK-NEXT: symbolnum: 4 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000007 +# CHECK-NEXT: symbolnum: 5 +# CHECK-NEXT: pcrel: true +# CHECK-NEXT: length: 2 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 1 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __data +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000050 +# CHECK-NEXT: size: 16 +# CHECK-NEXT: offset: 0x00000360 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000498 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: '01000000020000000000000000000000' +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000008 +# CHECK-NEXT: symbolnum: 4 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __common +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000158 +# CHECK-NEXT: size: 8 +# CHECK-NEXT: offset: 0x00000000 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x00000001 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: - sectname: __mod_init_func +# CHECK-NEXT: segname: __DATA +# CHECK-NEXT: addr: 0x0000000000000060 +# CHECK-NEXT: size: 8 +# CHECK-NEXT: offset: 0x00000370 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x000004A0 +# CHECK-NEXT: nreloc: 1 +# CHECK-NEXT: flags: 0x00000009 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 1 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: true +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __compact_unwind +# CHECK-NEXT: segname: __LD +# CHECK-NEXT: addr: 0x0000000000000068 +# CHECK-NEXT: size: 96 +# CHECK-NEXT: offset: 0x00000378 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x000004A8 +# CHECK-NEXT: nreloc: 3 +# CHECK-NEXT: flags: 0x02000000 +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 +# CHECK-NEXT: content: +# CHECK-NEXT: relocations: +# CHECK-NEXT: - address: 0x00000040 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000020 +# CHECK-NEXT: symbolnum: 1 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - address: 0x00000000 +# CHECK-NEXT: symbolnum: 2 +# CHECK-NEXT: pcrel: false +# CHECK-NEXT: length: 3 +# CHECK-NEXT: extern: false +# CHECK-NEXT: type: 0 +# CHECK-NEXT: scattered: false +# CHECK-NEXT: value: 0 +# CHECK-NEXT: - sectname: __eh_frame +# CHECK-NEXT: segname: __TEXT +# CHECK-NEXT: addr: 0x00000000000000C8 +# CHECK-NEXT: size: 144 +# CHECK-NEXT: offset: 0x000003D8 +# CHECK-NEXT: align: 3 +# CHECK-NEXT: reloff: 0x00000000 +# CHECK-NEXT: nreloc: 0 +# CHECK-NEXT: flags: 0x6800000B +# CHECK-NEXT: reserved1: 0x00000000 +# CHECK-NEXT: reserved2: 0x00000000 +# CHECK-NEXT: reserved3: 0x00000000 + +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x01000007 + cpusubtype: 0x00000003 + filetype: 0x00000001 + ncmds: 4 + sizeofcmds: 752 + flags: 0x00002000 + reserved: 0x00000000 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 632 + segname: '' + vmaddr: 0 + vmsize: 352 + fileoff: 784 + filesize: 344 + maxprot: 7 + initprot: 7 + nsects: 7 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0000000000000000 + size: 27 + offset: 0x00000310 + align: 4 + reloff: 0x00000468 + nreloc: 2 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 554889E5C745FC00000000488B0500000000480305000000005DC3 + relocations: + - address: 0x00000015 + symbolnum: 3 + pcrel: true + length: 2 + extern: true + type: 1 + scattered: false + value: 0 + - address: 0x0000000E + symbolnum: 6 + pcrel: true + length: 2 + extern: true + type: 1 + scattered: false + value: 0 + - sectname: __StaticInit + segname: __TEXT + addr: 0x0000000000000020 + size: 43 + offset: 0x00000330 + align: 4 + reloff: 0x00000478 + nreloc: 4 + flags: 0x80000400 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 554889E5488D0500000000488D0D000000004829C148890D000000005DC36690554889E5E8000000005DC3 + relocations: + - address: 0x00000025 + symbolnum: 0 + pcrel: true + length: 2 + extern: true + type: 2 + scattered: false + value: 0 + - address: 0x00000018 + symbolnum: 3 + pcrel: true + length: 2 + extern: true + type: 1 + scattered: false + value: 0 + - address: 0x0000000E + symbolnum: 4 + pcrel: true + length: 2 + extern: true + type: 1 + scattered: false + value: 0 + - address: 0x00000007 + symbolnum: 5 + pcrel: true + length: 2 + extern: true + type: 1 + scattered: false + value: 0 + - sectname: __data + segname: __DATA + addr: 0x0000000000000050 + size: 16 + offset: 0x00000360 + align: 3 + reloff: 0x00000498 + nreloc: 1 + flags: 0x00000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '01000000020000000000000000000000' + relocations: + - address: 0x00000008 + symbolnum: 4 + pcrel: false + length: 3 + extern: true + type: 0 + scattered: false + value: 0 + - sectname: __common + segname: __DATA + addr: 0x0000000000000158 + size: 8 + offset: 0x00000000 + align: 3 + reloff: 0x00000000 + nreloc: 0 + flags: 0x00000001 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + - sectname: __mod_init_func + segname: __DATA + addr: 0x0000000000000060 + size: 8 + offset: 0x00000370 + align: 3 + reloff: 0x000004A0 + nreloc: 1 + flags: 0x00000009 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: '0000000000000000' + relocations: + - address: 0x00000000 + symbolnum: 1 + pcrel: false + length: 3 + extern: true + type: 0 + scattered: false + value: 0 + - sectname: __compact_unwind + segname: __LD + addr: 0x0000000000000068 + size: 96 + offset: 0x00000378 + align: 3 + reloff: 0x000004A8 + nreloc: 3 + flags: 0x02000000 + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 20000000000000001E000000000000010000000000000000000000000000000000000000000000001B000000000000010000000000000000000000000000000040000000000000000B0000000000000100000000000000000000000000000000 + relocations: + - address: 0x00000040 + symbolnum: 2 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - address: 0x00000020 + symbolnum: 1 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - address: 0x00000000 + symbolnum: 2 + pcrel: false + length: 3 + extern: false + type: 0 + scattered: false + value: 0 + - sectname: __eh_frame + segname: __TEXT + addr: 0x00000000000000C8 + size: 144 + offset: 0x000003D8 + align: 3 + reloff: 0x00000000 + nreloc: 0 + flags: 0x6800000B + reserved1: 0x00000000 + reserved2: 0x00000000 + reserved3: 0x00000000 + content: 1400000000000000017A520001781001100C070890010000240000001C00000038FFFFFFFFFFFFFF1E0000000000000000410E108602430D06000000000000002400000044000000F0FEFFFFFFFFFFFF1B0000000000000000410E108602430D0600000000000000240000006C00000008FFFFFFFFFFFFFF0B0000000000000000410E108602430D0600000000000000 + - cmd: LC_VERSION_MIN_MACOSX + cmdsize: 16 + version: 658944 + sdk: 0 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 1216 + nsyms: 7 + stroff: 1328 + strsize: 68 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 2 + iextdefsym: 2 + nextdefsym: 5 + iundefsym: 7 + nundefsym: 0 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 +LinkEditData: + NameList: + - n_strx: 13 + n_type: 0x0E + n_sect: 2 + n_desc: 0 + n_value: 32 + - n_strx: 36 + n_type: 0x0E + n_sect: 2 + n_desc: 0 + n_value: 64 + - n_strx: 61 + n_type: 0x0F + n_sect: 1 + n_desc: 0 + n_value: 0 + - n_strx: 10 + n_type: 0x0F + n_sect: 4 + n_desc: 0 + n_value: 344 + - n_strx: 7 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 80 + - n_strx: 4 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 84 + - n_strx: 1 + n_type: 0x0F + n_sect: 3 + n_desc: 0 + n_value: 88 + StringTable: + - '' + - _z + - _y + - _x + - _w + - ___cxx_global_var_init + - __GLOBAL__sub_I_main.cpp + - _main + - '' +... diff --git a/llvm/test/ObjectYAML/MachO/virtual_section.yaml b/llvm/test/ObjectYAML/MachO/virtual_section.yaml index edc13df122d4..73c7b6baa924 100644 --- a/llvm/test/ObjectYAML/MachO/virtual_section.yaml +++ b/llvm/test/ObjectYAML/MachO/virtual_section.yaml @@ -29,7 +29,7 @@ LoadCommands: offset: 0x000002B0 align: 4 reloff: 0x00000350 - nreloc: 7 + nreloc: 0 flags: 0x80000400 reserved1: 0x00000000 reserved2: 0x00000000 @@ -77,7 +77,7 @@ LoadCommands: offset: 0x000002FC align: 0 reloff: 0x00000388 - nreloc: 2 + nreloc: 0 flags: 0x00000013 reserved1: 0x00000000 reserved2: 0x00000000 @@ -170,7 +170,7 @@ LinkEditData: # CHECK-NEXT: offset: 0x000002B0 # CHECK-NEXT: align: 4 # CHECK-NEXT: reloff: 0x00000350 -# CHECK-NEXT: nreloc: 7 +# CHECK-NEXT: nreloc: 0 # CHECK-NEXT: flags: 0x80000400 # CHECK-NEXT: reserved1: 0x00000000 # CHECK-NEXT: reserved2: 0x00000000 @@ -220,7 +220,7 @@ LinkEditData: # CHECK-NEXT: offset: 0x000002FC # CHECK-NEXT: align: 0 # CHECK-NEXT: reloff: 0x00000388 -# CHECK-NEXT: nreloc: 2 +# CHECK-NEXT: nreloc: 0 # CHECK-NEXT: flags: 0x00000013 # CHECK-NEXT: reserved1: 0x00000000 # CHECK-NEXT: reserved2: 0x00000000 diff --git a/llvm/tools/obj2yaml/macho2yaml.cpp b/llvm/tools/obj2yaml/macho2yaml.cpp index 0ee8814d35ab..6b0db2aa15fa 100644 --- a/llvm/tools/obj2yaml/macho2yaml.cpp +++ b/llvm/tools/obj2yaml/macho2yaml.cpp @@ -21,13 +21,13 @@ using namespace llvm; class MachODumper { template - const char *processLoadCommandData( + Expected processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd); const object::MachOObjectFile &Obj; void dumpHeader(std::unique_ptr &Y); - void dumpLoadCommands(std::unique_ptr &Y); + Error dumpLoadCommands(std::unique_ptr &Y); void dumpLinkEdit(std::unique_ptr &Y); void dumpRebaseOpcodes(std::unique_ptr &Y); void dumpBindOpcodes(std::vector &BindOpcodes, @@ -40,11 +40,13 @@ class MachODumper { std::unique_ptr &Y); template - MachOYAML::Section constructSectionCommon(SectionType Sec); + Expected constructSectionCommon(SectionType Sec, + size_t SecIndex); template - MachOYAML::Section constructSection(SectionType Sec); + Expected constructSection(SectionType Sec, + size_t SecIndex); template - const char * + Expected extractSections(const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd, std::vector &Sections); @@ -59,11 +61,16 @@ public: sizeof(MachO::LCStruct)); \ if (Obj.isLittleEndian() != sys::IsLittleEndianHost) \ MachO::swapStruct(LC.Data.LCStruct##_data); \ - EndPtr = processLoadCommandData(LC, LoadCmd); \ + if (Expected ExpectedEndPtr = \ + processLoadCommandData(LC, LoadCmd)) \ + EndPtr = *ExpectedEndPtr; \ + else \ + return ExpectedEndPtr.takeError(); \ break; template -MachOYAML::Section MachODumper::constructSectionCommon(SectionType Sec) { +Expected +MachODumper::constructSectionCommon(SectionType Sec, size_t SecIndex) { MachOYAML::Section TempSec; memcpy(reinterpret_cast(&TempSec.sectname[0]), &Sec.sectname[0], 16); memcpy(reinterpret_cast(&TempSec.segname[0]), &Sec.segname[0], 16); @@ -80,52 +87,80 @@ MachOYAML::Section MachODumper::constructSectionCommon(SectionType Sec) { if (!MachO::isVirtualSection(Sec.flags & MachO::SECTION_TYPE)) TempSec.content = yaml::BinaryRef(Obj.getSectionContents(Sec.offset, Sec.size)); + + if (Expected SecRef = Obj.getSection(SecIndex)) { + TempSec.relocations.reserve(TempSec.nreloc); + for (const object::RelocationRef &Reloc : SecRef->relocations()) { + const object::DataRefImpl Rel = Reloc.getRawDataRefImpl(); + const MachO::any_relocation_info RE = Obj.getRelocation(Rel); + MachOYAML::Relocation R; + R.address = Obj.getAnyRelocationAddress(RE); + R.is_pcrel = Obj.getAnyRelocationPCRel(RE); + R.length = Obj.getAnyRelocationLength(RE); + R.type = Obj.getAnyRelocationType(RE); + R.is_scattered = Obj.isRelocationScattered(RE); + R.symbolnum = (R.is_scattered ? 0 : Obj.getPlainRelocationSymbolNum(RE)); + R.is_extern = + (R.is_scattered ? false : Obj.getPlainRelocationExternal(RE)); + R.value = (R.is_scattered ? Obj.getScatteredRelocationValue(RE) : 0); + TempSec.relocations.push_back(R); + } + } else { + return SecRef.takeError(); + } return TempSec; } template <> -MachOYAML::Section MachODumper::constructSection(MachO::section Sec) { - MachOYAML::Section TempSec = constructSectionCommon(Sec); - TempSec.reserved3 = 0; +Expected MachODumper::constructSection(MachO::section Sec, + size_t SecIndex) { + Expected TempSec = constructSectionCommon(Sec, SecIndex); + if (TempSec) + TempSec->reserved3 = 0; return TempSec; } template <> -MachOYAML::Section MachODumper::constructSection(MachO::section_64 Sec) { - MachOYAML::Section TempSec = constructSectionCommon(Sec); - TempSec.reserved3 = Sec.reserved3; +Expected +MachODumper::constructSection(MachO::section_64 Sec, size_t SecIndex) { + Expected TempSec = constructSectionCommon(Sec, SecIndex); + if (TempSec) + TempSec->reserved3 = Sec.reserved3; return TempSec; } template -const char *MachODumper::extractSections( +Expected MachODumper::extractSections( const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd, std::vector &Sections) { auto End = LoadCmd.Ptr + LoadCmd.C.cmdsize; const SectionType *Curr = reinterpret_cast(LoadCmd.Ptr + sizeof(SegmentType)); for (; reinterpret_cast(Curr) < End; Curr++) { - if (Obj.isLittleEndian() != sys::IsLittleEndianHost) { - SectionType Sec; - memcpy((void *)&Sec, Curr, sizeof(SectionType)); + SectionType Sec; + memcpy((void *)&Sec, Curr, sizeof(SectionType)); + if (Obj.isLittleEndian() != sys::IsLittleEndianHost) MachO::swapStruct(Sec); - Sections.push_back(constructSection(Sec)); - } else { - Sections.push_back(constructSection(*Curr)); - } + // For MachO section indices start from 1. + if (Expected S = + constructSection(Sec, Sections.size() + 1)) + Sections.push_back(std::move(*S)); + else + return S.takeError(); } return reinterpret_cast(Curr); } template -const char *MachODumper::processLoadCommandData( +Expected MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return LoadCmd.Ptr + sizeof(StructType); } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return extractSections(LoadCmd, @@ -133,7 +168,8 @@ const char *MachODumper::processLoadCommandData( } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return extractSections( @@ -152,28 +188,32 @@ readString(MachOYAML::LoadCommand &LC, } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return readString(LC, LoadCmd); } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return readString(LC, LoadCmd); } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { return readString(LC, LoadCmd); } template <> -const char *MachODumper::processLoadCommandData( +Expected +MachODumper::processLoadCommandData( MachOYAML::LoadCommand &LC, const llvm::object::MachOObjectFile::LoadCommandInfo &LoadCmd) { auto Start = LoadCmd.Ptr + sizeof(MachO::build_version_command); @@ -193,7 +233,8 @@ Expected> MachODumper::dump() { auto Y = std::make_unique(); Y->IsLittleEndian = Obj.isLittleEndian(); dumpHeader(Y); - dumpLoadCommands(Y); + if (Error Err = dumpLoadCommands(Y)) + return std::move(Err); dumpLinkEdit(Y); std::unique_ptr DICtx = DWARFContext::create(Obj); @@ -213,7 +254,7 @@ void MachODumper::dumpHeader(std::unique_ptr &Y) { Y->Header.reserved = 0; } -void MachODumper::dumpLoadCommands(std::unique_ptr &Y) { +Error MachODumper::dumpLoadCommands(std::unique_ptr &Y) { for (auto LoadCmd : Obj.load_commands()) { MachOYAML::LoadCommand LC; const char *EndPtr = LoadCmd.Ptr; @@ -223,7 +264,11 @@ void MachODumper::dumpLoadCommands(std::unique_ptr &Y) { sizeof(MachO::load_command)); if (Obj.isLittleEndian() != sys::IsLittleEndianHost) MachO::swapStruct(LC.Data.load_command_data); - EndPtr = processLoadCommandData(LC, LoadCmd); + if (Expected ExpectedEndPtr = + processLoadCommandData(LC, LoadCmd)) + EndPtr = *ExpectedEndPtr; + else + return ExpectedEndPtr.takeError(); break; #include "llvm/BinaryFormat/MachO.def" } @@ -237,6 +282,7 @@ void MachODumper::dumpLoadCommands(std::unique_ptr &Y) { LC.ZeroPadBytes = RemainingBytes; Y->LoadCommands.push_back(std::move(LC)); } + return Error::success(); } void MachODumper::dumpLinkEdit(std::unique_ptr &Y) { -- GitLab From b3f168274d8fee531af6d28d5977ffad119f7791 Mon Sep 17 00:00:00 2001 From: Jon Roelofs Date: Wed, 22 Apr 2020 12:56:22 -0600 Subject: [PATCH 124/910] [docs] Document lit's --timeout=N flag --- llvm/docs/CommandGuide/lit.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/llvm/docs/CommandGuide/lit.rst b/llvm/docs/CommandGuide/lit.rst index bbd739f28d42..86f1fdae3b6a 100644 --- a/llvm/docs/CommandGuide/lit.rst +++ b/llvm/docs/CommandGuide/lit.rst @@ -165,10 +165,8 @@ SELECTION OPTIONS .. option:: --max-time=N Spend at most ``N`` seconds (approximately) running tests and then terminate. - -.. option:: --shuffle - - Run the tests in a random order. + Note that this is not an alias for :option:``--timeout=N``; the two are + different kinds of maximums. .. option:: --num-shards=M @@ -187,6 +185,16 @@ SELECTION OPTIONS must be in the range ``1..M``. The environment variable ``LIT_RUN_SHARD`` can also be used in place of this option. +.. option:: --shuffle + + Run the tests in a random order. + +.. option:: --timeout=N + + Spend at most ``N`` seconds (approximately) running each individual test. + ``0`` means no time limit, and ``0`` is the default. Note that this is not an + alias for :option:``--max-time=N``; the two are different kinds of maximums. + .. option:: --filter=REGEXP Run only those tests whose name matches the regular expression specified in -- GitLab From 430b00954c674241f16549290ab49cc69f93a431 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Wed, 22 Apr 2020 13:58:17 -0400 Subject: [PATCH 125/910] [libc++] Add support for blocks in std::function rdar://14390808 --- libcxx/include/functional | 76 ++++++++++ .../function.objects/func.blocks.sh.cpp | 142 ++++++++++++++++++ 2 files changed, 218 insertions(+) create mode 100644 libcxx/test/libcxx/utilities/function.objects/func.blocks.sh.cpp diff --git a/libcxx/include/functional b/libcxx/include/functional index b13992f94e2b..f03ba8bb5541 100644 --- a/libcxx/include/functional +++ b/libcxx/include/functional @@ -508,6 +508,10 @@ POLICY: For non-variadic implementations, the number of arguments is limited #include <__functional_base> +#if defined(_LIBCPP_HAS_EXTENSION_BLOCKS) && !defined(_LIBCPP_HAS_OBJC_ARC) +#include +#endif + #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) #pragma GCC system_header #endif @@ -1484,6 +1488,12 @@ template _LIBCPP_INLINE_VISIBILITY bool __not_null(function<_Fp> const& __f) { return !!__f; } +#ifdef _LIBCPP_HAS_EXTENSION_BLOCKS +template +_LIBCPP_INLINE_VISIBILITY +bool __not_null(_Rp (^__p)(_Args...)) { return __p; } +#endif + } // namespace __function #ifndef _LIBCPP_CXX03_LANG @@ -2245,6 +2255,72 @@ template class __policy_func<_Rp(_ArgTypes...)> #endif // _LIBCPP_NO_RTTI }; +#if defined(_LIBCPP_HAS_EXTENSION_BLOCKS) && !defined(_LIBCPP_HAS_OBJC_ARC) + +template +class __func<_Rp1(^)(_ArgTypes1...), _Alloc, _Rp(_ArgTypes...)> + : public __base<_Rp(_ArgTypes...)> +{ + typedef _Rp1(^__block_type)(_ArgTypes1...); + __block_type __f_; + +public: + _LIBCPP_INLINE_VISIBILITY + explicit __func(__block_type const& __f) + : __f_(__f ? Block_copy(__f) : (__block_type)0) + { } + + // [TODO] add && to save on a retain + + _LIBCPP_INLINE_VISIBILITY + explicit __func(__block_type __f, const _Alloc& /* unused */) + : __f_(__f ? Block_copy(__f) : (__block_type)0) + { } + + virtual __base<_Rp(_ArgTypes...)>* __clone() const { + _LIBCPP_ASSERT(false, + "Block pointers are just pointers, so they should always fit into " + "std::function's small buffer optimization. This function should " + "never be invoked."); + return nullptr; + } + + virtual void __clone(__base<_Rp(_ArgTypes...)>* __p) const { + ::new (__p) __func(__f_); + } + + virtual void destroy() _NOEXCEPT { + if (__f_) + Block_release(__f_); + __f_ = 0; + } + + virtual void destroy_deallocate() _NOEXCEPT { + _LIBCPP_ASSERT(false, + "Block pointers are just pointers, so they should always fit into " + "std::function's small buffer optimization. This function should " + "never be invoked."); + } + + virtual _Rp operator()(_ArgTypes&& ... __arg) { + return __invoke(__f_, _VSTD::forward<_ArgTypes>(__arg)...); + } + +#ifndef _LIBCPP_NO_RTTI + virtual const void* target(type_info const& __ti) const _NOEXCEPT { + if (__ti == typeid(__func::__block_type)) + return &__f_; + return (const void*)nullptr; + } + + virtual const std::type_info& target_type() const _NOEXCEPT { + return typeid(__func::__block_type); + } +#endif // _LIBCPP_NO_RTTI +}; + +#endif // _LIBCPP_HAS_EXTENSION_BLOCKS && !_LIBCPP_HAS_OBJC_ARC + } // __function template diff --git a/libcxx/test/libcxx/utilities/function.objects/func.blocks.sh.cpp b/libcxx/test/libcxx/utilities/function.objects/func.blocks.sh.cpp new file mode 100644 index 000000000000..a608d42eb515 --- /dev/null +++ b/libcxx/test/libcxx/utilities/function.objects/func.blocks.sh.cpp @@ -0,0 +1,142 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// std::function support for the "blocks" extension + +// UNSUPPORTED: c++98, c++03 +// REQUIRES: has-fblocks + +// RUN: %{build} -fblocks +// RUN: %{run} + +#include +#include +#include + +#include "test_macros.h" +#include "count_new.h" + + +struct A { + static int count; + int id_; + explicit A(int id) { ++count; id_ = id; } + A(const A &a) { id_ = a.id_; ++count; } + ~A() { id_ = -1; --count; } + int operator()() const { return -1; } + int operator()(int i) const { return i; } + int operator()(int, int) const { return -2; } + int operator()(int, int, int) const { return -3; } + int id() const { return id_; } +}; + +int A::count = 0; + +int g(int) { return 0; } + +int main(int, char**) +{ + // swap + { + std::function f1 = g; + std::function f2 = ^(int x) { return x + 1; }; + assert(globalMemCounter.checkOutstandingNewEq(0)); + assert(*f1.target() == g); + assert(*f2.target() != 0); + swap(f1, f2); + assert(globalMemCounter.checkOutstandingNewEq(0)); + assert(*f1.target() != 0); + assert(*f2.target() == g); + } + + // operator bool + { + std::function f; + assert(!f); + f = ^(int x) { return x+1; }; + assert(f); + } + + // operator() + { + std::function r1(^{ return 4; }); + assert(r1() == 4); + } + { + __block bool called = false; + std::function r1(^{ called = true; }); + r1(); + assert(called); + } + { + __block int param = 0; + std::function r1(^(int x){ param = x; }); + r1(4); + assert(param == 4); + } + { + std::function r1(^(int x){ return x + 4; }); + assert(r1(3) == 7); + } + { + __block int param1 = 0; + __block int param2 = 0; + std::function r1(^(int x, int y){ param1 = x; param2 = y; }); + r1(3, 4); + assert(param1 == 3); + assert(param2 == 4); + } + { + std::function r1(^(int x, int y){ return x + y; }); + assert(r1(3, 4) == 7); + } + + // swap + { + std::function f1 = A(999); + std::function f2 = ^(int x) { return x + 1; }; + assert(A::count == 1); + assert(globalMemCounter.checkOutstandingNewEq(1)); + assert(f1.target()->id() == 999); + assert((*f2.target())(13) == 14); + f1.swap(f2); + assert(A::count == 1); + assert(globalMemCounter.checkOutstandingNewEq(1)); + assert((*f1.target())(13) == 14); + assert(f2.target()->id() == 999); + } + assert(globalMemCounter.checkOutstandingNewEq(0)); + assert(A::count == 0); + + // operator== and operator!= + { + std::function f; + assert(f == nullptr); + assert(nullptr == f); + f = ^(int x) { return x + 1; }; + assert(f != nullptr); + assert(nullptr != f); + } + + // target + { + int (^block)(int) = Block_copy(^(int x) { return x + 1; }); + std::function f = block; + assert(*f.target() == block); + assert(f.target() == 0); + Block_release(block); + } + + // target_type + { + std::function f = ^(int x) { return x + 1; }; + assert(f.target_type() == typeid(int(^)(int))); + } + + return 0; +} -- GitLab From 264c07ef77667d5c90a75e95cc71c370afb86083 Mon Sep 17 00:00:00 2001 From: Puyan Lotfi Date: Sat, 11 Apr 2020 22:09:08 -0700 Subject: [PATCH 126/910] [llvm][MIRVRegNamer] Avoid collisions across jump table indices. Hash Jump Table Indices uniquely within a basic block for MIR Canonicalizer / MIR VReg Renamer passes. Differential Revision: https://reviews.llvm.org/D77966 --- llvm/lib/CodeGen/MIRVRegNamerUtils.cpp | 2 +- .../MIR/AArch64/mir-canon-jump-table.mir | 33 +++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp index 9b45a0d5669f..54441301d65b 100644 --- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp +++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp @@ -72,6 +72,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) { return MO.getOffset() | (MO.getTargetFlags() << 16); case MachineOperand::MO_FrameIndex: case MachineOperand::MO_ConstantPoolIndex: + case MachineOperand::MO_JumpTableIndex: return llvm::hash_value(MO); // We could explicitly handle all the types of the MachineOperand, @@ -82,7 +83,6 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) { // TODO: Handle the following Index/ID/Predicate cases. They can // be hashed on in a stable manner. - case MachineOperand::MO_JumpTableIndex: case MachineOperand::MO_CFIIndex: case MachineOperand::MO_IntrinsicID: case MachineOperand::MO_Predicate: diff --git a/llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir b/llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir new file mode 100644 index 000000000000..dbb6b62b68bb --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir @@ -0,0 +1,33 @@ +# RUN: llc -run-pass mir-canonicalizer -verify-machineinstrs -mtriple aarch64-unknown-linux-gnu -o - %s | FileCheck %s +... +--- +name: foo +alignment: 16 +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.0', '%bb.1'] + - id: 1 + blocks: [ '%bb.2', '%bb.3' ] + - id: 2 + blocks: [ '%bb.3', '%bb.7'] + - id: 3 + blocks: [ '%bb.2', '%bb.3' ] +body: | + bb.0: + bb.1: + bb.2: + bb.3: + bb.7: + ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.0 + ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.1 + ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.2 + ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.3 + %a:_(p0) = G_JUMP_TABLE %jump-table.0 + %b:_(p0) = G_JUMP_TABLE %jump-table.1 + %c:_(p0) = G_JUMP_TABLE %jump-table.2 + %d:_(p0) = G_JUMP_TABLE %jump-table.3 + +... + -- GitLab From 7d1ee639cb9efea364bec90afe4d1161ec624a7f Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Wed, 22 Apr 2020 13:33:02 +0200 Subject: [PATCH 127/910] [clangd] Fix a crash for accessing a null template decl returned by findExplicitReferences. Summary: Fixes https://github.com/clangd/clangd/issues/347. Reviewers: kadircet Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D78626 --- clang-tools-extra/clangd/FindTarget.cpp | 10 ++++++---- .../clangd/unittests/FindTargetTests.cpp | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/clang-tools-extra/clangd/FindTarget.cpp b/clang-tools-extra/clangd/FindTarget.cpp index 1ff20e6e4bc1..be3306f3fc78 100644 --- a/clang-tools-extra/clangd/FindTarget.cpp +++ b/clang-tools-extra/clangd/FindTarget.cpp @@ -860,15 +860,17 @@ public: // TemplateArgumentLoc is the only way to get locations for references to // template template parameters. bool TraverseTemplateArgumentLoc(TemplateArgumentLoc A) { + llvm::SmallVector Targets; switch (A.getArgument().getKind()) { case TemplateArgument::Template: case TemplateArgument::TemplateExpansion: + if (const auto *D = A.getArgument() + .getAsTemplateOrTemplatePattern() + .getAsTemplateDecl()) + Targets.push_back(D); reportReference(ReferenceLoc{A.getTemplateQualifierLoc(), A.getTemplateNameLoc(), - /*IsDecl=*/false, - {A.getArgument() - .getAsTemplateOrTemplatePattern() - .getAsTemplateDecl()}}, + /*IsDecl=*/false, Targets}, DynTypedNode::create(A.getArgument())); break; case TemplateArgument::Declaration: diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp index f943772e052e..03cdc02fbb18 100644 --- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp +++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp @@ -1286,6 +1286,20 @@ TEST_F(FindExplicitReferencesTest, All) { "1: targets = {}\n" "2: targets = {T}\n" }, + // unknown template name should not crash. + {R"cpp( + template